JPS61207050A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61207050A JPS61207050A JP4870185A JP4870185A JPS61207050A JP S61207050 A JPS61207050 A JP S61207050A JP 4870185 A JP4870185 A JP 4870185A JP 4870185 A JP4870185 A JP 4870185A JP S61207050 A JPS61207050 A JP S61207050A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- region
- emitter
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims 6
- 238000004519 manufacturing process Methods 0.000 title claims 2
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 230000001681 protective effect Effects 0.000 claims abstract description 8
- 239000012808 vapor phase Substances 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052681 coesite Inorganic materials 0.000 abstract description 6
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 6
- 239000000377 silicon dioxide Substances 0.000 abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 6
- 229910052682 stishovite Inorganic materials 0.000 abstract description 6
- 229910052905 tridymite Inorganic materials 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- 238000002347 injection Methods 0.000 abstract description 3
- 239000007924 injection Substances 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
- 230000002265 prevention Effects 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- -1 phosphorus ions Chemical class 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000010405 reoxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
バイポーラトランジスタの深いエミッタ領域形゛成のた
めの高温気相拡散用の厚いマスク膜と、Ｊ−ＦＥＴの浅
いゲート領域形成のためのイオン注入用の薄い保護膜と
をＳｔ、Ｎ、ＩＩ！とＳ ｉ ｏ、 ＩＩ！の２層構造
にて一体的に形成し工程の簡単化及びバイポーラトラン
ジスタのり、Ｅ変動を抑えたプロセスである。[Detailed Description of the Invention] [Summary] A thick mask film for high-temperature vapor phase diffusion to form a deep emitter region of a bipolar transistor and a thin protection film for ion implantation to form a shallow gate region of a J-FET. St, N, II! and Sio, II! This process simplifies the process by integrally forming a two-layer structure, and suppresses variations in the thickness and E of bipolar transistors.
本発明は高耐圧バイポーラトランジスタと接合型電界効
果形トランジスタ（Ｊ −Ｆ ＥＴと称す）とを同一基
板上に形成するためのプロセスに関する。The present invention relates to a process for forming a high voltage bipolar transistor and a junction field effect transistor (referred to as J-FET) on the same substrate.
高耐圧バイポーラトランジスタはベース領域及びエミッ
タ領域が深く、エミッタの形成はりンイオンを高温の気
相拡散で形成される。一方ＰチャネルのＪ−ＦＥＴのゲ
ート領域は薄＜Ａｓ等のイオンを注入することで形成さ
れる。第２図の断面図を利用して説明する。A high-voltage bipolar transistor has a deep base region and an emitter region, and the emitter is formed by high-temperature vapor phase diffusion of phosphorus ions. On the other hand, the gate region of a P-channel J-FET is formed by implanting ions such as As. This will be explained using the sectional view of FIG.
第２図（ａ）
基板表面のエピタキシャル層２内にベース領域３とドレ
イン、ソースコンタクト領域４．５とを形成後、基板表
面前面に例えば４０００人の厚い５ｉｏ２ｙ！６を熱酸
化で形成し、エミツタ窓７を形成後、リンイオンを二層
よ上辺気相拡散にて基板中に拡散せしめ深いエミッタ領
域８を形成する。FIG. 2(a) After forming the base region 3 and the drain and source contact regions 4.5 in the epitaxial layer 2 on the surface of the substrate, a thick 5io2y! 6 is formed by thermal oxidation, and after forming an emitter window 7, phosphorus ions are diffused into the substrate by vapor phase diffusion over the two layers to form a deep emitter region 8.
第２図０１１）
次にＪ−ＦＥＴ側にチャネル領域９とＮ型のゲート領域
１０を形成するのに、厚いＳｉＯっ膜を一部除去し、イ
オン注入用の薄い保護膜として例えば５００人の５ｉ０
２１１を再度例えば９００℃で熱酸化で形成し、その上
にレジスト１２をマスクとして形成しＡｓイオンを注入
し薄いゲート領域１０及び９を形成する。その後Ｂ４イ
オンを注入しチャネルを形成する。エネルギー、ドーズ
は適宜えらぶ。(Fig. 2 011) Next, to form a channel region 9 and an N-type gate region 10 on the J-FET side, a portion of the thick SiO film is removed and used as a thin protective film for ion implantation using, for example, 500 5i0
211 is again formed by thermal oxidation at, for example, 900° C., a resist 12 is formed thereon as a mask, and As ions are implanted to form thin gate regions 10 and 9. After that, B4 ions are implanted to form a channel. Select energy and dose appropriately.
第２図（Ｃ１
各電極を形成する前に全面にＣＶＤ法にて５ｉ０２膜１
３を４０００人形成し、その後各電極窓を形成して電極
を形成する。Figure 2 (C1) Before forming each electrode, a 5i02 film 1 is applied to the entire surface using the CVD method.
3, and then each electrode window is formed to form an electrode.
深いエミッタ領域８の形成のためには、高温（１０００
℃〜１０５０℃）の熱処理が必要故、そのマスクとして
は厚いＳｉＯり膜６を利用しなければならない。一方で
Ｊ−ＦＥＴのゲート領域は浅いのでイオン注入が通し、
そのためには上記厚い５ｉ０２膜６の上からイオン注入
できず、しかたなくＳｔＯ，膜１１の９００℃の再熱酸
化という工程をとっている。ところがこの熱酸化にて、
エミッタ領域の深さが変化しベース幅が変動し、バイポ
ーラトランジスタの電流増幅率り、Ｅの変動が大きくな
るのである。In order to form the deep emitter region 8, a high temperature (1000
Since heat treatment at a temperature of 1050°C to 1050°C is required, a thick SiO film 6 must be used as a mask. On the other hand, since the gate region of J-FET is shallow, ion implantation can pass through.
For this purpose, ions cannot be implanted from above the thick 5i02 film 6, so a process of re-thermal oxidation of the StO film 11 at 900° C. is required. However, in this thermal oxidation,
The depth of the emitter region changes, the base width changes, and the current amplification factor, E, of the bipolar transistor fluctuates greatly.
またＪ−ＦＥＴのために薄い５ｉ０２膜１１が必要故、
電極形成前にＣＶＤ法の酸化膜１３を形成する必要があ
り、その結果バイポーラトランジスタ上の５１０１２膜
はＳｔＯ，膜６と１３の二層となり全部で８０００〜９
０００人と厚くなり、そのようなところへの電極形成は
窓開精度が悪く、且つＡｆｆｉ膜のカバレージも悪くな
る。Also, since a thin 5i02 film 11 is required for the J-FET,
Before forming the electrodes, it is necessary to form an oxide film 13 by CVD method, and as a result, the 51012 film on the bipolar transistor becomes two layers of StO, films 6 and 13, with a total of 8000 to 9
The electrode formation in such a place results in poor window opening precision and poor coverage of the Affi film.
本発明は上記問題点を解決することを目的とし、エミッ
タ８の拡散用マスク膜とゲート注入用の保護膜とを第１
．第２の絶縁膜の２層構造で一体化形成しているのであ
る。The present invention aims to solve the above-mentioned problems, and the present invention aims to solve the above-mentioned problems by using a diffusion mask film for the emitter 8 and a protective film for gate injection as a first layer.
．． It is integrally formed with a two-layer structure of the second insulating film.
ゲート注入用の保護膜としての薄いＳ ｉ ０２膜とエ
ミッタ拡散マスク膜としての厚いＳ Ｌ ３ Ｎ４−と
の２層構造にエミッタ用窓を形成し拡散した後、Ｓ ｉ
３ Ｎ４膜を全面除去し、残ったＳｉＯ２膜を保護膜と
してゲート注入を行なって、最後は低温のＣＶＤ法でＳ
ｉＯユ膜を形成している。よって再度高温熱酸化をエミ
ッタ領域拡散後行なう必要がないのでバイポーラトラン
ジスタのり、ｆ制御が容易で、且つ電極窓を厚いＳｉＯ
ユ膜に形成することも必要ない。After forming and diffusing an emitter window in a two-layer structure of a thin S i 02 film as a protective film for gate injection and a thick S L 3 N4- as an emitter diffusion mask film, the Si
3 The N4 film is completely removed, the remaining SiO2 film is used as a protective film for gate implantation, and finally S is removed using a low-temperature CVD method.
It forms an iOyu film. Therefore, there is no need to perform high-temperature thermal oxidation again after diffusing the emitter region, so it is easy to control the thickness and f of the bipolar transistor, and the electrode window can be made of thick SiO
It is also not necessary to form a membrane.
第１図は本発明の一実施例の各工程断面図である。 FIG. 1 is a cross-sectional view of each step in an embodiment of the present invention.
第１図（ａ）
Ｐ型シリコン基板１上のＮ型エピタキシャル層２上に第
１の絶縁膜として５００〜１０００人の５ｉ０２膜２１
を形成しそのｓｔｏ、膜２１を介してイオン注入により
Ｐ型ベース領域３、ソース、ドレインコンタクト領域４
．５を形成後、第２の絶縁膜として約２０００人のＳ
ｉ ３ Ｎ４膜２２を以り１九で形成する。そしてドラ
イエツチングにより第１．第２の絶縁膜２１．２２をバ
ターニングしてエミッタ拡散用窓２３を形成する。そし
て１０００℃の気相拡散にも不純物リンを導入し、ラン
ニングにより１．５μの深いエミッタ領域８を形成する
。このときＳ ｉ Ｏ２膜が窓内に２゜００人程度形成
されるが図面では省略している。FIG. 1(a) A 5i02 film 21 of 500 to 1000 layers is formed as a first insulating film on the N-type epitaxial layer 2 on the P-type silicon substrate 1.
P-type base region 3, source and drain contact regions 4 are formed by ion implantation through the sto and film 21.
．． After forming 5, approximately 2000 S.
An i 3 N4 film 22 is then formed in step 19. Then, by dry etching, the first. The second insulating films 21 and 22 are patterned to form an emitter diffusion window 23. Then, impurity phosphorus is also introduced through vapor phase diffusion at 1000° C., and a deep emitter region 8 of 1.5 μm is formed by running. At this time, a SiO2 film of about 2000 layers is formed inside the window, but this is omitted in the drawing.
第１図（ｂ）
次にＳ ｉ３ Ｎ４膜２２をウォシュアウトにより除去
し、ＳｉＯユ膜２１を露出させ、その上にレジストパタ
ーンを形成しチャネル領域にレジストパターンでホウ素
をイオン注入し、及び異なるレジスタパターン２４にて
窓２５を介してゲート領域１０にＡｓをイオン注入する
。この場合イオン注入用の保護膜はＳ ｉＯ，膜２１を
使用するので従来の如き再酸化はない。よってエミッタ
の拡散はなくｈＦＥの制御が容易である。FIG. 1(b) Next, the Si3N4 film 22 is removed by washout, the SiO2 film 21 is exposed, a resist pattern is formed on it, boron ions are implanted into the channel region using the resist pattern, and a different As is ion-implanted into the gate region 10 through the window 25 in the resistor pattern 24 . In this case, since SiO film 21 is used as the protective film for ion implantation, there is no reoxidation as in the conventional case. Therefore, there is no emitter diffusion and hFE can be easily controlled.
第１図（Ｃｌ
レジスト除去後、前面にＣＶＤ法にて５ｉ０２膜２５を
３０００人程度形成し、同時にその時の低温度８００℃
にてゲート、チャネル領域の活性化を行なう。そして各
電極窓を形成し、Ａｌの電極を形成する。この時酸化膜
２１．２５は全部で４０００人程度色落いので、電極窓
の形成精度は高く、またＡｌのステップカバレージも良
好である。Figure 1 (After removing the Cl resist, approximately 3,000 5i02 films 25 are formed on the front surface using the CVD method, and at the same time the low temperature of 800°C
Activate the gate and channel regions. Then, each electrode window is formed, and an Al electrode is formed. At this time, the oxide films 21 and 25 are discolored by about 4,000 layers in total, so the precision in forming the electrode window is high, and the step coverage of Al is also good.
以上述べたように、高耐圧バイポーラトランジスタのｈ
ＦＥの制御性が良（、電極窓の精度、Ａｌ電極のステッ
プカバレージが良い。As mentioned above, h of high voltage bipolar transistor
Good controllability of FE (good electrode window accuracy, good step coverage of Al electrodes.
第１図は本発明の各工程断面図、
第２図は従来の各工程断面図である。
図中、１は基板、８はエミッタ領域、１０はゲート領域
、２１は第１の絶縁膜、２２は第２の絶縁膜である。FIG. 1 is a sectional view of each step of the present invention, and FIG. 2 is a sectional view of each step of the conventional method. In the figure, 1 is a substrate, 8 is an emitter region, 10 is a gate region, 21 is a first insulating film, and 22 is a second insulating film.
Claims (1)
形電界効果型トランジスタとを形成する際に、 該基板上に、該接合形電界効果型トランジスタのゲート
領域形成のイオン注入の保護膜としての薄い第１の絶縁
膜（２１）を形成し、 該第１の絶縁膜上に気相拡散用マスク膜としての厚い第
２の絶縁膜（２２）を形成し、 該第２の絶縁膜にエミッタ用窓を形成し、それを介して
不純物を該半導体基板中に気相拡散して深いエミッタ領
域（８）を形成し、 該第２の絶縁膜を除去し、 該第１の絶縁膜上にゲートイオン注入用窓を有するレジ
スト膜を形成し、それを介して不純物イオンを該半導体
基板中にイオン注入し、浅いゲート領域（１０）を形成
する工程を有することを特徴とする半導体装置の製造方
法。[Claims] When a bipolar transistor and a junction field effect transistor are formed on the surface of the same semiconductor substrate, a protective film for ion implantation to form a gate region of the junction field effect transistor is formed on the substrate. forming a thin first insulating film (21), forming a thick second insulating film (22) as a vapor phase diffusion mask film on the first insulating film, and forming a thick second insulating film (22) on the second insulating film; forming an emitter window and vapor phase diffusing impurities into the semiconductor substrate through the emitter window to form a deep emitter region (8); removing the second insulating film; and removing the second insulating film on the first insulating film. A semiconductor device comprising the steps of forming a resist film having a gate ion implantation window in the semiconductor substrate, and implanting impurity ions into the semiconductor substrate through the resist film to form a shallow gate region (10). Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4870185A JPS61207050A (en) | 1985-03-12 | 1985-03-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4870185A JPS61207050A (en) | 1985-03-12 | 1985-03-12 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61207050A true JPS61207050A (en) | 1986-09-13 |
Family
ID=12810611
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4870185A Pending JPS61207050A (en) | 1985-03-12 | 1985-03-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61207050A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009521804A (en) * | 2005-12-22 | 2009-06-04 | アナログ デバイセス インコーポレーテッド | JFET with drain and / or source deformation implant |
-
1985
- 1985-03-12 JP JP4870185A patent/JPS61207050A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009521804A (en) * | 2005-12-22 | 2009-06-04 | アナログ デバイセス インコーポレーテッド | JFET with drain and / or source deformation implant |
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