JPS61206341A - Frame synchronization method and frame circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a serial
al) A method of frame synchronization of data groups and a frame circuit for achieving such frame synchronization.

It is well known that frame circuits are provided to detect frame patterns in serial data sets and to achieve frame synchronization based on this detection. Ideally, frame patterns can be easily detected and do not occur in the remainder of the data group. However, in practice, such an ideal
Bandwidth limitations and explicit data transfer requirements, i.e.
It is rare that the restriction is due to other constraints beyond the control of the frame. As a result, the frame time or frame reproduction time is very important for 7-framed transmission of serial data.

As is well known, this gap is the time required to detect and initialize a frame pattern in a data group or to synchronize with it in the event of a loss of frame synchronization during transmission.

If the frame pattern extends over a relatively large number of bits of the data group, a delay will occur before a sufficient number of bits are examined to form a poLential frame pattern. This delay is repeated each time the presence of sync slips and bit settings are checked for suitability as a frame pattern, lengthening the frame time.

To avoid such delays and long frame times,
It is known to provide one frame pattern detector for a frame pattern of length n bits, in which at least n candidate bits are stored from each of 11 consecutive frames. At the end of this storage or candidate bit collection period, where no frame synchronization slips are allowed, each candidate bit sequence with a corresponding candidate bit from the n consecutive 7 frames that make up the frame pattern is valid as a frame pattern. will be evaluated. Any candidate pit sequences that do not correspond to a frame bit pattern are not considered further, and frame synchronization slips are optionally effected through one or more bit positions. This sequence is repeated until all possible bit positions are considered for suitability as a frame pattern and no more than one candidate bit sequence is removed. This is then viewed as a frame bit pattern and the final synchronization slip is made to synchronize to this.

Although parallel frame train schemes of the type described above can achieve fast frame times, they require great complexity and result in expensive circuitry in their implementation. As a result, such complex schemes are preferably avoided in practice.

It is therefore an object of the invention to provide an improved method of frame synchronization and an improved frame circuit.

According to the present invention, a method for frame synchronization of a serial data group including a predetermined frame pattern is provided, comprising the following steps. That is, it detects a frame pattern in a data group, generates an error signal in response to the non-detection of the frame pattern, generates a synchronization slip depending on the error signal, and detects a frame pattern for a previous synchronization slip. Get compensation.

According to the present invention, during 7-raming, a synchronization slip occurs in response to each candidate bit detected that does not match the frame pattern, and compensation ensures that the setting of the next candidate bit is properly selected without incurring long delays. is provided by a frame pattern detector to adapt to the occurrence of each sync slip. Implementation of the second method can be accomplished with relatively little circuitry and complexity, as explained in detail below.

Preferred steps for providing compensation include the following steps. That is, storing a large number of consecutive bits of the data group, generating at least one selection signal depending on the occurrence of a synchronization slip, and depending on the selection signal, storing a large number of consecutive bits of the data group for the detection of a frame pattern. Selecting one of a number of stored consecutive bits.

A preferred method also includes the following steps.

generating an in-frame (in-fra+ae) signal in the absence of an error signal within at least one predetermined period; generating a synchronous slip in response to each error signal in the absence of an in-frame signal; generating and terminating the in-frame signal in response to a predetermined number of error signals occurring during a predetermined period of time in the in-frame signal.

The present invention also provides a frame circuit having the following configuration for frame synchronization of a serial data group including a predetermined frame pattern. 207243; means responsive to the clock signal to detect frame patterns in the data group;
means for generating a synchronization error signal in response to the detection means not detecting the frame pattern and thereby controlling the timing means to generate a synchronization slip and change the phase of the clock signal associated with the data group; A means of responding to a signal. Here, the detection means comprises means for compensating for previous synchronization slips.

In one embodiment of the invention, the timing means includes the following means. That is, a first frequency dividing means for frequency dividing one signal by the bit ratio of the data group by a first predetermined element to generate one control signal, and @2 frequency dividing means for frequency dividing one signal by the bit ratio of the data group to generate one control signal Second frequency dividing means for frequency dividing the control signal by a predetermined element and means for frequency dividing by a third predetermined element depending on the clock signal to modify the frequency division by the first frequency dividing means. . wherein the means responsive to the error signal for controlling the timing means comprises a first
$ to generate a synchronization slip in the frequency division means of
It is equipped with means for frequency division by three predetermined elements.

A preferred means for compensating for previous synchronization slips comprises the following arrangement. namely, means for storing a large number of consecutive bits of a data group, means responsive to an error signal to generate at least one selection signal in dependence on the occurrence of a synchronization slip, and means for storing a plurality of consecutive bits of a data group for frame pattern detection. Means responsive to a selection signal for selecting one of the stored plurality of consecutive bits.

Preferred detection means are responsive to a series of at least three bits of the data group to detect a frame pattern, and means for storing a plurality of consecutive bits of the data group are responsive to at least three bits of the data group for each of said series of at least three bits. and means for storing 63 consecutive bits.

Preferred means for responding to an error signal include the following means. means for counting the pulses of the clock signal during the presence and absence of the error signal; tIS of the clock signal counted by the counting means during the absence of the error signal;
means for generating an in-frame signal in response to a predetermined number of pulses of i; means for generating a synchronous slip command signal in response to an error signal during the absence of an in-frame signal; and means for generating a synchronous slip command signal. , means for terminating the in-frame signal in response to counting means for counting a predetermined number of @2 pulses of the clock signal during the presence of the error signal within a third predetermined period of the clock signal.

Examples The present invention will be further understood from the following description in conjunction with the accompanying drawings.

Regarding the tISi diagram, a known form of multi-array for multiplexing bit groups from DS1 to DS3 level is shown. As is known, the DS1 bit group is 1
．． It consists of bits at a bit rate of 544 MB/s, for example constituted by a T1 carrier signal containing a 248-bit voice channel signal and associated frame bits. Four such S1 bit groups are multiplexed together by multiplexers MPX 1-2 to create one D32 bit group at a bit rate of 6.312 MB/s, two of which are As shown in the figure. 7 such 82 bit groups is 44.736M
Multiplexed together by one multiplexer - MPX 2-3 to create D83 bit groups at a bit rate of B/s. Thus, the D83 bit group can include 28 DSI bit groups.

Each multiplexer-MPXI-2 creates a DS2S2 piff by sampling the four inputs, or a set of D32 bits by inverting all other bits and doing so 12 times regularly and adding one auxiliary bit. I'm making it.

Thus, if each auxiliary focus is denoted by "toI" and the four-man input focus is denoted by "xl" to "x41", then the DS2S2 piff has the following form: +1XIX2X3X4XIX2X3X4XIX2X3X
4XIX2X3X4XIX2X3X4XIX2X3X4
XIX2X3X4XIX2X3X4XIX2X3X4X
IX2X3X4XIX2X3X4XIX2X3X41+
1X2X3X4 For convenience, this will be expressed as follows.

+1[(XIX2X3X4)X 12]H[(XIX2
X3X4)X12] -・-Multiplexer-MPX
2-3 is repeated 12 times regularly by sampling 7 or taking 1 bit from each DS2S2 pif of each sample to yield a series of 84 bits with 1 auxiliary bit added. By returning it, a DS3 bit group is created. eight of these eight
The 5-bit sequence forms one frame containing 8 auxiliary bits, and seven of these 7-frames form one master 7-frame. In each frame,
8 auxiliary focus forms the following data pattern.

Mi F, Ci, FOCi2 Fo Ci3
F.

However, i=1 to 7 Mi forms one master 7 frame word pattern, and will be described below as M bits.

Ci 1 HCi z Ci s is the tripled stuff/no-stuff for subordinate i of DS2 in the current master frame.
This is a dependent control bit and will be described below as the C bit.

Fl and Fo indicate the 1 and 0 bits forming the respective F-bit frame patterns.

D63 to enable frame synchronization for proper multiplexing
The 63-bit F-bit frame pattern has consecutive F, F, F, F in each frame.
The F bit frame pattern 1 consists of consecutive bits 1001100110011001, . . .

In the prior art, such a frame bit pattern is detected in the DS3 bit set, and based on detection and statistical confirmation (i.e., the pattern persists for at least a predetermined period of time), the system is within 7 frames. Therefore, multiplexing is achieved.

The problem that the present invention seeks to solve is that adjacent incompatible DS1 rings produce bit patterns in the DS3 bit group that mimic this frame bit pattern. As a natural result, a very long 7-raming playback time is obtained.

The problem is that if there is an input adjacent to one multiplexer MPXI-2 that has two adjacent incompatible DS1+j links, i.e., one multiplexer that permanently has a buried 1 or 0, then the resulting DS2S2 generated by the multiplexer
Each of the seven frames of Biff would have the following form, for example:

+1 [(IOXX)
The 2S2 piff results from the multiplexer's alternating bit flips of non-compliant DSI link bits.

Multiplexer with 12 inputs between consecutive DS2 auxiliary bits H - sampling by MPXl-2 and multiplexer with 12 inputs between consecutive DS3 auxiliary bits
Sampling by MPX2-3 consists of D83 bit group and D
The conclusion is that there is a direct relationship between the focus positions in the S1 bit group. Due to this result and the fact that the F bits of the frame bit pattern in the DS3 bit group are searched within the alternating 85 bit sequence of the D83 bit group (i.e. there are four F bits in each DS3 frame), the D32 The bit group is DS2 auxiliary bin)H
generates a pattern in the D33 bit group that is responsive to the 7-ram bit pattern during short terms until interrupted by the occurrence of D33. Detection of this simulated frame bit pattern introduces additional 7 reaming times and delays detection of the true DS37 ream bit pattern.

This condition is exacerbated with many non-compliant DSI links. With four unmatched DSL links, the frame time can be 48 times longer than a system where random data is present on every D81 human.

like this! ! Long frame spacing can occur despite the advantages of the 7-ram bit pattern itself, which allows fast 7-raming to be achieved in the absence of a simulated data bit pattern.

In order to avoid such a long 7-raming pit pattern, the present invention provides not only the 7-raming pits themselves, but also the rapid development of a simulated data bit pattern from consideration as a true 7-raming pit pattern in the darkness of the 7-raming process. It utilizes the characteristics of predetermined bits in the Bissi group to facilitate easy removal. In this embodiment of the invention, this predetermined feature is the nature of the auxiliary focus C of the D83 bit group.

As already mentioned, there are three triplex C-focuses in each DS37 frame, C1 to C1.

Since they are triplexed, they have the property that in the absence of errors, C,=C2=C, ie, the three C bits are all 0 or all 1. Furthermore, the C bit is D in relation to the F bit frame pattern.
It has a fixed position in the S3 frame. This S3 auxiliary bit sequence in each 7 frames actually has the following form.

Mi　F+　C1IFoCi2Fo　Ci,F.

MIO00001 When c,=c2=c3=o Mll Of 01 1 When C,=C2=C,=1 The M bit is variably O or 1.

From these bit patterns, when 7-raming is correct (also assuming that no bit is in error),
It can be seen that the following relationship applies.

(i) When the two most adjacent F bits are both 0, in a sequence of M and C bits, the two adjacent bits are C bits and must be the same since they are C1 and 02.

(ii) When the current F bit is 1 and the previous F bit is O, in the sequence of M and C bits, three adjacent bits are the same because there are three C bits in 7 frames. There must be.

In the 7>-ming process according to embodiments of the invention, these relationships are examined as much as the frame bit patterns themselves. During the 7-raming process, even if one or both of these relationships are not true and the frame bit pattern itself appears correct, bit slips occur and the search for proper frame synchronization continues. Thus, in the presence of the simulated data bit pattern described above, when the simulated data bit pattern is evaluated as a frame bit pattern, an examination of these relationships immediately indicates that the pattern is incorrect. As a result, traditional long frame times are avoided.

Although the above relationship assumes that there is no error in the C bit, it has been shown that the probability of this error is very small, much smaller than the probability that the FA pseudo data bit pattern can occur. There is. When a true 7-frame bit pattern is evaluated, in the unlikely event that an error occurs during the 7-frame process, it simply causes a longer than normal frame time in accordance with the invention as an isolated event. Will. It should also be noted that the present invention also returns to a much faster frame time in the absence of a simulated data bit pattern (although not necessarily longer than similar errors would occur in the prior art). .

Figure vJ2 shows a frame circuit according to an embodiment of the invention.

In FIG. 2 and MS4 through FIG. 7, the following symbols in the various blocks have the following meanings.

D Data input CK Clock input Q, -Q Output and its complement D-FF D type 7 lips 70 tubes! With reference to Figure @2, the D33 bit group on line 10 and the generated response of the clock signal DS3 CLOCK on line 12 are connected to the input of the 8-bit latch 16.
It is fed to a series-to-parallel converter 14 with parallel outputs. The signal D83 CLOCK is also provided to the divider 18 and is typically divided by 7, but the OR date 20 provides a logical 1 to the input ÷8 of the divider 18 so that it is divided by 8. can be controlled. ? s calculator 18
constitutes a clock signal C6M which controls the latch 16 to latch the contents of the converter 14 and generates one bit each of the dependent data group at the D82 level for seven outputs, line numbers 1 to 7. The eighth output of latch 16 is the DS3S3 auxiliary bit, M, as described in more detail below.

A signal II B I T is generated which provides the C and F bits.

Signal C6M is also provided to a ÷12 divider 22 whose Q output is connected to one input of gate 20.

The elements of the frame circuit described are for multiplexing the DS3 S3 piff into a group of dependent D82 bits and generating the DS3 auxiliary bit as signal HB I T, assuming that DS37 frame synchronization has already been established. The divider 18 thus properly distributes the DS3 bits into seven dependent DS2 data groups, and the @g calculator 22 divides the D33 bits constituting one auxiliary bit, as already mentioned.
Each 85th bit of the bit group is separated into signal 1 (B
Modify the operation of divider 18 to occur as IT.

To achieve frame synchronization, an additional bit slip can be achieved by one signal 5LIP applied to the ÷8 power of divider 18 via OR date 20. Just 1
Two such additional bit slips are required between consecutive F bits of the D33 bit group, and the signal 5LIP
If it occurs at the same time as 1 of the Q output of ÷1211Jg unit 22, there will be no effect, so the signal 5LIP
is generated by being dated by the AND date 23 together with the slip command signal SL IPCMDit generated by the slip filter 24 and the signal SLTPTIME which is generated by the AND date and supplied to the slip filter 24. Divider 2
The 2Q output signal is provided to a ÷2 divider 26 to generate complementary (F-bit) clock signals FCLK and (M and C-bit) clock signals FCLK. Signal FCLK is date 25
, and the other input is drawn out from the second output of the divider 22, e.g.
The sixth one of the states is at a high level for one counting state.

fjS3 diagram shows signal FCLK%MCLK%SLIPTIM
The associated timing of the E and Q output signals of divider 22 is shown. FIG. 3 also shows D
Also shown is the associated period during which each type of S3 ancillary bit may be evaluated.

The frame circuit also provides F-bit frame error detection +a
28, M/C bit frame error detector 30, slip condition circuit 32 and OR gate 34. Part 24.
28.30 and 32 are discussed in detail below. The general arrangement and interaction of these parts will first be described.

Error detector 28 to provide fast 7-raming
and 30 are supplied with preview bit signals PVI and PV2 from adjacent outputs of latch 16, as well as supplied with signal HBIT containing the bits of the DS3 data group whose validity is evaluated as DS3 auxiliary bits. be done. In this way, the signals pvi and PV2 become the signal 1
- 1 and 2 of the bits constituting IBIT, respectively.
It consists of bits extracted from the D83 bit group bit later (that is, later in time). 7.1 of the many bit slips achieved during the framing process
When this occurs, detectors 28 and 30 will be
Controlled by the slip status signal on line 36 to use one or both of signals P1 and Pv2 in their evaluation without waiting for a new sequence of S3 ancillary bits. As a result, the 7-raming process has a possible rate of 94 bit slips per DS37 frame (ie, 1 bit slip per F bit).

Each slip state signal is a signal S that causes a bit slip.
Generated by slip condition circuit 32 in response to L I PCMD.

Error detectors 28 and 30 each receive an error signal FER.
R and MCERR, and is logic 1 if each detects an error in its respective detector. The signal is determined when some error is detected! ! ! 1 signal SL
I PREQ is supplied to an OR gate 34 which supplies I PREQ to slip filter 24 .

The slip filter 24 outputs 1 in response to the signal 5LIPREQ during the 7-raming process before frame synchronization is established.
A signal SLIPCMD is generated to cause a bit slip. When frame synchronization is established, slip filter 24 generates a signal INFRAME on output line 38;
To avoid lack of frame synchronization due to spurious signals,
It only generates the signal SL I PCMD in response to some occurrences of the signal Sl, IPREQ and therefore some errors.

Each of the error detectors 28 and 30 shown in PIIJ4 and FIG. 5, respectively, is in a sleep state in which it adapts any recent bit slips made in response to previous evaluations for evaluation as DS3 auxiliary bits. It consists of a first part for generating candidate bits that are selected depending on the signal and a second part for carrying out the evaluation itself. In the F-bit frame error detector 28, the candidate bits are evaluated as F-bit signals FCn representing the current, previous and previous slip compensation bits, respectively.

It is composed of FCn+, and C/FCn z.

Similarly, in the M/C bit 7 frame error detector 30, the candidate bits are evaluated as M and C bits by the signals MCCn, MCCn-, and MCCn representing the current, previous, and previous slip compensation bits, respectively.
It is composed of 2. Signal FOn and MCC
Since n represents the current bit, these are not affected by slip compensation.

Previous compensation bit signals FCn- and MCCn+ are the previous slip time (when signal SLIPTIME=1)
The selection is based on whether there are no bit slips or one bit slip. The candidate bit signals FCI+2 and MCCn-2 are selected based on whether there are no bit slips, one bit slip, or two bit slips at the last two slip times.

FIG. 6 shows the slip condition circuit 32 in detail. It is timed by the signal FCLK and the signal SL r
It comprises two D-type 7-lip 70 tubes 40 and 42 forming a two-stage renoster fed with data configured by the PCMD. The register is the signal SL
Store and update the history of I-PCMD and the occurrence of bit slips in response to errors over the last two periods of candidate DS3 auxiliary bit opening. 7 lip 70 lip 4
The outputs of 0 and v42 are decoded by an AND gate 44 to generate signals SSO to SS3, some of which are further connected to an OR date 46 to generate signals 5SOI and 5S12. signal 5
SO1ssoi, 5S12 and SS3 constitute the slip-like 4s signal on line 36. The states of the various signals depending on the occurrence of a bit slip are summarized in the table below.

ω Ro Ro Ro − ω ω 0 ′″ −0 ω Umbrella −〇〇〇ω Regarding FIG. 4, in the initial state of the F-bit 7 frame error detector, the signals 1-IBIT, PVI and PV2
are timed by signal FCLK and fed to the inputs of three steno shift registers each formed by D-type 7-lip 70 tubes 51-59. Signal FCn is 7
Current signal + (B
It is composed of IT. This signal and the signal FERR generated by the error detector 28 are exclusive-OR'ed 60 whose output constitutes the input data to the 7 lip 70 tube 52 which constitutes the next stage of the HBIT shift renoster.
is fed to the input of Depending on the slip selection signal 5Sol, if there is no focus slip in the last period, the output of this 7-lip 70 knob 52, and if there is one bit slip 7 in the last period, the output in the PVI shift register The output of the second 7-rip 70-tube 55 is selected by the selector 62 as the signal FCn+. Selector 6 formed by three AND dates and one OR date, depending on other slip status signals
4 outputs the output of the 7-rip 70-rub 53 if there is no bit slip in either of the last two periods.
If there is a bit slip in one of the two periods, the output is 7 rip 70, or if there is a bit slip in both of the last two periods, the output is 7 rip 70.
The output of knob 59 is selected as signal FCn-2. Thus, the provision of signals PVI and PV2 and the selection described above ensures that the candidate bits making up signals FCnSFCn+ and FCn-2 are appropriately selected regardless of whether a bit slip has recently occurred.

Signals F Cn and FCn- are provided to the inputs of exclusive OR date 66, and signals FCn+ and FCn+2 are provided to exclusive OR date 66.
It is supplied to the input of R date 68. Date 66 and 6
The output of 8 is 41!, the output of which constitutes the signal FERR. - fed to the input of the other NOR gate 70; Date 6
6 to 70 are D of a succession of three slip-compensated candidate bit signals FCn, FCn-3 and FCn-2 together.
Contributes to inspecting S37 frame bit pattern 10011001...

Since only the three candidate bits FCn, FCn-, and FCn-2 are examined in the generation of signal FERR, the exclusive OR data) 60 generates signal FERR only once in response to each frame pattern candidate bit error. =1
The output of the 7 limp 70 tube 51 is supplemented in response to the 7 limp 70 tube 51 output.

In addition, signal FCn-1 is provided to one input of each of two NOR dates 72 and 74, the second input of which is provided with signal FCn and its complement from complementary outputs of 7-rip 70-tube 51, respectively. Ru. The outputs of these dates constitute signals FBOO and FBO1 which are provided to M/'C bit 7 frame error detection 530 as shown in FIG. Signal FBOO or FBO1 is a logic 1 if the current and previous slip compensated candidate F bits have a continuity of 00 or 01, respectively.

With reference to the @S diagram, the first portion of the M/C bit frame error detector 30 is generally responsive to the fjSl portion of the F bit seven frame error detector 28 and serves a similar purpose. In this error detector, the D-type 7 lip 70 tabs 81 to 89 are timed by the signal MCLK, and the selectors 76 and 78 are activated in a manner similar to that described above. ! Depending on the signal, select the signals MCCn-1 and MCCn-2, respectively.

Slip compensated M/C compensation pitch) M CCn, M
CCn+ and MCCn 2 are signals FBOO and FB
Depending on OI, it is processed by an array comprising AND gates 90 to 93, OR dates 94 and 95, NOR dates 96 and 98, and inverter 99 to generate signal MCERR.

As previously mentioned and as seen from FIG. Candidate bits are bits C1 and C
fC2 and will be equal, date 90 will produce an output of 1 if signals MCCn and MCCn-, are both 1, and date 94 will produce an output of 0 if these signals are both O. output, and inverter 99 outputs 1
produces an output of If these states are not held, gate 98 has its inputs both 0 and produces an output of 1, which is OR? through date 93 enabled by signal FBOO. −) signal M by 95
Generates CERR.

Similarly, if signal FBO1 is logic 1, ie, if the previous and current F candidate bits form sequence 01, then the current and previous 2 bits as shown in FIG.
The three MC candidate bits are pinto C6, C2, and C1, and are all equal. Date 91 is Moshi signal MCC
If n, MCCn-, and MCCn2 are all ones, it will produce an output of one, and gate 96 will produce an output of one if these signals are all zero. If these states are not held, date 97 has its inputs both O and produces an output of 1, which passes through gate 92 enabled by signal FBO1 and OR date 95 produces signal MCERR. .

These two relationships above are checked and if they do not hold common candidate bits, the signal M
CERR connects signal 5LIPREQ via OR date 34
Theory 1 to generate this! I! .

FIG. 7 shows the slip filter 24, which has two D-type 7
control logic with outputs Q1, C2 and output Q complementary to each other with a lip 70 tubes 100 and 102 and an error counter 104, a programmable counter 106, an AND date 108 and one data input D1, D2, D3; A circuit 110 is provided.

If an error is detected as described above, the signal 5LIPREQ generated by date 34 is
The time is measured by E with 7 rip 7 t 77 rip 100. The resulting signal is provided to one input of gate 108;
Also, the time is measured in the 7-lip 70-tube 102 by the signal FCLK, and the Q output of the 7-lip 70-tube 102 is 1.
It constitutes one error signal and is directed to the input D1 of the control logic circuit 110 and the D input of the error counter 104. The Q1 output of circuit 110 is connected to another input of date 108, which output is connected to signal SLIPCM
D and is also connected to the reset input of the counter 106. The output Q2 of circuit 110 is the signal INFRA
It constitutes the ME and is also connected to the clear manual CL of counters 104 and 106. Enable power EN of error counter 104 is connected to the output of C3 of circuit 110. That is, when this input is a logic 1, the error counter 104 is capable of counting the error signal applied to its D input under the control of the signal FCLK;
It also provides a signal via its Q output to input D2 of circuit 110 when the count of 3 is reached. Counter 10G counts pulses of signal FCLK when not cleared or reset via input CL or RESET, respectively.
Counter 106 sends a signal to the circuit through its Q output when it reaches a count of 12 when the signal applied to Q2 is a logic 1, or when it reaches a count of 22 when this input signal is a logic 0. 110 input D3.

Before frame synchronization is established, circuit 110 outputs its output Q
1 to Q3 generate logic levels 1.0 and 0, respectively, thereby enabling AND data 108 and setting counter 106 to count to 22. Each signal SL I PREQ thus proceeds by gate 108 to generate signal SLIPCMD, generating one bit slip and resetting counter 106 to counter zero. Signal FCLK 2
If two cycles occur without an error occurring, counter 106 will reach a count of 22 and provide a signal to input D3 of circuit 110. Frame synchronization is this error 7'J-
(error-tree) condition is assumed to be established, and thus circuit 110 generates logic levels 0, 1, and 0 at its outputs Q1 to Q3, respectively. Date 108 is thus inhibited, signal INFRAME is generated, and counters 104 and 10G are each cleared to a zero counter. Although not shown in the figure for the sake of brevity, an additional date circuit causes counter 104 and V106 to operate in circuit 1 only when output Q3 is a logic O.
10 output signal Q2=1. Signal Q3=1 from circuit 110 overrides the clear signal provided to these counters to allow them to count up from zero, as described below.

If an error subsequently occurs, signal 5LIPREQ is generated and D1 input of circuit 110 is supplied with logic 1;
In response, circuit 110 generates logic levels O11 and 1 at its outputs Q1 to Q3, respectively. Signal rNFRAME does not change here, but counter 104 is enabled and counter 106 is controlled to count 12. This means that the counter 104 counts 3 and 1
The 7-frame missing test (frame e-1
oss-eeheeking) state. If the former occurs first, then as a result of the signal provided at input D2, control logic circuit 110 indicates that frame synchronization has been lost and that date 108 is the initial time to allow frame synchronization to be re-established. considered to be back to normal. If the latter occurs first, as a result of the signal provided to input D3, circuit 110 determines that one or more apparent errors have occurred and causes frame synchronization to be maintained. In that case, the signal INFRAME
and clearing counters 104 and 106.
Return to state.

It will be appreciated that the 3.12 and c/22 counts above are given by way of example only, and other counts may be used subject to statistical considerations. The above embodiments are described only to ensure a complete description of one all-inclusive frame circuit; in fact, any form of slip filter 24 may be fundamentally varied.

Also, to avoid wrong frames, or
The auxiliary nature of the data examined for speeding up the frame process may be the requirement of fixed logic functions, such as in the embodiments of the invention described above, or the general It should be noted that it may also be a statistical property of some useful data.

Numerous and versatile modifications, variations and adaptations may be made to the embodiments described without departing from the scope of the invention as defined by the claims.

[Brief explanation of drawings]

1 is a schematic diagram showing a known form of multi-array; FIG. 2 is a block diagram of a frame circuit according to the invention; FIG. 3 is a timing diagram showing the states of the signals during operation of the frame circuit; FIG. 7 is a diagram illustrating the F bit 7 frame error detector, M/C bit frame error detector, slip state circuit, and slip filter of the frame circuit of FIG. 2, respectively. 14 Series-parallel converter 16 Latch 18.22.26 Divider 24 Slip filter 28 F bit 7 frame error detector 30 M/C
Bit 7 frame error detector 32 Slip state circuit - to S')? - ~ 1st mouth

Claims (1)

[Claims] 1. A frame synchronization method for a serial data group including a predetermined frame pattern, which detects a frame pattern in the data group and generates an error signal in response to the inability to detect the frame pattern. and generating a synchronization slip in dependence on the error signal to provide compensation for previous synchronization slips in frame pattern detection. 2. The step of providing compensation stores a number of consecutive bits of the data group, and depending on the occurrence of a synchronization slip, generates at least one selection signal, and depending on the selection signal, for the detection of a frame pattern. 2. The method of claim 1, further comprising the step of: selecting one of a plurality of stored contiguous bits of the data group. 3. generating an in-frame signal in the absence of an error signal within at least one predetermined period, generating a synchronization slip in response to each error signal in the absence of the in-frame signal; 2. The method of claim 1, including the step of terminating an in-frame signal in response to a predetermined number of error signals occurring during a predetermined period of time in the presence of the frame signal. 4. generating an in-frame signal in the absence of an error signal within at least one predetermined period, generating a synchronization step in response to each error signal in the absence of the in-frame signal; 3. The method of claim 2, including the step of terminating an in-frame signal in response to a predetermined number of error signals occurring during a predetermined period of time in the presence of the frame signal. 5. A frame circuit for frame synchronization of a serial data group including a predetermined frame pattern, timing means for generating a clock signal, means responsive to the clock signal for detecting a frame pattern in the data group; means for generating a synchronization error signal in response to said detection means in which a frame pattern is not detected, and controlling said timing means to vary the phase of said clock signal relative to a data group so as to thereby generate a synchronization slip; A frame circuit comprising: means responsive to said error signal to detect, said means for detecting comprising means for compensating for previous synchronization slips. 6. a first frequency dividing means for frequency dividing a signal to generate a control signal with a bit ratio of a data group by a first predetermined element; a control signal to generate a clock signal by a second predetermined element; a second frequency dividing means for dividing the frequency by a third predetermined factor dependent on the clock signal; and controlling the timing means. means responsive to the error signal for generating a synchronization slip;
6. The frame circuit according to claim 5, further comprising means for frequency-dividing the frequency dividing means by a third predetermined element. 7. The seven-frame circuit according to claim 6, wherein the first frequency division element, the second frequency division element, and the third frequency division element are 7, 12, and 8, respectively. 8. The means for compensating for a previous synchronization slip includes means for storing a number of consecutive bits of a data group, and means responsive to an error signal to generate at least one selection signal in dependence on the occurrence of a synchronization slip; 6. The frame circuit of claim 5, further comprising means responsive to a selection signal to select one of the stored plurality of consecutive bits of the data group for frame pattern detection. 9. The detection means is responsive to the sequence of at least 3 bits of the data group to detect a frame pattern;
9. A frame circuit as claimed in claim 8, wherein the means for storing a plurality of consecutive bits of the data group comprises means for storing at least three consecutive bits of the data group for each of the at least three bits of the sequence. 10. The means responsive to the error signal includes: means for counting pulses of the clock signal in the presence and absence of the error signal; and a first predetermined number of pulses of the clock signal counted by the counting means in the absence of the error signal. means for generating an in-frame signal in response to a third clock signal; means for generating a sync slip command signal in response to the error signal in the absence of the in-frame signal;
5. Means for terminating the in-frame signal in response to counting means for counting a second predetermined number of pulses of the clock signal during the presence of the error signal within a predetermined number of periods of time. Frame circuit as described. 11. The means for compensating for a previous sync slip comprises means for storing a number of consecutive bits of a data group, means responsive to a sync slip command signal to generate at least one selection signal, and means for detecting a frame pattern. 11. The frame circuit of claim 10, further comprising means responsive to said selection signal for selecting one of a plurality of stored consecutive bits of a group of data. 12. said detection means is responsive to a sequence of at least three bits of a data group for detection of a frame pattern;
12. The frame circuit of claim 11, wherein the means for storing a number of consecutive bits of the data group comprises means for storing at least three consecutive bits of the data group for each of the at least three bits of the sequence.