JPH02246436A - Synchronization protection device - Google Patents

Abstract

PURPOSE:To reduce a circuit scale by revising a bit number to be collated from (n) bits into (n+1) bits after the pulse train of consecutive (n) bits is coincident with any of partial patterns. CONSTITUTION:A pattern collation means 7 collates a pulse train in consecutive (n) bits detected at first base on a reception pulse 6 as to whether or not any of m-set of n-bit partial patterns generated from an m-bit synchronous pattern 8 is coincident with the pulse train. When any coincidence is detected, a synchronization protection means 9 establishes a 1st stage backward protection to allow the pattern collation means 7 to revise a received pulse string into a consecutive (n+1)-bit train, detects all the n-set of consecutive (n+1) bits of reception pulse strings detected continuously with the shift of one multi-frame each coincident with any of the partial patterns and establishes one state of backward protection after the 2nd and subsequent stages of the multi-frame synchronization. Thus, the circuit scale is reduced.

Description

[Detailed Description of the Invention] [Summary] Synchronization protection that detects pulses for synchronizing multi-frames from each frame of a time division multiplexed signal, matches it with a predetermined synchronization pattern, and protects the synchronization backward. Regarding the circuit, with the aim of realizing a synchronization protection device with a small circuit scale, n and m are natural numbers such that n<m, and in order to synchronize the multiframes of the time division multiplexed signal, In the synchronization protection device, a synchronization pulse is inserted at a predetermined bit position of a predetermined frame position, and a synchronization pattern determined by the synchronization pulse train is m bits of a part of an n-stage PN pattern, and the multi-frame of the time division multiplexed signal pulse detecting means for detecting received pulses of one bit each from the predetermined bit position in each frame of the interval; and a continuous n-bit received pulse train detected by the means, which is determined from the m-bit synchronization pattern. pattern matching means for matching with any one of the n-bit partial patterns, and establishing backward protection for the first stage of multi-frame synchronization at the time when a match is detected by the means;
After that time point, all of the received pulse trains of 0 sets of consecutive n+1 bits, which are successively detected by the pulse detecting means with a shift of one multiframe, are transmitted to the pattern matching means from that point onwards. The m-bit synchronization pattern is compared to see if it matches any of the consecutive n+1-bit partial patterns found, and if all matches are detected, the second and subsequent stages of multi-frame synchronization are
a synchronization protection means that establishes backward protection for stages and repeats the operation according to the number of stages of backward protection; It is configured to operate independently for each phase.

[Industrial application field]

The present invention relates to a synchronization protection circuit that detects pulses for synchronizing multiframes from each frame of a time division multiplexed signal, checks the pulses against a predetermined synchronization pattern, and performs backward protection of the synchronization.

[Conventional technology]

In digital transmission networks, multiplexing of digital signals is often performed by time division multiplexing.

FIG. 5 shows an aspect of normal time division multiplexing. First, the minimum unit of time division multiplexing is the channel shown in FIG.
A channel is composed of multiple bits (usually 8 bits) from 1 to i.

These channels are then grouped into j frames to form one frame, as shown in the same figure. A frame is a unit by which an exchange etc. simultaneously processes channels corresponding to multiple subscribers, and the number of channels in one frame j is:
For example, an 8.192 Mbit/s intra-office interface of the PCM system has a total of 128 channels, including 120 communication channels and 8 control channels, with L varying depending on the communication capacity of the transmission path.

The above frames are further grouped into frames as shown in FIG. 5(C) to form a multi-frame.

A multiframe is a communication unit for transferring control information between stations using a control channel within each frame, and the number of frames in one multiframe usually ranges from 8 to 16.
It is about one frame.

In the above-mentioned time division multiplexing system, if the entire communication network does not operate with the same clock, or even if it operates with the same clock, jitter may be superimposed on the time division multiplexed signal or clock. When a momentary interruption occurs in the transmission path, time division multiplexed signals become unsynchronized between stations.

Assuming such a case, a number of synchronization protections are performed on the time division multiplexed signal.

In the first synchronization protection, synchronization is established for each bit in the channel shown in FIG. 5(a). For this purpose,
Normally, bit-by-bit synchronization is established by extracting a clock from the received signal, writing the received signal into a buffer using the clock, and then importing it into the device (station) using the clock supplied from the network synchronization device. There is.

In the second synchronization protection, synchronization is established in units of frames as shown in FIG. For this purpose, at the first predetermined bit position (for example, the first bit) in each frame,
A synchronization bit called a frame synchronization pulse is inserted, and this frame synchronization pulse is set so that a certain frame synchronization pattern is repeated between consecutive frames. Then, the synchronization protection circuit acquires synchronization by detecting the frame synchronization pattern from the received signal. Specifically, in synchronization with each bit established in the first synchronization protection, a bit interval (iXj
The received pulses are detected in bits), and a check is made to see if the received continuous pulse train matches the predetermined frame synchronization pattern. Then, this process is performed in parallel for each bit phase (1st phase to jth phase) corresponding to one frame by shifting the phase one bit at a time, and the bit phase where the frame synchronization pattern is detected is The delimiter of each frame is detected from the position of , and synchronization is established.

In the third synchronization protection, synchronization is established in units of each multiframe as shown in FIG. 5(C). To do this, a pulse for multiframe synchronization similar to the frame synchronization pulse is inserted at a predetermined position in each multiframe (usually the second predetermined bit position in the first frame), and this multiframe synchronization pulse is set so that a certain multi-frame synchronization pattern (hereinafter simply referred to as a synchronization pattern) is repeated between consecutive multi-frames. and,
A synchronization protection circuit acquires synchronization by detecting the synchronization pattern from the received signal. Specifically, since the pulse for multi-frame synchronization is inserted at the second predetermined bit position in the frame as described above, one Interval corresponding to multi-frame (k frame interval = iXjXk
A received pulse is detected from the second predetermined bit position in each frame at a bit interval), and it is checked whether the received continuous pulse train matches the predetermined synchronization pattern. Then, this process is performed in parallel for each frame phase (1st phase to 1st phase) corresponding to l multiframes by shifting the phase one frame at a time, and the position of the frame phase where the synchronization pattern is detected is Detects the break between each multiframe and establishes synchronization.

A method in which synchronization patterns are checked in parallel for each of a plurality of phases, such as the second or third synchronization protection described above, is generally called a multi-point monitoring reset method.

In addition, in the second or third synchronization protection described above, since it is not possible to distinguish whether the pulse detected from the received signal is a synchronization pulse or communication data, the target synchronization pattern is detected once from this pulse. It cannot be determined whether synchronization has really been established or not. That is, there may be cases where pulses of communication data are continuously detected and coincidentally coincide with the desired synchronization pattern.

Therefore, normally, synchronization is established when the target synchronization pattern is detected consecutively, for example, four times (in the case of frame synchronization) or twice (in the case of multiframe synchronization). Such synchronization protection is generally called backward protection.

Here, a conventional example of multi-frame synchronization protection, which is the third synchronization protection, will be further explained.

As an m-bit synchronization pattern composed of synchronization pulses inserted into each multiframe, for example, m=4
An 8-bit pattern is used.

That is, when a synchronization pulse is detected from each multiframe of the received signal, a certain pattern is repeated every 48 multiframes.

Next, from the repetition of the above m-bit synchronization pattern,
Further, as an example of generating a continuous n-bit partial pattern, a continuous n=7-bit partial pattern is generated from repetition of a m=48-bit synchronization pattern. Therefore, from repetition of an m-bit synchronization pattern, m types of partial patterns are generated.

Then, using this partial pattern, the backward protection of the multi-frame synchronization is performed as shown in FIGS. Thus, one multi-frame is generated.The reception pulse F1 is consecutively received twice by n bits from the second predetermined bit position in each frame at frame intervals.
~F, and F+'~FII, whereby the received two consecutive sets of n consecutive bits of pulse trains are generated from the synchronization pattern repeating with said m bits. Check whether it matches any of the partial patterns. Then, repeat this process in the fifth
As shown in Figures (a) to (f), this is done in parallel for each frame phase of 1 phase to 1 phase corresponding to 1 multiframe, thereby establishing protection for the rear two stages of multiframe synchronization. For example, if a synchronization pulse is inserted in the first frame of the multi-frame in Fig. 5(C), 1 in Fig. 5(d)
Since coincidence is detected at the phase timing, multi-frame breaks can be detected from this.

Here, the coincidence detection for each frame □ phase is generally realized by the following conventional method.

First, an m-adic counter whose value advances each time a pulse train is detected at an interval of one multiframe is prepared.

Then, as shown in Figure 6 (■), the first detected continuous n-bit pulse train F, ~F, is one of m different n-bit partial patterns generated from the m-bit synchronization pattern. It is checked to see if there is a match, and the counter value at the time of the match is stored.

Next, as shown in FIG. 6 (3), a similar comparison is made for the second consecutive n-bit pulse train F, -Fn' detected, and the counter value at the time of a match is stored.

As a result, the difference between the above two counter values is exactly n
If so, two sets of pulse trains F, -Fn and F+'~Fn
' matches either of two consecutive partial patterns of n bits generated from the synchronization pattern repeated with m bits.

Here, the conditions for generating an n-bit partial pattern from the synchronization pattern that repeats with m bits are as follows:
In a synchronization pattern that repeats in bits, every consecutive n-bit partial pattern must be a different pattern from each other. Such a pattern can be generated by an n-stage PN pattern.

For example, if n=7, a seven-stage PN pattern can be generated using the generation circuit shown in principle in FIG.

In other words, among the bit patterns that are sequentially shifted in shift register 1 from a suitable initial value of 7 bits, when the bit values of 7 bits and 3 bits before match, it is set as "0", and when they do not match, it is set as "1". By determining the current pattern output 3 using the exclusive OR circuit 2, a seven-stage PN pattern can be generated. The 7-stage PN pattern generated by this principle returns to the initial 7-bit pattern with a pattern number of 27-1, and this pattern is
It has the property that any consecutive 7 bits have different patterns.

Therefore, by selecting arbitrary m=48 bits from the above 27-1 bit patterns, it is possible to generate synchronization patterns and partial patterns that satisfy the above conditions.

[Problem to be solved by the invention]

However, in the above conventional example for backward protection of multi-frame synchronization, if the length of the original m-bit synchronization pattern is long, an m-ary counter is used to remember the matching point of the received pattern. The number of bits will increase.

For example, if m = 48 bits, a 6-bit counter is required, and if the size of one multiframe in Figure 5 is set to -8, the above counter is required for each phase from phase 1 to phase 8. Therefore, a total of 6 bits x 8 counters are required.

Furthermore, in order to process a number of time-division multiplexed signals in parallel, a correspondingly large number of counters are required, leading to the problem that the circuit size for synchronization protection increases. .

An object of the present invention is to realize a synchronization protection device with a small circuit scale.

[Means to solve the problem]

FIG. 1(a) is a block diagram of the present invention. In the present invention, n and m are natural numbers such that n<m, and the time division multiplexed signal 4
In order to synchronize the multi-frames, a synchronization pulse is inserted at a predetermined bit position of a predetermined frame position in each multi-frame, and the synchronization pattern determined by the synchronization pulse train is n.
We assume a synchronization protection device that is m bits of a part of the PN pattern of a stage.

First, it has a pulse detection means for detecting the received pulse 6 bit by bit from the predetermined bit position in each frame of the multi-frame interval of the time division multiplexed signal 4.

Next, pattern matching means checks whether the continuous n-bit received pulse train detected by the means matches any of the continuous n-bit partial patterns found from the m-bit synchronization pattern 8. It has 7.

Further, at the point in time when a match is detected by the means, backward protection for the first stage of multi-frame synchronization is established, and from that point on, the pulse detection means is further applied to the pattern matching means 7. All of the n sets of consecutive received pulse trains of n+1 bits that are detected consecutively with a shift of one multiframe from 5 to 5 correspond to any of the partial patterns of consecutive n+1 bits found from the m-bit synchronization pattern 8. Synchronization protection that checks whether there is a match or not, and when all matches are detected, establishes one stage of backward protection from the second stage of multi-frame synchronization, and repeats this operation according to the number of stages of backward protection. It has means 9.

The pulse detection means 5, the pattern matching means 7, and the synchronization protection means 9 are each configured in a truncated manner so as to operate independently for each frame phase within the multi-frame, for example, in a time division manner.

[For production]

FIG. 1(b) is a detailed explanatory diagram of the present invention having the configuration shown in FIG. 1(a). This will be explained below with reference to FIG. 1(a).

First, assuming that frame-by-frame synchronization has been established in advance,
A pulse detection means 5 detects a received pulse 6 of one bit at a multiframe interval from a predetermined bit position in each frame where a synchronization pulse for multiframe synchronization may be inserted.

Next, in the pulse matching means 7, the continuous n-bit pulse train F+ detected the first time based on the received pulse 6 is
``Check whether Ffl matches any of the m types of n-bit partial patterns generated from the m-bit synchronization pattern 8.

If a match is detected (Fig. 1(b) ■), the synchronization protection means 9 establishes the first stage of backward protection, stores that the first match has been detected, and further performs pattern matching. For the means 7, the received pulse train is changed from consecutive n bits to consecutive n+1 bits, and the pulse detecting means 5 generates n sets that are successively detected with a shift of one multiframe as shown in Fig. 1. Continuous n+1 bit received pulse train Ft~F+', F2~F2',..., F, -F,'
It is checked whether or not all of them match any of the n+1 consecutive partial patterns of focus determined from the m-bit synchronization pattern 8.

Then, when all matches are detected, backward protection for one stage from the second stage of multi-frame synchronization is established, and this operation is repeated according to the number of stages of backward protection. Therefore, after the coincidence detection in Figure 1), one consecutive coincidence detection in Figure 1) is performed, thereby establishing the synchronization protection force 5 of the rear two stages of multi-frame synchronization. If it is desired to increase the number of stages of backward protection, it is sufficient to increase the number of cycles of the n+1 bit matching monitoring process shown in FIG.

The above operation is performed by the pulse detection means 5, the pattern matching means 7, and the synchronization protection means 9 independently for each frame phase within the multiframe, and the multiframe is separated from the frame phase where synchronization is first established. can be determined.

In the above operation, the synchronization protection means 9 operates as shown in FIG. 1(b).
It is sufficient to have a counter that counts how many times a match has occurred consecutively in the match detection of ■ in the same figure after the match detection of ■ in the figure.
48, n = 7, if the frame phase is 8 phases, it is only necessary to prepare 3-bit counters for 8 phases to count the coincidence detection of 0 to 7, whereas the conventional example required 6 bits x 8 phases. The circuit scale can be halved compared to the previous version.

〔Example〕

Hereinafter, the operation of the embodiment of the present invention will be explained with reference to the drawings.

FIG. 2 is an overall configuration diagram of an embodiment of the present invention.

The time division multiplexed signal 16 is input to the pulse detection section 10,
Here, the received pulse 17 at a predetermined bit position in each frame
are detected sequentially.

The received pulse 17 is inputted to a pattern detection section 11 constituted by a shift register for 8 bits x 8 phases,
From this, an 8-bit received pulse train 18 is obtained which is detected continuously (at intervals of 8 frames) from each frame phase for each frame phase from phase 1 to phase 8. Specifically, in a certain frame phase, a continuous 8-bit received pulse train 18 from 7 multiframes before the frame phase (for example, 1 phase) corresponding to that frame time is output, and in the next frame phase, the continuous 8-bit received pulse train 18 is output. , a similar received pulse train 18 of the next frame phase (for example, two phases) is output. Therefore, the received pulse train returns to the original frame phase in a period of 8 frames corresponding to 1 multiframe. Note that the pattern detection section 11 operates according to frame pulses for frame synchronization extracted in advance from the time division multiplexed signal 16, and its output maintains a constant value during each frame time.

This received pulse train for one day is input to the pattern matching section 12. Furthermore, 48 8-bit partial patterns 19 generated by the synchronization pattern generation section 13 are input to the pattern matching section 12 during one frame time.

+, in the pattern matching section 12, the 8-bit received pulse train 18 and partial pattern 1 inputted from the pattern detection section 11 and the synchronization pattern generation section 13 for each frame time.
Regarding 9, verification is performed using only 7 bits among them at first, and when a match is made, a high level match pulse COMP is generated.
is output to the protection circuit section 15.

When the protection circuit unit 15 recognizes the first coincidence pulse COMP for each frame phase, it outputs a control signal A to the pattern number switching unit 14.

When the pattern number switching unit 14 recognizes the control signal A, it outputs a low-level selection signal SEL to the pattern matching unit 12 at the frame phase thereafter.

When the pattern matching section t2 recognizes the low-level select signal SEL, it changes the number of matching bits from 7 bits to 8 bits, and performs the same matching operation as described above.

After detecting the coincidence of the first 7 bits, the protection circuit unit 15
After 8-bit coincidence detection is performed seven times in succession for each frame phase (described later), the synchronization establishment signal REC is lowered from high level to low level to output synchronization establishment.

FIG. 3 is a circuit diagram of the protection circuit section 15 and pattern number switching section 14 shown in FIG. 2.

First, in the protection circuit section 15, the coincidence pulse COMP from the pattern matching section 12 in FIG. The output is input to the AND circuit 25, and the output becomes high level when the timing clock TI is low level, and is input to the F/F 23. The output of the F/F 23 is output as a coincidence detection signal BPREC and is fed back to the OR circuit 24.

The counter 22 is counted up when the coincidence detection signal BPREC is at a high level at the rising timing of the timing clock T2, and is reset when it is at a low level.

The 3-bit output Coo-CO2 of the counter 22 is RA
Feedback to M21. Reading and writing of the RAM 21 is controlled by the address generation section 20.

Moreover, the 3-bit output coo-c02 of the counter 22 is
An AND circuit 26 performs a logical product, and its output is inverted and input to an AND circuit 28. The AND circuit 28 has F/
The output of the F 27 is fed back, and the output of the AND circuit 2 is input to the F/F 27 via the OR circuit 29 .

Note that the output of a forward protection circuit 30 for performing forward protection is connected to the OR circuit 29, but this circuit is not particularly related to the present invention and will therefore be omitted.

The output of the F/F 27 is output as a synchronization establishment signal REC. As a result, the station equipped with the synchronization protection circuits shown in FIGS. 2 and 3 can extract the multi-frame delimiter from the timing of the frame phase when the synchronization establishment signal RFC becomes low level.

Next, the 3-bit outputs 000 to CO2 of the counter 22 in the protection circuit section 15 are output as a 3-bit control signal A.
It is input to the pattern number switching unit 14 shown in the figure.

The control signal A is input to the NOR circuit 33, and its output becomes high level only when the control signal A is all "0".

The output of the NOR circuit 33 is taken in from the selector 32 to the F/F 31 only when the timing clock T2 is at a high level, and the selector 32 feeds back the output of the F/F 31 when the timing clock T2 is at a low level.

The output of the F/F 31 is then output as a select signal SEL to the pattern matching section 12 in FIG. 2. When the select signal SEL is "l", the pattern matching section 1 in FIG.
2 performs 7-bit verification, and when the same signal is "0", 8
Perform bit matching.

The operation of the embodiment having the configuration shown in FIGS. 2 and 3 will be described below along with the operation timing chart shown in FIG. 4.

This embodiment relates to a synchronization protection circuit that performs the third multi-frame synchronization protection described in the "Prior Art" section, and particularly performs two-stage backward protection. The channel structure and frame structure of the multi-frame in FIG. 4(a) are the same as those in the conventional example shown in FIGS. 5(a) and 5(b).

Note that in this embodiment, one multiframe is composed of eight frames.

Furthermore, in this embodiment, as in the case of the conventional example, a synchronization pulse for multiframe synchronization is inserted at a predetermined position within each multiframe, and this synchronization pulse is set to be repeated between consecutive multiframes. . As the synchronization pattern in this case, in the case of this embodiment, a pattern of m=48 bits is used, and from the repetition of this 48-bit synchronization pattern, a continuous partial pattern 19 of n=8 bits is generated as shown in FIG. The synchronization pattern generation section 13 generates the synchronization pattern. Here, the m-48 bit synchronization pattern is generated from a PN pattern of n=7 stages (see the explanation in FIG. 7), as in the conventional example.

Under the above conditions, the pulse detection unit 10 in FIG. 2 first performs frame synchronization (not shown) in advance because the pulse for multi-frame synchronization is inserted into the second predetermined bit position in the frame as described above. For each frame synchronized with the frame pulse of FIG. 4(B) obtained by the protection circuit (which performs the second synchronization protection in the "Prior Art" section), the second predetermined value in each frame is A received pulse 17 is detected from the bit position.

Next, from the pattern detection unit 11 in FIG. 2, 8 bits are detected continuously (at intervals of 8 frames) from each frame phase for each frame phase from phase 1 to phase 8 as described above. A received pulse train 18 is obtained. Specifically, for example, in the frame phase corresponding to the first frame of multiframe M8 in FIG. The received pulses 17 extracted from each second frame of the eight multi-frames M1-M8 are related to the frame phase corresponding to the 0th-order second frame from which the corresponding received pulse train 18 is obtained. A received pulse train 18 is obtained. Furthermore, in the frame phase corresponding to the first frame of the next multiframe 4M9 (7), a received pulse train 18 corresponding to the received pulse 17 extracted from each first frame of multiframes M2 to M9 is obtained.

In the pattern matching section 12, as will be described later, since the select signal SEL from the pattern number switching section 14 is at a high level, the pattern matching section 12 receives input from the pattern detecting section 11 and the synchronization pattern generating section 13 for each frame time. Verification is performed using only 7 bits of the 8-bit received pulse train 18 and partial pattern 19. Here, the partial pattern 19 can be generated from the m=48-bit synchronization pattern within each frame time.
Since a pattern is given, if any one of these patterns matches, the matching pulse COMP becomes high level.

Next, the protection circuit section 15 of FIG. 3 uses the pattern matching section 12 of FIG. When 8 bits match seven times in seven consecutive multi-frames, a low-level match detection signal BPREC is output at the timing of the frame phase.

The number of times a match is detected at that time is counted by a 3-bit octal counter 22. At this time, RAM21
stores the outputs CoO to Co2 of the counter 22 for 8 frame phases, and the address generation unit 20 stores the outputs CoO to CO2 corresponding to each frame phase in the counter 2 every 8 frame times.
2, the counter 22 can operate independently for each frame phase. As a result, the multi-point monitoring reset method described in the "Prior Art" section is realized.

Now, attention will be paid only to the frame phase corresponding to the first frame among the multi-frames M1 to M14 in FIG. 4(a). Note that FIGS. 4(c) to 4(p) show multi-frame M9
The operation timing for one frame of the frame phase corresponding to the first frame is expanded, and the logic of the select signal SEL in FIG. 4(n) and the logic of the select signal SEL in FIG. The process is the same except that the counter output co in (p) changes.

First, the outputs C00 to CO2 of the counter 22 are all "
0'', therefore, in the pattern number switching section 14,
The output of the NOR circuit 33 is at a high level, and the select signal SEL from the F/F 31 is at a no level.

This is the timing clock TO immediately after the frame pulse.
is output in synchronization with the rising edge of (Figure 4 (c) and (
(see i)).

As a result, the pattern matching section 12 shown in FIG. 2 performs 7-bit pattern matching.

In this state, for example, when the matching pulse COMP is output from the pattern matching section 12 at the frame phase of the first frame of the multi-frame M8 in FIG. 4(a) (see FIG. 4(1)), the timing F/F 23 at the rising timing of clock T1 (see Figure 4 (j))
The coincidence detection signal BPREC output from becomes high level (
(See Figure 4(e)). From now on, the coincidence detection signal B
PREC maintains a high level for one frame time.

The rising timing of the subsequent timing clock T2 (
(see FIG. 4 (9)), the output Co (1
phase) corresponds to the value 0 to 1 (both 1) as shown in Figure 4 (C).
Count up in 0-decimal notation). And this output C
0 (1 phase) is stored in the RAM 21.

Subsequently, the next multiframe M9 after multiframe M8
At the frame phase corresponding to the first frame, first, the value 1 of the counter output C0 (1 phase) of the frame phase corresponding to the first frame is read from the RAM 21 in FIG. Therefore, the output of the NOR circuit 33 of the pattern number switching unit 14 in FIG. 3 becomes low level, and the select signal SEL
becomes low level at the rising timing of the timing clock TO (FIG. 4(i), (n), and (f)).

Therefore, the pattern matching section 12 in FIG. 2 switches from 7-bit matching to 8-bit matching. As a result, the 8-bit received pulse 17 detected at the frame phase of the first frame of multi-frames M1 to M9 is compared with 48 different 8-bit partial patterns 19. Now, in the time division multiplexed signal 16 (FIG. 2) of FIG. 4(a), if a synchronization pulse is stored in the first frame of each multiframe, then in the multiframe M8, the synchronization pulse of FIG. Even after a match is detected by the pattern matching unit 12, V
Even in each of the multi-frames t,<M9 to M14, the received pulse train 18 in FIG. Therefore,
Matching pulse COMP from the pattern matching section 12 in FIG.
is output as shown in FIG. 4(1), and the coincidence detection signal BPREC in FIG. 3 is output as shown in FIG. 4(e) and 6'rl)
The counter 22 becomes high level as shown in Fig. 4 (
C) and count up from the value 1 to 2 (decimal number) like (0).

Here, after the first match is detected in multiframe M8, the number of matching bits in the pattern matching section 12 in FIG.
The reason why we changed from 7 bits to 8 bits including those 7 bits is that if we simply match with 7 bits, the pattern matching section 12 will generate 48 patterns from the m = 48 bit synchronization pattern output from the synchronization pattern generation section 13. This is because, among the partial patterns 19 of , a pattern that is not continuous with the previously matched partial pattern 19 may be detected. On the other hand, if 8 bits including the previous 7 bits are used for matching, the pattern of the part that is continuous with the partial pattern 19 that was matched previously will always be matched. As a result, the continuous verification operation shown in FIG. 1(b) is realized.

Thereafter, each multi-frame MIO-M14 in FIG. 4(a)
As for the smell, as shown in FIG. 4(f), the pattern number switching section 14
The select signal SEL from is low level, Fig. 4(e)
The coincidence detection signal BP from F/F 23 in FIG.
REC becomes high level and a count-up is performed in the same manner as above.

Then, at the time of multi-frame M14, the output of the counter 22 in FIG. 3 becomes 7, that is, coo-co2 becomes all "1". As a result, the output of the AND circuit 26 in FIG. 3 becomes high level, and the synchronization establishment signal RFC output from the F/F 27 falls to low level as shown in FIG. Multiframe synchronization is established at the timing of .

Through the above operation, backward protection of n=7 bits×2 stages is realized for multi-frame synchronization, as in FIG. 1(b).

Next, in parallel with the above operation, the protection circuit unit 15 and pattern number switching unit 14 in FIG. 3 operate independently even in frame phases corresponding to the second to eighth frames other than the first frame. do. However, for example, if a synchronization pulse is inserted in the frame phase of the first frame, it is impossible for the received pulse train 18 in FIG. 2 to continuously match the partial pattern 19 in other frame phases. Therefore, for example, in multiframe M8 in FIG. 4(a), the fourth
As shown in FIG.
Even if C starts up, the next multiframe M
Since it is highly unlikely that they will match even at 9, the output CO (other phase) of the counter 22 in FIG. 3 is immediately reset to O, as shown in FIG. 4(d) or Φ), and Synchronization is not established by phase.

With such a multi-point monitoring reset method, the same synchronization protection process is performed in parallel on each frame phase that makes up a multiframe, and the multiframe break is finally determined from the frame phase where synchronization protection has been established. be able to.

In the embodiment shown above, when the received pulse 17 and the partial pattern 19 first match at 7 bits and then match at 8 bits seven times in a row while shifting 1 bit at a time, the synchronization protection of the rear two stages is performed. can be established.

As a result, the counter 22 in the protection circuit section 15 in FIG.
Because only a 3-bit counter that counts 0 to 7 is required, the circuit size can be reduced to about 1/2 compared to the conventional example described in the "Prior Technology" section. .

[Effects of the Invention] According to the present invention, after a continuous n-bit pulse train initially matches any of the partial patterns, the number of bits to be matched is changed from n bits to n+1 bits, and the sequence is shifted by one multiframe. By detecting that all of n sets of consecutive n+1 bit received pulse trains that are consecutively detected match any of the partial patterns, backward protection for one stage from the second stage of multi-frame synchronization is performed. Since this is established, the synchronization protection means only needs to have a counter that counts how many times a match has occurred consecutively, and the circuit scale can be reduced.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are diagrams of the principle of the present invention, and FIG. 2 is:
3 is a circuit diagram of the protection circuit section and the pattern number switching section; FIG. 4(a) to Φ) are operation timing charts of the embodiment of the present invention; FIG. 6 is an explanatory diagram of the conventional example, FIG. 6 is an explanatory diagram of the principle of the conventional example, and FIG. 7 is a diagram of the principle of the PN pattern generation circuit. Time division multiplexed signal, pulse detection means, received pulses, pattern matching means, synchronization pattern, synchronization protection means.

Claims (1)

[Claims] n and m are natural numbers such that n<m, and a time division multiplexed signal (4
), a synchronization pulse is inserted at a predetermined bit position of a predetermined frame position in each multiframe, and the synchronization pattern determined by the synchronization pulse train is a part of m bits of a PN pattern with n stages. A synchronization protection device comprising: pulse detection means (5) for detecting received pulses (6) bit by bit from the predetermined bit position in each frame of the multi-frame interval of the time division multiplexed signal (4); , pattern matching means for checking whether the continuous n-bit received pulse train detected by the means matches any one of the continuous n-bit partial patterns determined from the m-bit synchronization pattern (8); (7), and establishing backward protection for the first stage of multi-frame synchronization at the time when a match is detected by the means, and from then on including the time, for the pattern matching means (7), Furthermore, all of the n sets of consecutive received pulse trains of n+1 bits, which are successively detected by the pulse detecting means (5) with a one-multiframe shift, are all in accordance with the m-bit synchronization pattern (8
) is compared to see if it matches any of the consecutive n+1 bit partial patterns found from
It has a synchronization protection means (9) that establishes rear protection for stages and repeats the operation according to the number of stages of rear protection, and the pulse detection means (5), the pattern matching means (7) and the synchronization protection means ( 9) The synchronization protection device operates independently for each frame phase within the multiframe.