CA1262384A - Frame synchronization with slip compensation - Google Patents

Abstract

FRAME SYNCHRONIZATION WITH SLIP COMPENSATION

Abstract of the Disclosure Frame synchronization to the framing pattern of a DS3 bit stream is achieved by detecting the framing pattern and producing a synchronizing slip in the absence of such detection. In order to avoid long framing times as a result of unconfigured adjacent DS1 transmission links producing data which mimic the DS3 framing pattern, redundantly transmitted stuff information (tributary justification control) bits are also checked to ensure that appropriate bits, relative to the position of the framing pattern bits, have expected properties (e.g. triplicated values), and a synchronizing slip is also produced if this is not the case. Short framing times are also achieved by storing in each of the framing pattern and stuff information bit detectors not only the particular bits which are currently to be checked, but also consecutive bits which are selected in dependence upon the occurrence of previous synchronizing slips.

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Description

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FRAME SYNCHRONIZATION WITH SLIP COMPENSATION
This invention relates to a method of synchronizing to -frames of a serial da-ta stream including a predetermined framing pa-ttern, and to a framing circuit for achieving such frame synchronization.
It is well known to provide a framing circuit to detect a framing pat-tern in a serial data stream, and to ef-fect frame synchronization on the basis of this detection. Ideally, the framing pattern is easily detectable and does not occur in the remainder of the data stream; these ideals, however, are rarely met in practice as a result of other constraints, such as bandwidth limitations and the need to transmit data transparently, i.e. without limitations imposed by framing considerations. In consequence the framing time, or time-to-reframe, is of considerable importance in the framed transmission of serial data. This time, as is well known, is the time which is requlred in order to detect the framing pattern in the data stream and to synchronize to it, ei-ther initially or in the event of a loss of frame synchronization during transmission.
When a framing pattern extends over a relatively large number of bits of the data stream, then there is a delay which occurs before a sufFicient number of bits forming a poten-tial framing pattern can be checkedO This delay recurs each time that there is a synchronizing slip and a set of bits are to be checked for their suitability as the framing pattern, leading to long framing times.
In order to avoid such delays and long Framing times, it is known to provide a framing pa-ttern detector in which, for a framing pattern which is n bi-ts long, at least n candidate bi-ts are stored From each oF n consecutive frames. At the end of this storage or candidate bit collection period, during which no frame synchronizing slips are permit-ted, each of the candidate bit sequences, comprising corresponding candidate bits from the n successive frames which may constitute the framing pattern, is assessed For its validity as the framing pattern. Any candidate bit sequence which does not correspond to the framing bit pattern is eliminated from fwrther consideration, and a frame synchronizing slip is then optionally effected through one or more bit positions. This sequence is repeated until all possible bit positions have been considered -for their suitability as the framing pattern, and until only one ~ ~iZ3i~

candidate bit sequence has not been eliminated. This is then regarded as the framing bit pattern, and a final synchronizing slip is made to synchronize to this.
While parallel frame-alignment schemes of the above type can 5 achieve Fast framing times, they require very complicated and consequently expensive circuitry to implement them. In consequence, such complex schemes are desirably avoided in practice.
An object of this invention, therefore, is to provide an improved method of frame synchronization and an improved framing circuit.
According to this invention there is provided a method of synchronizing to frames of a serial data stream including a predetermined framing pattern, comprising the steps of: detecting the framing pattern in the data stream; producing an error signal in response to a failure to detect the framing pattern; changing the phase of a clock signal relative to the data stream, thereby to produce a synchronizing slip, in dependence upon the error signal; and providing compensation for previous synchronizing slips in detecting the framing pattern.
Thus in accordance with this invention, during framing a synchronizing slip is produced in response to each candidate bit which is detected as being inconsistent with the framing pattern, and compensation is provided by the framing pattern detector to accommodate the occurrence of each synchronizing slip so that the next set of candidate b;ts is properly selected without incurring a long delay. The implementation of this method can be eFfected with relatively little circuitry and complexity, as described in detail below.
The step of providing compensation preferably comprises the steps of: storing a plurality of successive bits of the data stream; producing at least one selection signal in dependence upon the occurrence of a synchronizing slip; and selecting one of the stored plurality of successive bits of the data stream, for detection of the framing pattern, in dependence upon the selection signal.
The method preferably also includes the steps of: producing an in-frame signal in the absence of the error signal for at least a predetermined period; producing the synchronizing slip in response to each error signal in the absence of the in-frame signal; and

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producing the synchronizing slip and terminating the in-frame signal in response to a predetermined plurality of error signals occurring in a predetermined period in the presence of the in-frame signal.
The invention also provides a framing circuit, for synchronizing to frames of a serial data stream including a predetermined framing pattern, comprising: timing means for producing a clock signal; means responsive to the clock signal for detecting the framing pattern in -the data stream; means for producing a synchronization error signal in response to the detecting means failing to detect the framing pattern; and means responsive to the error signal for controlling the timing means to change the phase of the clock signal relative to the data stream thereby to produce a synchronizing slip; wherein the detecting means comprises means for compensating for previous synchronizing slips.
In an embodiment of the invention the timing means comprises:
first frequency divider means for frequency dividing a signal at the bit ra-te of the data stream by a first predetermined factor to produce a control signal; second frequency divider means for frequency dividing the control signal by a second predetermined factor to produce the clock signal; and means for modifying the Frequency division by the firs-t frequency divider means to frequency divide by a third predetermined factor in dependence upon the clock signal; wherein the means responsive to the error signal for controlling the timing means comprises means for causing the firs-t frequency divider means to frequency divide by the third predetermined factor to produce the synchronizing slip.
The means for compensating for previous synchronizing slips preferably comprises: means for storing a plurality of successive bits of the data stream; means responsive to the error signal for producing at least one selection signal in dependence upon the occurrence of a synchronizing slip, and means responsive to the selection signal for selecting one of the stored plurality of successive bits of the data stream for the detection of the framing pattern.
Advantageously the detecting means is responsive to a sequence of at least three bits of the data s-tream for detecting the framing pattern, and the means for storing a plurality of successive bits of the data stream comprises means for storing at least three successive bits of the data stream in respect of each of the a-t least three bi-ts of said sequence.
PreFerably the means responsive to the error signal comprises: means for counting pulses of the clock signal in the presence and in the absence of the error signal; means for producing an in-frame signal in response to a first predetermined number of pulses of the clock signal being counted by the counting means in the absence of the error signal; means for producing a synchronizing slip command signal in response to the error signal in the absence of the in~frame signal; and means -For producing the synchronizing slip command signal and for terminating the in-frame signal in response to the counting means counting a second predetermined number of pulses of the clock signal in the presence of the error signal within a third predetermined number of periods of the clock signal.
The invention will be further unders-tood from the following description with reference to the accompanying drawings, in which:
Fig. 1 schcmatically illustrates a known form oF multiplexing arrangement;
Fig. 2 shows a block diagram of a framing circuit in accordance with this invention;
Fig. 3, which is on the same sheet as Fig. 1, shows a timing diagram showing signals which occur in operation of the framing circui-t; and Figs. 4 to 7 show diagrams of respectively an F bit frame error detector, an M/C bit frame error detector, a slip state circuit, and a slip filter of the framing circuit of Fig. 2.
Referring to Fig. 1, there is illustrated a known form of multiplexing arrangement for multiplexing bit streams from the DS1 -to the DS3 level. As is known, a DS1 bit stream consists of bits at a bit rate of 1.544MBs, which may for example be constituted by a T1 carrier signal comprising 24 8-bit voice channel signals and associated framing bits. Four such DSl bit streams are multiplexed together by a multiplexer MPX1-2, two of which are illustrated in Fig. 1, to produce a DS2 bi-t stream at a bit rate of 6.312MB/s.
Seven such DS2 bit streams are multiplexed together by a multiplexer MPX2-3 to produce a DS3 bit stream at a bit rate of 44.736MB/s. Thus 3i~

a DS3 bit stream can comprise 28 DS1 bit streams.
Each multiplexer MPX1-2 produces its DS2 bit stream by sampling its 4 inputs or tributaries sequentially 12 times, inverting every other bit, and adding a housekeeping bit. Thus if each housekeeping bit is denoted by H and the input bits for the 4 inputs are denoted X1 to X4, the DS2 bit stream has the form:
~IXlX2X3X4XlX2X3X4XlX2X3X4X1X2X3X4XlX2X3X4XlX2X3X4XlX2X3X4 XlX2X3X4XlX2X3X4XlX2X3X4XlX2X3X4XlX2X3X4HXlX2X3X4...
This is more conveniently expressed as:
10 H [(X1 X2 X3 X4) x 12] H [(X1 X2 X3 X4) x 12]
The mul-tiplexer MPX2-3 produces the DS3 bit stream by sampling its 7 inputs or tributaries sequentially 12 times, taking one bit from each DS2 bit stream on each sample to produce a serial stream of 84 bits to which it adds one housekeeping bit. Eight such 85-bit sequences form a frame which comprises 8 housekeeping bits, and 7 such frames form a masterframe. In each frame, the 8 housekeeping bits form the data pattern:
M; F1 Cj1 Fo Cj2 Fo C
where: i = 1 to 7;
Mj Forms a mas-terFrame word pattern, and is referred to below as an M bit;
Cjl, Cj2, and Cj3 are triplicated stuff/nostuff tributary control bits for the DS2 tributary i in the current masterframe, and are referred to below as C bits; and Fj and Fo are respectively 1 and 0 bits forming an F bit framing pattern.
The F bit framing pattern in the DS3 bit stream, which permits frame synchronization for proper demultiplexing, thus has the sequence F1 Fo Fo F1 in each frame. The F bit framing pattern is thus the bit sequence 1001100110011001....
In the prior art, such a framing bit pattern is detected in the DS3 bit stream, and upon detection and statistical validation (i.e. the pattern persists for at least a predetermined period) the system is deemed to be in frame and demultiplexing is effected accordingly. The problem which the invention seeks to overcome arises in that adjacent unconfigured DS1 links produce bit patterns 2~

in the DS3 bit s-tream which mimic this framing bi-t pattern. A
consequent result is very long reframing times.
The problem arises in -that if there are two adjacent unconfigured DS1 links, i.e. adjacent inputs to a multiplexer MPX1-2 which are permanently both logic 1 or 0, each frame of the resultant DS2 bit stream produced by the multiplexer will for example have -the form:
Il ~(1 0 X X ) x 12]
where X denotes an arbitrary bi-t derived From a DS1 bit stream, and the alternating 1 and 0 arise from the multiplexer's alternate bit inversion of the unconfigured DS1 link, bits in producing the DS2 bit stream~ The sampling by the multiplexer MPX1-2 of its inputs 12 times between successive DS2 housekeeping bits H, and the sampling by the multiplexer MPX2-3 of its inputs 12 times between successive DS3 housekeeping bits, has the result that there is a direct relationship between bit positions in the DS3 bit stream and the DS1 bit streams.
As a result of this and the fact that the F bits of the framing bit pattern in the DS3 bit stream are searched for in alternate 85~bit sequences of the DS3 bit stream (i.eO there are four F bits in each DS3 frame), the above DS2 bit stream produces in the DS3 bit stream a pattern which, in the short term until is is disrupted by the occurrence oF a DS2 housekeeping bit H, corresponds -to the framing bit pattern. The detection of this mimicking framing bit pattern delays detection of the real DS3 framing bit pattern, leading to long framing times.
This situa-tion is exacerba-ted with a greater number of unconfigured DS1 links. With four DS1 links unconfigured, the framing time can be 48 times as long as that For a system in which random data is present on all DS1 inputsO Such long framing times can occur in spite of the merits of the framing bit pattern itself, which enables fast framing to be achieved in the absence o-f the mimicking data bit patterns.
In order to avoid such long framing times, the invention utilizes a predetermined characteristic of bits in the bit stream, other than the framing bits themselves, to facilitate rapid elimination of mimicking data bit pa-tterns From consideration as the real framing bit pattern during the Framing process. In this 23~

embodiment of -the invention, this predetermined characteristic is the nature of the C housekeeping bits of the DS3 bit stream.
As already described, in each DS3 frame there are three triplicated C bits, C1 to C3. As these are triplicated, in the absence of errors they have the property that C1 = C2 = C3, i.e. the three C bits are either all 0 or all 1. Furthermore,-the C bits have a fixed position in the DS3 Frame rela-tive to the F bi-t framing pattern. Thus the DS3 housekeeping bit sequence in each frame actually has the form:
Mj F1 Cjl Fo Cj2 Fo Cj3 F1 M 1 0 0 0 0 0 1 for C1=C2=C3=0 M 1 1 0 1 0 1 1 for C1=C2=C3=1, the M bit being variably 0 or 1.
From these bit patterns, it can be seen tha-t, when framing is correct (and assuming that none of the bits are in error) two relationships hold:
(i) when the most recent two F bits are both 0, then the two most recent bits in the sequence of M and C bits must be the same because they are the C bits C1 and C2;
(ii) when the most recent F bit is 1 and the preceding F bit is 0, then the -three most recent bits in the sequence oF M and C bits must be the same because they are the three C bits in the frame.
In the framing process in accordance with this embodiment of the inven-tion, these relationships are checked as well as the checking for the framing bit pattern itself. In the event that during the framing process one or both oF these relationships is not true, even though the framing bit pat-tern itself appears to be correct, a bit slip is eFfected and hunting for the proper frame synchronization is continued. Thus in the presence of the mimicking data bi-t patterns described above, the checking of these relationships, when a mimicking data bit pattern is being evalua-ted as the Framing bit pattern, rapidly shows that the pattern is not correct, In consequence, the long framing times of the prior art are avoided, Whilst the relationships discussed above rely on the absence of any error in the C bits, it is noted that the probability of such error is very small, and is much less than the probability of ~;23~

mimicking data bit patterns occurring. In the unlikely event that an error does occur in the C bits during the framing process when the real Framing bit pattern is being evaluated, this will merely lead to a framing time, on that isolated occasion9 which is 10nger than normal in accordance with the invention (although not necessarily longer than occurs normally in the prior art with a similar error).
It is also noted that the invention contributes to faster framing times even in the absence of mimicking data bit patterns.
Fig. 2 shows a framing circuit in accordance with this embodiment of the invention. In Fig. 2 and Figs. 4 to 7 the following symbols in various blocks have the following meanings:
D Data Input CK Clock Input Q, -Q Output and its complement D-FF D-type flip-flop Referring to Fig. 2, a DS3 bit stream on a line 10 and a corresponding recovered clock signal DS3 CLOCK on a line 12 are supplied to a serial-parallel converter 14 having eight parallel outputs which are connected to inputs of an 8-bit latch 16. The signal DS3 CLOCK is also supplied to a divider 18, which normally divides by 7 but can be controlled, by a logic 1 supplied by an OR
gate 20 to an input 8 of the divider 18, to divide by 8. The output of the divider 18 constitutes a clock signal C6M which controls the latch 16 to latch the contents of the converter 14 and produce at seven of its outputs, and hence on lines numbered 1 to 7, a bit of each of the tributary data streams at the DS2 level. An eighth output of the latch 16 produces a signal HBIT which provides the DS3 housekeeping bit stream, i.e. the M, C, and F bits, as described in greater detail below~ The signal C6M is also supplied to a 12 divider 22 whose Q output is connected to one input of the gate 20.
The elements of the framing circuit as so far described serve to demultiplex the D53 bit stream into its tributary DS2 bit streams and to produce the DS3 housekeeping bits as the signal HBIT, assuming that DS3 frame synchronization has already been established. Thus the divider 18 causes the DS3 bits to be properly distributed among the seven tributary DS2 data streams~ and the divider 22 modifies the operation of the divider 18 so that each 85th bit, which as already ~2~

described consti-tutes a housekeeping bit, of the DS3 bit stream is separated and produced as the signal HBIT.
In order to achieve frame synchronization, additional bit slips can be achieved by a signal SLIP which is supplied via the OR
gate 20 to -the 8 input o-F-the divider 18. As only one such additional bit slip is desired between successive F bits of the DS3 bit stream, and as the signal SLIP would have no effect if it occurred at the same time that the Q output of the .12 divider 22 is 1, the signal SLIP is produced by gating in an AND gate 23 a slip command signal SLIPCMD, which is produced by a slip filter 24, with a signal SLIPTIME produced by an AND ga-te 25 and also supplied to the slip filter 24. The signal at the Q ou-tput of the divider 22 is supplied to a .2 divider 26, which produces complemen-tary clock signals FCLK (for the F bits) and MCLK (for the M and C bits) at its outputs. The signal FCLK is supplied as one input to the gate 25;
the other input is derived from a second output of the divider 22, and is high -For one coun-ting sta-te, e.g. the 6th o-F the 12 states, o-F
the divider 22.
Fig. 3 illus-trates the relative -timing of the signals FCLK, MCLK, and SLIPTIME and the signal at the Q output of the divider 22.
Fig. 3 also illustrates the relative periods during which the respec-tive types of DS3 housekeeping bits, shown in the synchronized state, can be evalua-ted.
The framing circuit also comprises an F bi-t Frame error detector 28, an M/C bit frame error detector 30, a slip s-ta-te circuit 32, and an OR gate 34. The units 24, 28, 30, and 32 are described in detail below. The general arrangement of these units and their interaction is described first.
In order -to provide rapid framing, the error detectors 28 and 30 are supplied not only with the signal HBIT, comprising bi-ts of the DS3 data stream which are being evaluated for their validity as the DS3 housekeeping bits, but also preview bit signals PV1 and PV2 from adjacen-t outputs of the latch 16. The signals PV1 and PV2 thus consist of bits derived from the DS3 bi-t stream respectively 1 and 2 bi-ts behind (i.e. later in time -than) the bits constituting the signal HBIT. In the even-t of one of more bit slips being effected during the framing process, the detectors 28 and 30 are con-trolled by

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slip state signals on lines 36 to use one or both of these signals PV1 and PV2 in their evaluations, without having to wait for a new sequence of potential DS3 housekeeping bits to be accumula-ted. In consequence, the framing process has a poten-tial rate of four bit slips per DS3 frame (i.e. one bit slip per F bi-t). The slip state signals are produced by -the slip state circuit 32 in response to the signal SLIPCMD which produces each bi-t slip.
The error detectors 28 and 30 produce error signals FERR and MCERR respectively, each of which is a logic 1 in the event of an error being detected by the respective detector. The signals are supplied to the OR gate 34 which accordingly supplies a signal SLIPREQ with a logic 1 to the slip filter 24 in the event of any error being detected. The slip filter 24 produces the signal SLIPCMD
to effect a bit slip in response to the signal SLIPREQ during the framing process before frame synchronization is established. When frame synchronizatiDn is established, the slip filter 24 produces a signal INFRAME on an output line 38, and only produces the signal SLIPCMD in response to several occurrences of the signal SLIPREQ and hence several errors, in order to avoid a loss of frame synchronization due to spurious signals.
Each of the error detectors 28 and 30, shown in Figs. 4 and 5 respectively, consists of a firs-t part for producing candida-te bits, for evaluation as DS3 housekeeping bits, which are selected in dependence upon the slip state signals to accommodate any recent bit slips which may have taken place in response to preceding evaluations, and a second part for performing the evaluation itself.
In the F bit frame error detector 28 the candidate bits are constituted by signals FCn, FCn 1~ and FCn 2 representing respectively the present, previous, and next previous slip-compensated bits which are to be evaluated as F bits.
Similarly, in the M/C bit frame error detector 30, the candidate bits are consti-tuted by signals MCCn, MCCn_1, and MCCn_2 represen-ting respectively -the present, previous, and next previous slip-compensated bits which are to be evaluated as M and C bits. As the signals FCn and MCCn represent current bits, these are no-t affected by the slip compensation. The previous candidate bit signals FCn 1 and MCCn 1 are selected in dependence upon whether no bit slip or one bit slip took place at the preceding slip time (when the signal SLIPTIME=1). The next previous candidate bit signals FCn_2 and MCCn 2 are selected in dependence upon whether no, oneS or two bit slips took place at the last two slip times.
Fig. 6 illustrates the slip state circuit 32 in detail. It comprises two D-type flip-flops 40 and 42 forming a two-stage register which is clocked by -the signal FCLK and supplied with data constituted by the signal SLIPCMD. The register thus stores, and is updated with, the history of the signal SLIPCMD, and hence the occurrence of bit slips in response to errors, over the last two periods between candidate DS3 housekeeping bits. The outputs of the flip-flops 40 and 42 are decoded by AND gates 44 to produce signals SSO to SS3, some of which are combined in OR gates 46 to produce further signals SS01 and SS12. The signals SSO, SS01, SS12, and SS3 constitute the slip state signals on the lines 36. The states of the various signals in dependence upon the occurrence of bit slips is summarized in the following table:
Previous Bit Slips Slip Sta-te Signals Last PeriodPrevious Period SSO SS01 SS12 SS3 20(D-FF 40) (D-FF 42) No No 1 1 0 0 Yes No O 0 1 0 No Yes 0 1 1 0 Yes Yes O O O
ReFerring to Fig. 4, in the first part of -the F bit Frame error detector 28 the signals HBIT, PV1, and PV2 are supplied to the inputs of respec-tive 3-stage shiFt registers formed by D-type flip-flops 51 to 59 which are clocked by the signal FCLK. The signal FCn is constituted by the current signal HBIT latched in the flip-flop 51. This signal and the signal FERR produced by the error detector 28 are supplied to inputs of an Exclusive-OR gate 60 whose output constitutes the data input to the flip flop 52 constituting the next stage of the HBIT shift register. In dependence upon the slip select signal SS01 the output of this flip-flop 52 if there was no bit slip in the last period, or the output of the second flip-flop 55 in the PV1 shift register if there was a bit slip in the last period, is selected as the signal FCn_l by a selector 62. In 3~

dependence upon the other slip state signals a selector 64 formed by three AND gates and an OR gate selects as the signal FCn 2 the output of the flip-flop 53 if there was no bit slip in either of the last two periods, the output of the flip-flop 56 if there was a bit slip in one of the last two periods, or the output of the flip-flop 59 if there were bit slips in both of the last two periods. Thus the provision of the signals PV1 and PV2 and the selection described above ensures that the candidate bits constituting the signals FCn, FCn 1~ and FCn 2 are properly selected regardless of whether or not bi-t slips have recen-tly taken place.
The signals FCn and FCn l are applied to the inputs of an Exclusive-OR gate 66, and the signals FCn_1 and FCn 2 are applied to the inputs of an Exclusive-OR gate 68. The outputs of the gates 66 and 68 are applied to inputs of an Exclusive-NOR gate 70 whose output cons-titutes the signal FERR. Tne gates 66 to 70 together serve to check for the DS3 framing bit pattern 10011001... in the sequence of three slip-compensated candidate bit signals FCn, FCn 1, and FCn-2 Because only three candidate bits FCn, FCn 1, and FCn 2 are checked in producing the signal FERR, the Exclusive-OR gate 60 is provided to complement -the output of the flip-flop 51 in response to the signal FERR-1, so that this signal FERR=1 is produced only once in response to each framing pattern candidate bit error.
In addition, the signal FCn 1 is applied to one input of each of two NOR gates 72 and 74, second inputs of which are supplied with the signal FCn and its complement respectively from the complementary outputs of the flip-flop 51. The outputs of these gates consti-tute signals FBOO and FBOl which are supplied, as shown in Fig. 2, to the M/C bit frame error detector 30. The signal FBOO
or FB01 is a logic 1 if the current and previous slip-compensated candidate F bits have the sequence 00 or 01 respectively.
Referring to Fig. 5, the firs-t part of the M/C bit frame error detector 30 generally corresponds to the first part of the F
bit frame error detector 28, and serves a similar purpose. In this error detector D-type flip-flops 81 to 89 are clocked by the signal MCLK, and selectors 76 and 78 select the signals MCCn 1 and MCCn 2 respectively in dependence upon the slip state signals in a ~ ~23~
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similar manner to that described above.
The slip-compensated M/C candidate bits MCCn, MCCn_1, and MCCn 2 are processed in dependence upon the signals FBOO and FB01, by a logic array comprising AND gates 90 to 93, OR gates 94 and 95, NOR gates 96 to 98, and an inverter 99, to produce the signal MCERR.
As already described and as can be seen from Fig. 3, if the signal FBOO is a logic 1, i.e. if the current and preceding F
candidate bits are both 0, then the current and preceding MC
candidate bits should be the bits C1 and C2 and should be equal. The gate 90 produces a 1 output if the signals MCCn and MCCn_1 are both 1, and the gate 94 produces a O output, so that the inverter 99 produces a 1 output, if these signals are both 0. If neither of these situations holds, the gate 98 has O at both of its inputs so that it produces a 1 output, which is passed by the gate 93 enabled by the signal FBOO and by the OR gate 95 to produce the signal MCERR.
Similarly, if the signal FB01 is a logic 1, i.e. if the preceding and current F candidate bits form the sequence 01, then as shown in Fig. 3 the current and preceding two MC candidate bi-ts should be the bits C1, C2, and C3 and should all be equal. The gate 91 produces a 1 output if the signals MCCn, MCCn_1, and MCCn_2 are all 1, and the gate 96 produces a 1 output if these signals are all 0. If neither of these situations holds, the gate 97 has O at bo-th of its inputs so that it produces a 1 output, which is passed by the gate 92 enabled by the signal FB01 and by the OR gate 95 to produce the s~gnal MCERR.
Thus the two relationships described above are checked, and if these do not hold -for the prevailing candidate bits then the signal MCERR is produced with a logic 1 to produce the signal SLIPREQ
via the OR gate 34, whereby a bit slip is triggered during the framing process even though the F bit frame error detector 28 may not have detected any error in the pattern of candidate F bits which it is checking.
Fig. 7 shows -the slip filter 24, which comprises two D-type flip-flops 100 and 102, an error counter 104, a programmable counter 106, an AND gate 108, and a control logic circui-t 110 having da-ta inputs D1, D2, and D3 and outputs Q1, Q2~ and Q3, the outputs Q1 and Q2 being complementary to one another.

The signal SLIPREQ, produced by the gate 34 in the event of an error detected as described above, is clocked through the flip-flop 100 by the signal SLIPTIME. The resulting signal is applied to one input of the gate 108, and is also clocked through the 5 Flip-flop 102 by the signal FCLK, the Q ou-tput of the flip-flop 102 constitu-ting an error signal and being applied to the input D1 of the control logic circuit 110 and to the D input of the error counter 104. The Q1 outpu-t of the circuit 110 is connected to another input of the gate 108~ whose output constitutes the signal SLIPCMD and is 10 also connected to a reset input of the counter 106. The output Q2 of -the circuit 110 constitutes the signal INFRAME and is also connec-ted to clear inputs CL of the counters 104 and 106~ An enable input EN
of-the error counter 104 is connected to the Q3 output of the circuit 110; when this inpu-t is a logic 1 the error counter 104 is enabled 15 to count, under the control of the signal FCLK, error signals supplied to its D inputs, and on reaching a count of 3 it supplies a signal via its Q output to the input D2 oF the circui-t 110. The counter 106 counts pulses of the signal FCLK when it is not cleared or reset via its input CL or RESET respectively. On reaching a count 20 of 12 i f the signal applied from the Q3 output of the circuit 110 to its input 12 is a logic 1, or on reaching a count oF 22 if this input signal is a logic 0, the counter 106 supplies a signal via its Q
output to the inpu-t D3 of the circui-t 110.
Before frame synchronization is established, the circuit 110 25 produces a-t its outputs Q1 to Q3 logic levels 1, O, and O
respectively, so that the AND gate 108 is enabled and the counter 106 is set to count to 22. Each signal SLIPREQ is thus passed by the gate 108 to produce the signal SLIPCMD, which produces a bit slip and resets the counter 106 to a count oF 0. If 22 cycles oF the signal 30 FCLK occur without an error occurring the counter 106 reaches a count of 22 and supplies a signal to the input D3 of the circuit 110.
Frame synchronization is deemed to have been established by this error-free condition, and accordingly the circuit 110 produces at its outputs Q1 to Q3 logic levels 0, 1, and O respectively. Thus the 35 gate 108 is inhibited, the signal INFRAME is produced, and the counters 104 and 106 are cleared each to a count of 0. Additional gating circui-try, which is not shown -For the sake of clari-ty in the drawings, provides that the counters 104 and 106 are cleared by the output signal Q2=1 of the circuit 110 only when its output Q3 is logic 0. The signal Q3=1 from the circuit 110 over-rides the clear signal applied to these counters so that they can count up from 0 as described below.
IF an error subsequen-tly occurs, producing the signal SLIPREQ, the D1 input of the circuit 110 is supplied with a logic 1, in response to which the circui-t 110 produces at its outputs Q1 to Q3 logic levels 0, 1, and 1 respectively. Thus the signal INFRAME is unchanged, but the counter 104 is enabled and the counter 106 is controlled to count to 12. This constitutes a frame-loss-checking sta-te which persists until either the counter 104 reaches a count of 3 or the counter 106 reaches a count of 12. If the former occurs first, as a result of the signal supplied to its input D2 the control logic circuit 110 deems that -Frame synchronization has been lost and returns to its initial state in which the gate 108 is enabled to re-establish frame synchronization. If the latter occurs first, as a result of the signal supplied to its input D3 the circuit 110 determines that one or more spurious errors have occurred and that frame synchronization has been maintained, in which case it returns to its second state in which it confirms the signal INFRAME and clears the counters 104 and 106.
It should be appreciated that the counts of 3, 12, and 22 described above are given by way oF example only, and other counts mawy be used depending on statistical considerations. Indeed, the whole Form of the slip Filter 24 may be changed radically, the above embodiment o-f-this being described here only in order to ensure completeness of the description of an overall framing circuit.
It should also be noted that the auxiliary characteristic of the data which is examined in order to avoid false framing, or tc speed up the framing process, may be either a fixed logical function requirement, as in the embodiment of the invention described above, or in general any useful statistical property o-F the data in the predetermined position(s).
Numerous and extensive other modifications, variations, and adaptations may be made to -the described embodiment without departing from the scope of the invention as defined by the claims.

Claims (12)

WHAT IS CLAIMED IS:

1. A method of synchronizing to frames of a serial data stream including a predetermined framing pattern, comprising the steps of:
detecting the framing pattern in the data stream;
producing an error signal in response to a failure to detect the framing pattern;
changing the phase of a clock signal relative to the data stream, thereby to produce a synchronizing slip, in dependence upon the error signal; and providing compensation for previous synchronizing slips in detecting the framing pattern.

2. A method as claimed in claim 1 wherein the step of providing compensation comprises the steps of:
storing a plurality of successive bits of the data stream;
producing at least one selection signal in dependence upon the occurrence of a synchronizing slip; and selecting one of the stored plurality of successive bits of the data stream, for detection of the framing pattern, in dependence upon the selection signal.

3. A method as claimed in claim 1 and including the steps of:
producing an in-frame signal in the absence of the error signal for at least a predetermined period;
producing the synchronizing slip in response to each error signal in the absence of the in-frame signal; and producing the synchronizing slip and terminating the in-frame signal in response to a predetermined plurality of error signals occurring in a predetermined period in the presence of the in-frame signal.

4. A method as claimed in claim 2 and including the steps of:
producing an in-frame signal in the absence of the error signal for at least a predetermined period;

producing the synchronizing slip in response to each error signal in the absence of the in-frame signal; and producing the synchronizing slip and terminating the in-frame signal in response to a predetermined plurality of error signals occurring in a predetermined period in the presence of the in-frame signal.

5. A framing circuit, for synchronizing to frames of a serial data stream including a predetermined framing pattern, comprising:
timing means for producing a clock signal;
means responsive to the clock signal for detecting the framing pattern in the data stream;
means for producing a synchronization error signal in response to the detecting means failing to detect the framing pattern; and means responsive to the error signal for controlling the timing means to change the phase of the clock signal relative to the data stream thereby to produce a synchronizing slip;
wherein the detecting means comprises means for compensating for previous synchronizing slips.

6. A framing circuit as claimed in claim 5 wherein the timing means comprises:
first frequency divider means for frequency dividing a signal at the bit rate of the data stream by a first predetermined factor to produce a control signal:
second frequency divider means for frequency dividing the control signal by a second predetermined factor to produce the clock signal; and means for modifying the frequency division by the first frequency divider means to frequency divide by a third predetermined factor in dependence upon the clock signal;
wherein the means responsive to the error signal for controlling the timing means comprises means for causing the first frequency divider means to frequency divide by the third predetermined factor to produce the synchronizing slip.

7. A framing circuit as claimed in claim 6 wherein the first, second, and third frequency division factors are respectively 7, 12, and 8.

8. A framing circuit as claimed in claim 5 wherein the means for compensating for previous synchronizing slips comprises:
means for storing a plurality of successive bits of the data stream;
means responsive to the error signal for producing at least one selection signal in dependence upon the occurrence of a synchronizing slip; and means responsive to the selection signal for selecting one of the stored plurality of successive bits of the data stream for the detection of the framing pattern.

9. A framing circuit as claimed in claim 8 wherein the detecting means is responsive to a sequence of at least three bits of the data stream for detecting the framing pattern, and wherein the means for storing a plurality of successive bits of the data stream comprises means for storing at least three successive bits of the data stream in respect of each of the at least three bits of said sequence.

10. A framing circuit as claimed in claim 5 wherein the means responsive to the error signal comprises:
means for counting pulses of the clock signal in the presence and in the absence of the error signal, means for producing an in-frame signal in response to a first predetermined number of pulses of the clock signal being counted by the counting means in the absence of the error signal;
means for producing a synchronizing slip command signal in response to the error signal in the absence of the in-frame signal;
and means for producing the synchronizing slip command signal and for terminating the in-frame signal in response to the counting means counting a second predetermined number of pulses of the clock signal in the presence of the error signal within a third predetermined number of periods of the clock signal.

11. A framing circuit as claimed in claim 10 wherein the means for compensating for previous synchronizing slips comprises:
means for storing a plurality of successive bits of the data stream;
means responsive to the synchronizing slip command signal for producing at least one selection signal, and means responsive to the selection signal for selecting one of the stored plurality of successive bits of the data stream for the detection of the framing pattern.

12. A framing circuit as claimed in claim 11 wherein the detecting means is responsive to a sequence of at least three bits of the data stream for detecting the framing pattern, and wherein the means for storing a plurality of successive bits of the data stream comprises means for storing at least three successive bits of the data stream in respect of each of the at least three bits of said sequence.