JPS61205991A - Image display processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image display processing device, and more particularly to an image display processing device for image data displayed on a raster scan type color graphic display device.

[Technical background of the invention and its problems]

A teletext system has been developed in which a digital signal is superimposed and transmitted during the horizontal scanning period, which until now was a no-signal portion, within the vertical retrace period of a television digital signal. In the receiving terminal of this teletext system, the transmitted character/graphic information is temporarily stored in an image memory as image data, the stored image data is read out, and after being converted into display data by an image display processing device, it is then converted into display data using a raster scan method. Displaying on a graphics display device.

The number of pixels of the display screen of the above system is K248 (horizontal) x 204 (vertical) as shown in FIG.

Coloring of the pixels displayed on this display screen involves block unit coloring in which coloring is performed in function block units with the number of constituent pixels 4 (*) There are two methods of dot unit coloring to achieve this.

Block unit coloring is a dot pattern D which is brightness information.
P 4 @) X 4 (vertical) Coloring is achieved by selecting one of the f scenery BG as coloring information depending on the polarity of the dot pattern DP. 16
Since the coloring information can be specified by the pixel rate, the amount of coloring information is reduced, and the screen information transmission time is reduced by red information R1 green information G.
, blue information B, and half-brightness information R and I.

On the other hand, in dot unit coloring, red information R, green information G, and blue information B are assigned as color information to each pixel, and an image is formed from these three bits of color information.

Since coloring can be done at a rate of about 1 pixel, it has the advantage of realizing high-definition pixel display. Teletext broadcasting systems have the above two types of coloring methods.
The image display processing device that converts the image data such as the luminance information and color information into the display data displayed on the display device can be extremely versatile if it is designed to be compatible with block unit coloring processing and dot unit coloring processing. can be made into something.

For example, when performing multi-plane display in which two display screens using the above two coloring methods are combined and displayed as one display screen, it is better to use the same image display processing device in different display processing modes. , has advantages that are easily realized. The above advantages become noticeable when this image display processing device is integrated into an integrated circuit. [Object of the Invention] An object of the present invention is to be able to support image display processing in both block unit coloring processing and dot unit coloring processing. Another object of the present invention is to provide an image display processing device that is more versatile.

[Summary of the invention]

In this invention, for example, as shown in FIG. 1, image data supplied to a data bus MD of an image memory is latched into latches 71 to 74. Among these, the image data in the block unit coloring mode is stored in the latches 81 to 84. The IH shift registers 90, 91, parallel-serial exchangers 95-97, shift registers 100, 110, 120, smoothing decoder 130, and switch 140 convert the image data into display data, and the image data in the dot unit coloring mode is transferred to the latch 81.
~84, are converted into display data by parallel/serial conversion circuits 95~97, and shift register 110, respectively, and are converted to display data by switch 1.
43, the display data of the mode corresponding to the mode data M is selectively output. Furthermore, latches 72 to 7
Since the parallel-serial converters 95-97 are shared by both modes, switches 92-94 are used to switch them according to the mode.

An example in which the present invention is applied to a receiving terminal of the system will be described with reference to the drawings.

In this embodiment, flashing (blinking) and concealment can be performed as display functions other than coloring for the functional blocks that are the coloring units of the block unit coloring process. Flashing refers to the blinking of characters and figures in a specified area of the display screen.The color of the characters and figures when "bright" is the color specified by the foreground color FG, and when the color is "dark" the color of the characters and figures is the color of the background. This can be achieved by displaying in the color specified by the color BG (that is, characters and figures cannot be seen). Concealing is a display method in which a part of the reception screen (specified area) is hidden and that part is displayed only by the operation of the reception side.
G, and when canceled, the specified foreground color FG, ii
Display in scenery BG.

The control signal CC indicating the phase of the flushing and the presence/absence of concealment is assigned 4 bits to each functional block.

First, a block diagram of an image memory control device of a receiving terminal to which this embodiment is applied is shown in FIG. 2, and will be explained.

In this image memory control device, the image memory 10 shown in FIG. 2 is configured by connecting four 4-bit x 16 RAMs in parallel, so that the data bus MD has a 16-bit configuration, and 16 pixels (16 4 types of 16-bit display data during the display period.

Dot pattern DP in block unit coloring mode.

The foreground color FG, background color BG, and control signal CC are being read out. In this case, the access time of the image memory 10 (2
00nsec) and the frequency of the display clock CP (5,73
MHz), two clock CP periods (350 nsec) are required to read data.

However, in the case of a 16-bit path configuration, as shown in FIG. 4, during the 16-bit period of the display clock CP (FIG. 4a), there is a READ period ( Figure 4b) and ACC accessing the image memory 10 for purposes other than reading display data.
Four periods are provided on the ESSCC, and during the READ period, a read address corresponding to the mode set in the mode register is supplied to the image memory 10, and 0 characters corresponding to the block unit coloring mode and the dot unit coloring mode are provided. The coordinates on the pixel configuration of a display screen in a broadcasting system are expressed by an 8-bit address (hereinafter referred to as X address and X address, respectively). In this example,
The data bus MD to the image memory 10 has a t-16 pit configuration, and 16 bits in the horizontal direction are processed at once.
The upper 4 bits of the X address on the 8-bit display area become the horizontal address actually given to the image memory.

In addition, in the block unit coloring mode, pre-color FG
, background color BG, control signal CC, etc. coloring information is 4 (horizontal) ×
Since 4-bit information is assigned to each of the 4 (vertical) columns, the vertical address of the coloring information uses the upper 6 pits of the X address on the 8-bit display area.

As shown in FIG. 5, the image memory 10 stores a dot pattern DP in the block coloring unit mode (FIG. 5a).
, foreground color FG, background color BG, and control signal CC.On the other hand, in dot unit coloring mode (Fig. 5b), red information box, green information G, and blue information B are stored in 16-bit parallel in the same address space. Lete is here.

The access address supplied to the image memory 10 is generated from the address generator. Here, the XX address counters 21 and 22 generate read addresses for display data to be displayed on a raster scan type color graphic display device, and the word and line address registers n and 24 are controlled by a control unit such as a CPU. Image memory 1
The X address counter 21, which generates the write destination address when writing image data to 0, counts the display clock CP synchronized with raster scan, and outputs the clock CP 16 clocks earlier than the horizontal display start position. An 8-bit counter that is reset by a horizontal synchronization reset pulse HR generates the above-mentioned 8-bit X address for display. In this case, the upper 4 bits output X4 to X7 of the counter 21 become the horizontal address given to the image memory 10, and the lower 4 bits output Xo-X3 is 16
Used as a reference for generating timing within a bit period. On the other hand, the Y address counter η is an 8-bit counter that counts the horizontal drive pulse HD synchronized with the horizontal synchronization and is reset by the vertical cycle reset pulse VR output to the vertical display start position. G,B
For the vertical and horizontal addresses, the upper 6 bit outputs Y2 to Y7 are used as the counter address.

The word address register contains the horizontal address 4 pinto (BAO~) in word units to access the image memory 10.
BA3) and two pits (Po, Pl) that specify areas within the same address space corresponding to the type of image data, a total of 6
The bit configuration of the 0 line address register is the 8-pitch vertical address of the access destination) (LAO-Li2)
Consists of. As mentioned above, registers B and 24 serve as output ports of the CPU, and address data BAo to BA3, Po are output onto the data bus DB by latch pulses output from an address decoder (not shown).
, Pl, LAo to LAf are latched.

The timing for supplying the plurality of addresses generated by the address generator to the image memory 10 is determined by the timing control signal generator 30. That is, this timing control signal generating section J decodes the lower 4 bits XO to x3 given from the X address counter 21, and
The timing within the 16-bit period of the clock CP is time-divided into 8 periods and given as shown in FIG.

Here, this embodiment has two types of modes as described above, and the storage form of image data in the image memory 10 corresponding to the mode is as shown in FIG. 5 above. . Since the display readout address supplied to the image memory 10 is different for each of the above two types of modes, mode data M indicating the above two types of modes is stored in the mode register 40 to control address supply.

In the block unit coloring mode, image data for one screen is stored in the image memory 0 as shown in FIG.
Four write periods WRITE- provided in the 6-bit period
: Do it using. During this write period WRITE (!6, d), the outputs of the word address register and line address register are supplied from the address switch 50 to the image memory 0 as the address shown in FIG. 87. Moreover, in FIG. 6(d), DP Adr, F GA
dr, BGAdr, CCAdr,)IDP
, F.G.

Indicates a period for reading BG and CC from the image memory 10,
As shown in FIG. 7, the addresses corresponding to each information are from X address counter 21% Y address counter n to image memo! J 101c granted. Here, brightness information (dot pattern Dr) and color information (foreground color FG, background color BG
, control signal CC). Furthermore, in the color information, the output X2 of the X address counter 21. X3
Even in the dot unit coloring mode in which the storage space of the above F'G, BG, and CC is defined by the addresses AIO and All as shown in FIG. is used to store one screen worth of image data in image memory 0 as shown in FIG. 5(b). In this mode, in order to realize dot unit coloring, three color information R, G, and B corresponding to the dot pattern DP in block unit coloring mode are stored.
Each pixel is meticulously colored using eight colors. Therefore, RAdr, GAdr in FIG. 8(d),
B During the Adr period, the outputs of the X address counter 21 and the Y address counter O are stored in the image memory 0 as shown in Figure 9.
supply to. Here, the output X of the X address counter 21
2. Address A12.x3 (Figure 8C). A1
3, the color information R, G, B 17) storage space is divided. Address supply in the write period WR and ITE color is the same as in the block unit read.

As described above, the trap/address switch section provides an address corresponding to the image memory IOK mode trap via the address address bus MA. Here, when the CPU writes image data, it does so via a write data register. On the other hand, when reading image data for display, the image display processing device 70 converts it into a KRGB signal and outputs it to a display device (not shown).

Next, the image display processing device 70, which is a feature of this image memory control device, will be explained with reference to the drawings. FIG. 1 is a circuit diagram showing details of this image display processing device 70, and FIG. 10 is a timing chart explaining its operation.

Referring to FIG. 1, 71 to 74 are 16-bit images 7' supplied from the image memory 10 via the data bus MD.
- Evening time, latch pulse CCLP, DPLP, FGLP
.

These are latches held by BGLPK. In the plot unit coloring mode, the latches 71 to 74 receive control signals CC, dot pattern DP, foreground color FG and background color B, respectively.
G is latched, and in dot unit coloring mode, latch 7
Three types of color information R1G and B are latched in 2 to 74, respectively. Switches 75 to 78 time-divide the 16-bit image data held in these latches 72 to 74 in units of 4 bits to a color control decoder 79 and a latch 81.
~ Output each to the wings 1 This is the decoding process for display 4
This is a precaution that is performed in bit units, and switch 75 ~
78 is the X address counter 2 as shown in Table 1.
Addresses X2 and Xa of 1 define which 4 bits of the 16 bits are to be output. In addition, the first
In the table, Bls~0 indicates the bit position to be output among the bit positions of input image data. 6th color control decoder 801ri, performs flushing and connor control in the hook unit coloring mode. Specifically, in flushing, r
When you are in "Fun seal state" in Conceal J, Conceal,
Since everything inside the functional block is displayed in the background color, all C dot patterns DP that stop supplying the dot patterns DP are 101).The signal C is output. Since this signal C is valid only in the block unit coloring mode, an AND gate of 80 feet is applied. In addition, the latch 84 allows
The image data held in the latch 82 is synchronized with the image data held in the latch 83, and the latches 81 to 84
The latch pulses are commonly LPI.

Below, the functions of this example differ depending on the mode, so
First, the case of block unit coloring mode will be described.

When the mode data M is 111, the block unit coloring mode is set, and when it is '01, the dot unit coloring mode is set. In this mode, smoothing processing is performed. This smoothing process is a process of smoothing the diagonal line part of the pattern data by half-pixel interpolation having a width of 1/2 of the display pixel. Lines RJ, , FL are required. Therefore, the shift register 90 for one horizontal period IH.
91, the dot pattern Dr is delayed, and the above 3
Pattern data DP for a line is obtained. That is, the latch 81 outputs the pattern data DP of the upper line 'fLL, the shift register 90 outputs the line CL currently being displayed, and the shift register 91 outputs the pattern data DP of the lower line FL. These 3 lines KL.

The 4-bit pattern data DP of CL and FL is applied to parallel-serial converters 95-97 via switches 92-94, respectively, and converted into serial data. At this time, load pulse L
It is applied via the Dld switch 98 and the OR gate 99, and the display clock CP is used as the shift clock. The switches 92-94 and 98 are used to switch image data or load pulses to be loaded into the parallel-serial exchangers 95-97 according to mode data M indicating the mode.

The serial data output from the parallel-to-serial converters 95 to 97 are transferred to 6-bit shift registers 100 and 110°12, respectively.
Shifted and timed by 0. In order to detect the diagonal line part in the above-mentioned smoothing, this is done by detecting the currently displayed dot position 1fl and the dot positions 1n- before and after it.
This is because it requires 11 leaves.

Latches 104-106, 114-116, 124-
From 7-126, 9 dot pattern data "tn+1 p R"nyfLtn corresponding to the above three lines
-1rC1n+1 t C1n r"" n I FF
Obtain tn+1 +Ftn, Ftn. The dot pattern data Ctn currently displayed on the currently displayed line is obtained as the output of the latch 115.

The smoothing decoder 130 detects the diagonal line part from the nine dot pattern data, and detects the one dot pattern CP2 having twice the frequency (1/2 period) of the display clock CP.
The dot pattern data D interpolated in half-pixel units is output. From this data DK, switch 1
40 is the 4-bit back color BG supplied from the latch 83
The 4-bit foreground color FG supplied from the latch 84 is selected to realize coloring in units of blocks. 141.14
Reference numeral 2 designates a latch for making the timing of 4-bit coloring data outputted from the switch 140 by the clock CF2 coincide with the timing of dot unit coloring data, which will be described later. 143 is a container supplied to the display device, G,
This is a switch that switches the B signal according to mode data M.

Next, the case of dot unit coloring mode will be described. In this mode, the latches 81 and 84.83 hold red information R, green information G, and blue information B, respectively.

, These color information R, G, B are sent to each switch 93.
, 92.94 through parallel-to-serial converter 96, 95.97
is given and converted to serial. At this time, a load pulse LDP2 is applied to the parallel-serial converter 95°97, and a load pulse LDPI is applied to the parallel-serial converter %. These load pulses LDP1. Since the timings of the LDP2 are different, the serial outputs G and B of the parallel-to-serial converters 95 and 97 are directly given, and the output from the parallel-to-serial converter 96 is given to the switch 143 via a 6-bit shift register 110. are output as R, G, and B signals.

The operation of the image display processing device 70 having the above-mentioned configuration is described in the tenth section.
This will be explained with reference to the figures.

First, the block unit coloring mode will be explained. In this mode, the address shown in FIG. 10 CK is given to the address bus MA of the image memory IO, and correspondingly, the control signal CC,
A 16-bit dot pattern DP, foreground color FG, and background color BG are supplied in parallel. This is the latch pulse CCL.
P, DPLP, FGLP.

BGLP (FIG. 10 d-g) is latched into latches 71-74. The switches 76 to 78 transfer this latch 72 to 74016 bit data to the address X2°X as described above.
a (Figure 10, i) is output in units of 4 bits, and latch 8! with the latch pulse LPI (Figure 10 j). ~8
3 latches (Fig. 10 k%-m). Further, in order to match the timing of the foreground color FG held in the latch 82 with the timing of the background color BG held in the latch 83, the foreground color FG is further latched in the latch 84 (FIG. 10n).

The parallel-serial converters 95 to 97 have load pulses LDPI
(FIG. 10 0), the latch 81 and shift register 9 are connected via switches 92 to 94, respectively.
4-bit pattern data D held at 0.91
P is loaded. Based on these data, the smoothing decoder 130 outputs dot pattern data D interpolated in half-pixel units to the switch 140. At this time, the rising timing t of the load pulse LDPI,
The rising timing t2 of the load pulse LPI is 5.
Although it is shifted by the clock CP (FIG. 10b), it is corrected by shift registers 110, 120, and 130.

That is, the timing tn of the currently displayed dot is corrected by making it the output of the 5th bit of the shift registers 10, 120, and 130.

The foreground color F selected by this dot pattern DVc
G, or 4-bit data R, G with background color BG.

B and R1 are delayed by two clocks CF2 (FIG. 10a) (one clock CP'') by latches 141 and 142, and are output from switch 143 at timing [3].

Next, the dot unit coloring mode will be explained.

In this mode, the address bus MA of image memory 0 is given the address shown in parentheses in FIG. B is supplied in 16 bits in parallel. In addition, the address period for the control signal CCK using the block unit coloring mode is latched in latches 72 to 74, and further outputted in units of 4 pits by switches 76 to 78, and latched in latches 81 to 83 with latch pulse LPI. (FIG. 10-m) o Also, the color information G output from the latch 82 is latched into the latch 84 (FIG. 10-n).

The parallel-serial converters 95 and 97 have a load pulse LDP.
At the rising timing of 2, switch f92.94 respectively.
The 4-bit color information G and B held in the latches 84 and 83 are loaded through the switch 93, and the 4-bit color information G and B held in the latch 81 is loaded into the parallel-serial converter 96 at the rising timing of the load pulse LDP1. The current 4-bit color information is loaded. At this time, load pulse LDP
1 and LDP2 startup timings 11 and 13 are 6.
Although the clock CP is off, the load pulse LDP is 1
The color information R loaded in the 6-pit shift register 1
This is corrected by pressing the 10 button.

The serial outputs G and B from the parallel-serial converters 95 and 97 and the serial outputs R from the shift register 1105% are at timing t.
3, the switch 143 outputs the signals as normal, G, and B signals.

As explained above, in this embodiment, by storing the mode data M indicating the block unit coloring mode or the dot unit coloring mode in the mode register 40, the display address corresponding to the mode is issued from the address switch. is supplied to the image memory 10, and this image memory 10
The image display processing device 70 decodes the image data outputted from the decoding device according to the mode and supplies the decoded image data to the display device as display data. At this time, the image display processing bag [70Fi, 1
6-bit latches 72-74, switches 76-78.4
Bit latches 81 to 84, parallel to serial conversion -5 to 97,
By sharing the shift register 110 in both the block-by-block coloring mode and the dot-by-dot coloring mode, the circuit size is not increased even though image display processing in one mode can be performed.

Therefore, since the chip size does not increase when integrated into a circuit, the defect rate per chip is reduced and the reliability of the chip is improved. Therefore, it is possible to provide a highly versatile image display processing device that can perform block-by-block coloring processing and dot-by-dot coloring processing that is easy to integrate at low cost.

Furthermore, in this embodiment, since the smoothing process that requires three lines of dot patterns DP is performed in the block unit coloring mode, three parallel-to-serial converters are used. Therefore, it has the advantage that it can be shared with the three parallel-serial converters required for three types of color information boxes, G and B in the dot unit coloring mode.

Furthermore, as shown in Figure 10, display data is output at the same timing in both the block unit coloring mode and the dot unit coloring mode, making it easy to perform multi-brain display with multiple image memories. Screen composition of both modes can be performed.

In this embodiment, the color information in the dot-by-dot coloring mode has been described as three types, R, G, and H, but it is also possible to add luminance information processing to enable coloring in eight colors and two gradations. In this case, the brightness information is stored in the free area of the image memory 10, and the address output is supplied during the free period of the read period READ. Then, it is sufficient to latch the luminance information device to the latch 71 and provide one parallel-serial converter.

Furthermore, the present invention is not limited to teletext systems, but can also be applied to computer systems and the like.

〔Effect of the invention〕

According to the present invention, since it is possible to handle coloring processing in units of blocks and coloring in units of dots without increasing the circuit scale, it is possible to obtain a low-cost and highly versatile image display processing device. −

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a circuit diagram showing an embodiment of the image display processing device of the present invention, FIG. 2 is a project diagram showing an image memory control device for a teletext broadcasting system, and FIG. A block diagram showing the pixel configuration of the display screen of the broadcasting system, FIGS. 4, 6, and 8 are timing charts explaining the operation of the circuit shown in FIG. 2, and FIG. 5 is a memory map showing the contents of the image memory. , FIG. 7 and FIG. 9 are explanatory diagrams showing addresses supplied by the address switch, and FIG. 10 is a timing chart explaining the operation of the embodiment shown in FIG. 1. 71-74, 81-84... Latch. 90.91,100,110,120...Shift register. 92-94, 143...switch, 95-97...
- Parallel-serial converter, 130... smoothing decoder. Agent Patent attorney Noriyuki Chika (and 1 other person) Figure 3) 4 Figure'! h 5 Figure (a)
(pJ%4 Figure Collection 7 Figure No. 5' Figure d Address Tsumi
RAdr RE dr
Ding 3 No. q

Claims (1)

[Scope of Claim] An image display processing device that converts image data read from an address of an image memory corresponding to a display position of an image display area into display data to be displayed on a color graphic display device, comprising: the image memory; block unit coloring processing means for converting block unit coloring image data supplied from the image memory into display data; dot unit coloring processing means converting dot unit coloring image data supplied from the image memory into display data; mode setting means for indicating which of the display data output from the dot unit coloring processing means or the block unit coloring processing means is to be supplied to the display device; An image display processing device comprising switch means for selectively outputting display data output from the processing means.