JPS61214073A - Smoothing processor - Google Patents

Abstract

PURPOSE:To obtain the thick and smooth contours of the oblique lines of mixed patterns with data containing a small number of lines, by deciding the presence or absence of the unit picture elements of the oblique lines according to the enlargement information only when a dot pattern is equal to an enlargement pattern. CONSTITUTION:A picture memory 10 stores a dot pattern including a standard pattern and an enlargement pattern mixed together as well as the enlargement information showing whether the dot pattern is equal to an enlargement pattern for each function block. Based on the enlargement information, a smoothing decoder in a picture display processor 70 decides whether the using unit picture element exists or not at the contact position between enlarged picture elements of the oblique line formed by spot contact between the enlarged picture elements only in case the dot pattern is equal to an enlargement pattern. When the using unit picture element is decided, the unit picture elements are totally displayed. Thus it is possible to display the thick and smooth contours of the oblique lines of mixed patterns with the data containing a small number of lines.

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to a smoothing processing device that displays a smooth image by interpolating pattern data stored in an image memory. [Technical backbone of the invention and its problems] In systems that display character pattern data such as letters and figures on a display screen, such as teletext systems, videotex systems, and computer systems, character patterns stored in a character generator, etc. The character pattern data is read out and written into the image memory using this code signal. After the character pattern data has been written, the character pattern data is displayed by protruding from the image memory. In such a system, for example, when displaying a diagonal line such as the symbol "/" shown in FIG. The lines become thinner and become very difficult to see. Conventionally, in order to solve this problem, as shown in FIG.
I am trying to add . By doing this, the outline of the diagonal line becomes thicker and smoother, making the line easier to see. The addition of this half pixel B corresponds to the unit pixel AC to be displayed.
This is performed by detecting diagonal lines from the current unit pixel (hereinafter referred to as the current unit pixel) and a plurality of unit pixels A centered around this. In other words, when character pattern data e [extracts from the image memory, the line L to be displayed
In addition to the data of n (hereinafter referred to as the current line),
Line above the line (hereinafter referred to as upper line) Ln-
1 data and the data of the line one line below (hereinafter referred to as the lower line) Ln+1 are read out, and as shown in FIG. 18, the data of the current unit pixel S4 and the data of eight unit pixels around this are read SO~S3. Ss to S8 are obtained as comparison data. And 11 of these 9 data
．． By determining t□*, a diagonal line is detected, and it is determined whether or not to add a half pixel to the display position of the current unit pixel. Figure 19 shows a conventional smoothing processing device.
In the figure, 1 is a smoothing decoder that detects a diagonal line from the nine data SO to S8 and adds half a pixel. The three data lines Ln-1, Lq, and Ln input to the smoothing decoder 11 are time-aligned using latch circuits 12 to 17 and input in parallel. By the way, a teletext system, a videotex system, and a computer system have a character pattern enlargement display function. This enlarged display is realized by enlarging a character pattern read from a character generator (hereinafter referred to as a standard pattern) and writing this enlarged and converted pattern c (hereinafter referred to as an enlarged pattern) into an image memory. Figure m is an enlarged view of the diagonal line shown in Figure 16. In this case, the diagonal line is obtained by point contact of a plurality of pixels C (hereinafter referred to as double pixels) having a width twice that of the unit pixel A. In this way, even when the display is enlarged, the smoothing process smoothes the outline of the line.

[~, it is necessary to make the line easy to see. However, in conventional smoothing processing, half a pixel B
Since only the lines are added, a sufficient smoothing effect cannot be obtained as shown in FIG. Furthermore, since enlarged patterns and standard patterns coexist in the image memory, if a smoothing processing device dedicated to enlarged patterns is installed, at least 5 lines (current line, upper and lower 2 lines) of data is required. In order to obtain data for five lines, it is necessary to prepare four shift registers for IH (H: horizontal scanning period) or to multiplex read data for five lines from the image memory in a time-division manner. Therefore, as the number of lines required increases, it is desired that the circuit scale increases or data 7 read control can be performed. [Object of the Invention] An object of the present invention is to provide a smoothing processing device that can display thick and smooth outlines of diagonal lines of enlarged patterns mixed with standard patterns using data with a small number of lines. . [Summary of the Invention] In this invention, for example, as shown in FIGS. 1 and 2, a dot pattern D in which a standard pattern and an enlarged pattern are mixed.
In the image memory 1o that stores P, enlargement information M indicating whether or not the dot pattern I) P is an enlarged pattern is also stored in the function block overlap. Based on this enlargement information M, only when the dot pattern DP is an enlarged pattern, the smoothing decoder 1 30 locates the current nest pixel at the point contact position of the enlarged pixels on the diagonal line formed by the point contact of the enlarged pixels. The above objective is achieved by determining whether or not there is a unit pixel, and if there is, displaying the entire unit pixel. [Embodiment of the Invention] Hereinafter, an embodiment in which the smoothing processing device of the present invention is applied to a receiving terminal of a teletext system will be described with reference to the drawings. The teletext system is a system in which a digital signal is superimposed and transmitted during the horizontal scanning period π, which was previously a no-signal portion, within the vertical retrace period of the TV Jimin signal. This receiving terminal temporarily stores the transmitted character and graphic information as image data in an image memory, reads out the stored image data, converts it into display data, and displays it on a raster scan color graphic display device. There is. The number of pixels of a general display screen of this system is 248 (l yellow) x 204 (*) as shown in FIG. The pixels displayed on this display screen are colored in units of functional blocks whose minimum unit is the number of constituent pixels 4 (horizontal) x 4 (, la). This block unit coloring is performed using a dot pattern DP4 (horizontal) x 4 (
Character/figure color (foreground Q) which is coloring information for vertical) F
G and character/figure background color (background color) BG are assigned, and either the foreground color FG or the background color BG is used as the dot pattern D.
Coloring is achieved by selecting depending on the polarity of P. Since it is sufficient to specify the coloring information in units of I6 pixels, the amount of coloring information is reduced, which has the advantage of shortening the transmission time of screen information and reducing the capacity of the image memory. In addition,
Foreground color FG and background color BG are red information R and green information G, respectively.
, blue information B, and half-brightness information R and I. In this embodiment, it is also possible to perform flashing (blinking) and concealment as display functions other than coloring for the functional blocks that are the coloring units of the block unit coloring process. Furano/Blowfish is a flashing character/figure in a specified area of the display screen. When 1-bright, the text/figure color is the color specified by front fuzzy color FG.
The figure color can be achieved by displaying it in the color specified by the background color BG (that is, the text and figures are not visible). Concealing also means that a part of the receiving screen (specified area) is hidden, and the receiving side This is a display method in which the part is displayed for the first time by the operation of . When concealed, that part is all background color BG, and when it is released, it is displayed in the specified previous enemy color FG and background color BG. Therefore, two bits are assigned as flushing phase information and one bit is assigned as concealing presence/absence information for each functional block to form the control signal CC. This control signal CC has a 3-bit configuration, which is 1 bit less than the data foreground FG and background color BG of other functional blocks. Therefore, in this embodiment, this one pit is assigned as enlargement information M indicating whether or not the dot pattern DP within the functional block is an enlarged pattern. By using this enlarged information M, an enlarged smoothing process that requires data for five lines, for example, can be realized using data for the next line. The details will be described later, but the dot pattern ψ within the functional block
If P is known to be an expanded pattern, the minimum pixel of the expanded pattern is equivalent to two lines of double pixels C, so
Looking at data for one line is equivalent to looking at data for two lines. Therefore, enlarged smoothing can be performed using three lines of data. Next, the outline of this embodiment is shown in the circuit (4 pins) shown in Fig. 2.
By configuring four RAMs connected in parallel to the X16, the data bus MD'5r has a 16-bit configuration, and four types of 16
Bit display data, ie, dot pattern DP, foreground color FG, background color BG, and control signal CC are read out. Therefore, when a 16-bit bus configuration is adopted, as shown in FIG. 4, during the 16-bit period of the display clock CP (FIG. 4a), there is a READ period (fourth bit period) during which data is read from the image memory 1o for display. Figure b) and ACCE for accessing the image memo IJIO for purposes other than reading display data
SS periods can be provided for four periods each. In this embodiment, the ACCB88 period is used as the JJWRITE period for writing data to the image memory 10. The pixel configuration of the display screen in the teletext system is
As explained using the diagram, 248 (horizontal) x 204 G
2). Therefore, the coordinates on both the horizontal and vertical display areas are 8-bit addresses (hereinafter referred to as X
address, Y address). In this embodiment, the data bus MD to the image memo IJIO has a 16-bit configuration and 16 bits in the horizontal direction are processed at once, so the upper 4 bits of the X address on the 8-bit display area are actually the image memory. In block unit coloring, previous Af! ! , FG,
Coloring information such as background color BG, control signal CC, etc. is 4 (horizontal) x 4
Since 4-bit information is assigned to each column (vertical), the upper 6 bits of the Y address on the 8-bit display area are used for the vertical address of the coloring information. The access address supplied to the image memory 10 is generated from the address generator. Here, the XYX address counters 21 and 22 supply the image memory 10 with the read and write addresses generated by the address generator for display on a raster scan type color graphic display device, using a timing control signal. The generation section decodes the lower 4 bits Xo-X3 provided from the X address counter 21, and provides the timing within the 16-bit period of the clock CP by time-division into 8 periods as shown in FIG. Image data is stored using four write periods WT'LITE provided in a 16-bit period by a timing control signal generator. During this write period WRITE (FIG. 6 d), the outputs of the word address register 23 and line address register 23 are supplied from the address switch to the image memory 0 as the addresses shown in FIG. (d)
Niite DP Adr, FGAdr, BGAd
r. CCAdr indicates the period during which DP, FG, BG, and CC are read from the image memory 0, and the addresses corresponding to each information are stored in the X address counter 21 as shown in FIG. Image memo January 0 is given from Y address counter n. Here, address A1 of the upper bit of image memory】0
2, the space for storing brightness information (dot pattern DP) and color information (foreground color FG, background color BG, control signal CC) is divided. Furthermore, in the color information, the X address counter 2
1 output x2. The above FG by address A1o, An which is X3 (Fig. 6, c). It defines the storage space for BG and CC. A read address for display data θ is generated, and a word/line address register 24 generates a write destination address when a control unit such as a CPU writes image data to the image memory 0. The X address counter 2I counts the display clock CP synchronized with the raster scan, and counts the 8-bit clock CP which is reset by the horizontal cycle reset pulse HR which is output 16 clocks CP earlier than the horizontal display start position. The counter uses the 8-bit X address XO for display as described above.
Generates X7. On the other hand, the Y address counter n is an 8-bit counter that counts horizontal drive pulses HD synchronized with one horizontal cycle and is reset by a vertical cycle reset pulse VR output to the display start position in the vertical direction. Generate a bit Y address YO to Y7. As mentioned above, all the outputs Yo to Y7 of the counter n are used as the vertical addresses of the dot pattern DP, and the vertical addresses of the coloring information such as the foreground color FG, background color BG, and phase information CC are the upper six. Bit outputs Y2-Y7 are used. Here, the image memory 1o contains a dot pattern DP, a foreground color F
G, background color BG, and control signal CC are 1 as shown in FIG.
6 bits are stored in parallel. The word address register path is a 4-bit horizontal address in word units to which the image memory 10 is accessed (13A
It has a total of 6 bits: O to BA3) and 2 bits (Po, Pl) specifying an area within the same address space corresponding to the type of image data. The line address register is the 8-bit vertical address of the access destination (LAO~LA?
). As mentioned above, the register 24 is the output port of the CPU, and the address data bundle BAo to BA3, P which is output onto the data bus DB by the latch pulse output from the address decoder (not shown).
Latch o, Pt, LAo-LAy. Here, when the CPU writes image data, it does so via the write data register 60. On the other hand, when reading image data for display, the image data is once read out by the image display processing device 70. After smoothing the image data read by the image display processing device 70, the RG
It is converted into a B signal and output to a display device (not shown). Next, the enlargement smoothing process that characterizes this embodiment will be explained with reference to the drawings. FIG. 1 is a circuit diagram showing details of this embodiment, and FIG. 8 is a timing chart explaining its operation. In FIG. 1, the control signal CC, dot pattern DP, foreground color FG, and background color BG read out from the image memory
Each 16-bit image data is applied to latches 71-74 via data bus MD. The 16-bit image data held in latches 71 to 74 is transferred to switches 75 to 74.
78 is time-divided into 4 bits and outputs to a color control decoder 80 and latches 81 to 83, respectively. This is because decoding processing for display is performed in units of 4 bits, which are functional blocks. Further, the front color FG latched to the latch 82 by the latch 84 is transferred to the latch 84.
It is aligned with the time axis of the background color BG latched to 3. Of the 4-bit control signals CC input to the color control decoder 80, 3 for flashing and competition
The bit information is provided to a decoder 85. Decoder 8
5 is a c-dratono that stops the supply of dot pattern DP because all the inside of the function block is displayed in the background color when it is in the "concealed state" in flushing and in the "concealed state" in concealing (all turn DPs are l□i) Signal C
Output. On the other hand, 1-bit enlargement information M indicating whether or not the dot pattern DP-1) in the functional block is an enlarged pattern is input to a 4-bit shift register 86, and the background color BG held in latches 83, 84, Scenery FG This time axis is aligned. In order to obtain three lines of data necessary for the smoothing process, in this embodiment, the dot pattern DP is delayed in units of one line by shift registers 90 and 91 for one horizontal period (IH). That is, from the latch 81, the lower line L port +1. From the shift register 90, the current line Ln,
The shift register 91 outputs the dot pattern DP of the upper line Ln-1, and the dot pattern DP of the upper line Ln-1 is outputted to the parallel-serial converters 92 to 9, respectively.
given to 4. Here, the operation of reading data from the image memory o will be explained with reference to FIG. Address switch The corresponding data is read onto the data bus MD by the addresses of the control signal CC, dot pattern DP, foreground color FG, and background color BG (Fig. 8b) that the criminal gives to the image memory in a time-divided manner. and held in latches 71 to 74 by latch pulses CCLP1DPLP, FGLP, and BGLP (FIG. 8c-f), respectively. Switches 75 to 78 output the 16-bit data of latches 71 to 74 in units of 4 bits according to addresses
Color control decoder 80 and latch 8 in figure i)
1 to 83 are latched (FIG. 8, j % m'). Further, the foreground color FG is matched with the timing of the background color BG by the latch 84 (FIG. 8n), and the enlarged information M is also matched with the background color BG by the /ft register 86 (FIG. 8O). Load pulse LDP (
At the rising timing of FIG. 8 p), the latch 81, shift register 90 . The lower line L that was previously maintained
4-bit dot pattern data DP of line n+1, current line Ln, and upper line Ln-1 are loaded at the same time. Note that the above pulses CCLP and DPLP. FGLP, BGLP, X2. X3, LPI, LDP
is output from between the timing control signal generators described above. Here, when the signal C is output from the decoder 85 described above, the OR gate 95 outputs the upper load pulse LDP.
is gated, so that the dot pattern DP is not loaded into the parallel-serial converter 93 and becomes all 10". This makes it possible to realize flushing and control control. The serial data output from the parallel-serial converters 92 and 94 are the display clocks CP (FIG. 8a) (therefore, they are applied to the shift registers 100 and 120 through switches 96 and 97, respectively, and the serial data output from the parallel-to-serial converter 93 is applied directly to the shift register 110. , foreground color F
G, Background color BG This time axis is aligned, that is, the timing t1 of the rise of the load pulse L DP that loads the dot pattern DP into the parallel-serial converters 92 to 94.
And the rising timing t2 of the latch pulse LPI at which the foreground color FG and back 1%-QBG are latched is 5 clocks C.
Since the timing is shifted by P, the timing of the current unit pixel S4 is corrected by setting the timing to the fifth bit of the shift register 110. Data 5o from shift registers 100, 110, 120
-8t. The smoothing decoder 130 determines from the input data whether the current unit pixel S4 is in a point contact position of a plurality of double pixels forming a diagonal line due to contact, and if so, displays the current pixel. Output data P. Depending on the polarity of this data P, the 4-bit back color BG supplied from the switch 140 latch 83 and the foreground color FG supplied from the latch 84 are selected, thereby realizing coloring in units of functional blocks. 4 pins output from switch 140) (11,,G
,B. Coloring data D of R, I) is timed by a latch 141 and supplied to the display device. (Figure 8q). The signal selection operation of the switches 96 and 97 is controlled by the field index FIJ output by counting the vertically synchronized reset pulse VRQ between the timing control signal generating sections. That is, if the field index FI is "I" (odd field), the switches 96 and 97 are respectively set to the upper line Ln.
-1, select the data on the lower line Ln+t, and FI is “O
' (even field), the opposite is true. The above line conversion operation simplifies the configuration of the smoothing decoder 130, the details of which will be described later. The smoothing decoder 130 has three latches (82 to So) from the latches 124 to 126 of the shift register 120 whose shift clock is the clock CP.
input at the same time. Furthermore, the data on the current line Ln is also five pieces (S
lo, as~83.89) are input at the same time, and similarly, three pieces of data (88-86) from the latches 104-106 of the shift register 100 are input at the same time on the lower line Ln+t. As a result, a total of 11 pieces of data are simultaneously input to the smoothing decoder 130 as shown in FIG. In general, the smoothing decoder 130 receives enlargement information M indicating whether or not the dot pattern DP in the functional block is an enlarged pattern from the soft register 86 using the launch pulse LP'l as a shift clock. Information M, data S4 of the current unit pixel, and data of 10 unit pixels around this current unit pixel SO~S2, Sa
, 85.86-81o total of 11 data SO~8
11, it is determined whether the current unit pixel is in a contact position between a plurality of double pixels C forming a diagonal line, and if the current unit pixel is in a point contact position, data for displaying the current unit pixel is determined. P
Output. As a result, as shown in Fig. 10, the unit side amateurs are added to the left and right of each machine contact position of the diagonal line formed by the point contact of multiple double pixels C, so the outline of the line is thick and smooth. This makes it much easier to see. Here, the addition operation of the unit pixel A by the smoothing decoder 130 will be explained using FIGS. 11 to 14. FIG. 11 shows the case where a unit-side amateur is added to the right side of the point contact position of a 45° left-down line. In this case, the smoothing decoder 130 determines that the enlargement information M is "1" (indicating an enlarged pattern) and that the data 81 and 82 indicate diagonal lines.
, 83, 86, 89 are '11, and data So , 84,
85.87, when Sto is IOl, the current unit pixel is assumed to be on the right side of the point contact value [D, and outputs data P1 of 111 to display the current unit pixel. Similarly, FIG. 12 shows a case where a unit pixel A is added to the left side of the point contact value [1] on the lower left line. Further, FIGS. 13 and 14 show examples in which unit surface amateurs are added to the right and left sides of the point contact position of a line descending to the right at 45°, respectively. In addition,
In FIGS. 11 to 14, data marked with an "x" is data whose contents are not particularly asked in the above determination operation. The above judgment operation can be expressed as a logical expression as follows. P+=Po・M...(1)
-+-8o・5l-82・S3・S4・S5・S7・S
8・S9・St. In the above equation (2), the first to fourth terms on the right side are logical expressions for executing the processes shown in FIGS. 11 to 14, respectively. Note that when the data S4 of the current unit pixel is "1", the data S4 of the current unit pixel output from the latch circuit 115 shown in FIG. That is, the data P2 and the data PI output from the smoothing decoder 130 are combined and output from the smoothing decoder 130 as data P. Fig. 15 is a circuit diagram showing the configuration of the smoothing decoder 130. , in the figure, 131 is an input section for 11 data SO to S10, and these 11 data S
It has a line for directly inputting O to Sjo and inverter circuits 11 to I2+ for inversion. 132 is the third right-hand side of the above equation
It is a decoder unit that outputs the term and the first term, and includes NAND circuits NAo to NA14 and NOR circuits NO11-7-NO12.
Consists of. In this case, NOR circuits No. 11 and No. 12-
1>h, etc., the third term and the first term are output, respectively. 133
is a decoder unit that also outputs the second term and the fourth term,
NAND circuit NA115 to NA 19, NOR circuit NO13
, No S4. In this case, NOR circuit No. 1
3 and No. 14 output the second term and the fourth term, respectively. Furthermore, enlarged information M is inverted and supplied to NOR circuits No11 to NO14 in common by an inverter circuit 13, and the decoders 132 and 133 are operated only when an enlarged pattern is generated. By passing the outputs of these four NOR circuits N011 to No. 14 to the OR circuit 135, the above equation (1) is realized and data P1 is obtained. Furthermore, current unit pixel data S4
as data P2 and OR circuit 13 together with the above data P1.
6, data P is obtained. Note that the above (1) and (2+ expressions are logical expressions when the field index FI is 111, that is, an odd field, and the upper half of the unit pixel shown in FIG. 9 is displayed. However, the field index FI is 101. In other words, in the case of an even field, a logical formula is required to display the lower half of the unit pixel, but in this case, by exchanging the data of the upper line and lower line, the above (1) and (2 ) formula can be used as is. This data swapping is done by the switches 96 and 97 shown in FIG. If the dot pattern DP is known to be an expanded pattern, 3
The fact that enlarged smoothing can be performed using line data will be explained. In explaining this, we will use the figures 11 and 12 shown earlier.
See diagram. Figures 11 and 12 show the case where a unit plane is added to the right and left sides of the point contact position of the downward left line, respectively, but in both cases, by looking at the data for three lines, The point contact position of the line is detected. This is because it is known that the dot pattern DP is an enlarged pattern, so the data of any line of the double pixel C consisting of two lines (in Fig. 11, the data of the lower line 81, 82, In Figure 12, the upper line data 86
．． 87), the presence or absence of the double pixel C can be identified. When performing enlargement smoothing for this without using enlargement information M, the current line Ln in FIG. The data of the lines Ln-2, Ln-1 two lines above, and the line Ln-H below are required, and in FIG.
2, and the data of the line Ln-1 above are required. That is, if the dot pattern DP is an enlarged pattern, but it is not known whether it is a standard pattern, five lines of data are required for enlargement smoothing. As detailed above, this embodiment performs pixel addition processing on a pixel-by-pixel basis, so even when a diagonal line is formed with double pixels, the outline of the line is made thick and smooth. It is possible to obtain lines that are very easy to see. Furthermore, by using the expansion information M indicating whether or not the turn DP is an expansion pattern, the expansion smoothing can be applied to the current line and the lines above and below it, even when the standard pattern and expansion (turn) are mixed. This can be done with a total of 3 lines, reducing the circuit scale.Also, since the expanded information M is assigned to 1 bit of the control signal CC, which was previously unused, no extra memory space is required. 0 In this embodiment, smoothing processing is not performed when the pattern is not an enlarged pattern, that is, when it is a standard pattern.
A smoothing decoder 11 for turns is provided and switched to a smoothing decoder 130 for enlarged smoothing so that in the case of standard turns, this smoothing decoder 11 performs standard smoothing processing as shown in FIG. In this case, it has the advantage that smoothing can be performed depending on the type of pattern.Also, the present invention is not only applied to smoothing processing of diagonal lines formed by double pixels, but also The present invention is applicable to general smoothing processing for lines formed by large enlarged pixels, and even in this case, a line that is easier to see than the conventional process of adding half pixels can be obtained with less line data.Furthermore, the present invention The present invention is not limited to the example of a teletext system, and can also be applied to a videotex system, etc. [Effects of the Invention] According to the present invention, diagonal correction of enlarged patterns mixed with standard patterns can be performed using data with a small number of lines. Since it is possible to display thick and smooth line outlines, the circuit scale does not increase.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the smoothing processing device of the present invention, FIG. 2 is a circuit diagram showing an overview of this embodiment, and FIG. 3 is a configuration showing the pixel configuration of a display screen of a teletext system. 4 and 6 are timing charts explaining the operation of the circuit shown in FIG. 2, FIG. 5 is a memory map showing the contents of the image memory, and FIG. 7 is an explanatory diagram showing the addresses supplied by the address switch. , FIG. 8 is a timing chart for explaining the operation of the embodiment shown in FIG. 1, FIG. 9 is a diagram for explaining data input to the smoothing decoder, and FIG. 10 is a timing chart for explaining the smoothing process of the embodiment. 11 to 14 are diagrams for explaining the operation of the smoothing decoder, FIG. 15 is a circuit diagram showing details of the smoothing decoder, and FIG. 16 is a diagram showing diagonal lines composed of unit pixels. , FIG. 17 is a diagram showing conventional smoothing processing, FIG. 18 is a diagram showing conventional data input before smoothing processing, FIG. 19 is a circuit diagram showing the configuration of a conventional smoothing processing device, and FIG. This is a diagram to explain the problem. JO... Image memory, 71-74. 81-84... Latch, 80... Color control decoder, 9o, 919
．． IH shift register 1 92-94...Parallel-serial converter, 96.97...Switch, 100.110,120...Shift register, 130
...Smoothing decoder. poz

Claims (1)

[Claims] A standard pattern consisting of unit pixels as image data to be displayed and an enlargement of the unit pixels in a memory space accessed by addresses corresponding to horizontal and vertical coordinates on the display screen. An image memory that stores a mixture of enlarged patterns made up of pixels, and enlargement information indicating whether or not the image data stored in this image memory is an enlarged pattern are stored at the address where the image data is stored. an enlarged information memory for storing image data at a corresponding address; image data for a line to be displayed and a plurality of lines above and below the line to be displayed from the image memory; and enlarged information from the enlarged information memory corresponding to the image data to be displayed. a data reading means for reading out the image data, and when the image data read by the data reading means is an enlarged pattern, a unit pixel to be displayed and a plurality of unit pixels around it are unit pixels forming a part of the enlarged pixel; and smoothing processing means for outputting data to display the unit pixel if the unit pixel to be displayed is located at the point contact position of the diagonal line formed by the point contact of the enlarged pixel. smoothing processing device.