JPS5975789A - Color display controller - Google Patents

Abstract

PURPOSE:To prevent color display even where pattern information is not sent out when color information is in background (BG) color, by providing a means which latches vertical display address data by using brightness information outputted from a picture memory and stores the address of the final line where the brightness information is present. CONSTITUTION:A color display controller 18 latches vertical display address data (VDA) from a display address signal generating circuit 10 to store the address of the final line where pattern information Y is present, and stores the information in a vertical period by using vertical synchronizing pulses (VP); and the circuit judges a coincidence between the stored data and data VDA to output a control signal (DAE-2) in the horizontal period following the coincidence, thereby stopping the output of a color latch circuit 16 by the control signal (DAE-2). The display controller 18 is controlled by inputting a display address signal (DAE-1), vertical synchronizing pulses (VP), and horizontal synchronizing pulses (HP).

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a color display control device, and in particular to a teletext broadcasting system that receives brightness information and color information and displays still images on a display screen. The present invention relates to a color display control device in still image information systems such as Captain System and Captain System.

[Technical background of the invention]

Conventionally, in still image information systems such as teletext broadcasting systems and captain systems, there are a code transmission method used in Western European countries and a pattern transmission method used in Japan. In the code transmission method, information is sent as codes from an information center, and a pattern generator provided at each terminal converts the codes into characters and graphics.

In the pattern transmission method, a large-scale pattern generator installed at an information center is used to create patterns of characters and figures in advance, and the signals are transmitted directly to television terminals in homes and the like for display. In the pattern transmission method, pattern information and color information are transmitted independently, with pattern information being transmitted line by line, and color information being transmitted not by line but by block. The block unit of color information is determined based on the character font used on the display screen, for example, it is composed of 8 dots horizontally x 12 dots vertically, and the coloring unit includes the background color (hereinafter referred to as BG color). and the specified color (
(hereinafter referred to as FG color).

Conventionally, in still image information systems such as teletext systems and captain systems, a display control device equipped with an image memory is installed on the receiving side, and this device is used to receive information sent from an information center on a television. Convert it into a signal for display on the machine. Dot pattern data and color data are stored in the image memory, and the data is generally stored in 8-bit parallel data in correspondence with the address. When reading out pattern information during the display period, it is read out in units of display clocks, parallel-to-parallel converted, and input to a color matrix decoder along with color data.
') are obtained and displayed on the display screen.

FIG. 1 is a block diagram showing a conventional display control device.

In Figure 1, CPUUI, work RAM 2 for CPU
, a chip select circuit 4 that outputs a signal to select program ROM 3, RAM 2, and ROM 3, and an input port 5 that takes in externally received data (EX'I' DATA) are connected to an address bus (ADDIζESS BUS).
) and a data bus (DATA BUS), and externally received data (EXT DATA) input to the input port 5 is sent to the display memory 7 via the bus driver 6 according to CPU processing. written. The display memory 7 displays a dot pattern with brightness information.
It consists of a dot pattern memory for storing data and a color memory for storing color data for coloring each colored block. Dot pattern memory e
The chips and color memory e-chips are selected using a chip select signal generated from a chip exposure select circuit 8. During the display period of the display memory 7, the switching circuit 9 switches between
Switching is performed so that a protruding address signal is output and an address signal from the CPU 1 is output during a non-display period. This switching is performed using the display address signal (DAE) output from the display address signal generation circuit 10. When the bus driver 6 loads the data from CP 0.1 into the display memory 7, it uses the data bus (DATλBU
S) is output to the display memory 7. The synchronization signal generation circuit 11 generates a synchronization signal (sYNc) for television.
It also generates a control signal to the display address signal generation circuit 10. Using this control signal, the display address signal generation circuit 10 generates a read address signal for the display memory 7 and various control signals (display clock signal CK, pattern latch signal PL).

It outputs a color latch signal CL and a switching signal YCC for switching between a pattern address signal and a color address signal. The color address decoder 12 decodes the color address signal from the read address signal, and the next stage switching circuit 13 uses a switching signal (YCC) to switch and output the pattern address signal and the color address signal, Perform Ml and protrusion in multiple ways. The chip select circuit 14 is a circuit that generates a chip select signal for the display memory 7 in relation to the Act starting address signal. The data read from the display memory 7 is subjected to pattern latching and parallel-to-serial conversion. The pattern information Y is outputted from the color matrix decoder 151c in synchronization with the display address signal (DAE) and inputted to the color matrix decoder 17. On the other hand, the color information C from the display memory 7 is transmitted to the color latch circuit 1.
6 and is input to the color matrix fist decoder 17 in synchronization with the display address signal ([AE). A color matrix decoder 17 combines the haha turn information Y and the color information C, and outputs primary color signals R, G, B and a luminance signal Y.

In such a configuration, when the display address signal (DAE) synchronized with the synchronization signal (SYNC) is output from the display address signal generation circuit 10 as shown in FIG. Bus driver 6I pattern latch and parallel-to-serial conversion circuit 159 is input to color latch circuit 16, pattern information Y (indicated by diagonal lines) is output from circuit 15, and at the same timing, color latch circuit 16 outputs pattern information Y (indicated by diagonal lines). Color information C (indicated by diagonal lines) is output.

However, in FIG. 2, the symbol A indicates the display period.

[Problems with background technology]

However, in the conventional display control device shown in FIG.
Pattern information Y and color information C are each pattern-latched.
Since the circuit 15 that performs parallel-to-serial conversion and the color latch circuit 16 are output independently, color information C is output at the timing of the display address signal (DAE) regardless of the presence or absence of pattern information Y. There was a drawback that it could be stored away.

In other words, when the color information for each block and the pattern information for each line is BG coloring, in the display area a on the display screen, as shown in FIG. Although the portion shown in FIG.

[Purpose of the invention]

The object of the present invention has been achieved in view of the above-mentioned points, and when the color information is BG coloring, it is possible to prevent portions to which pattern information is not transmitted from being displayed in color. An object of the present invention is to provide a color display control device.

[Summary of the invention]

The color display control device of the present invention receives external data including brightness information and color information from the outside, stores it as busy dot pattern data and color data in an image memory (display memory) using a CPU, and・Related to a display control device for an image memory that displays a still image on a display, the vertical display address is output by a display address signal generating means using the luminance information output from the image memory. - a first storage means for latching data and storing the address of the last line where the luminance information exists;
Furthermore, a second storage means for storing data in a vertical period;
a comparison means for performing a ratio between the address data stored in the storage means and the vertical display address data outputted by the display address signal generation means; and a control signal generated based on the comparison result of the comparison means. means for stopping the output of the color data from the display memory using the control signal from the next horizontal period in which the stored address data and the vertical display address data match. It is said that

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 4 is a block diagram showing a color display control device according to the present invention. In this figure, parts having the same functions as those in FIG. 1 are given the same reference numerals and will be explained. Therefore, the parts with the same reference numerals as in FIG. 1 are the same as the conventional circuit, and the broken line part is the color display control device of the present invention.

In FIG. 4, CPU I, work RAM 2 for CPU.
A chip select circuit 4 outputs signals for selecting program ROM 3, RAM 2, and ROM 3, and an input port 5 receives externally received data (EXTDATA). Externally received data (EXT DATA) input to the input port 5 is written to the display memory 7 via the bus driver 6 according to CPU processing.

The display memory 7 is composed of a dot pattern φ memory that stores dot pattern data that is luminance information, and a color memory that stores color data for coloring each colored block. The dot pattern memory chip and the color memory chip are selected using a chip select signal generated from a chip select circuit 8.

The switching circuit 9 performs switching so that the read address signal is output during the display period of the display memory 7, and the address signal from the CPU 1 is output during the non-display period. This switching is performed using the display address signal (DAE-1) output from the display address signal generation circuit 10. When writing data from the CPUI to the display memory 7, the bus driver 6 outputs data on the data path (DATA BUS) to the display memory 7. A synchronizing signal generating circuit 1 generates a synchronizing signal (SYNC') for television and also generates a control signal to a display address signal generating circuit 10. Using this control signal, the display address signal generation circuit 10 generates a read address signal for the display memory 7 and various control signals (display clock signal CK, pattern writing latch signal PL).
.

The color latch signal CL4 outputs a switching signal YCC) for switching between the pattern address signal and the color address signal. The color address decoder 12 decodes the color address signal from the read address signal, and the switching circuit 13 at the next stage switches between the pattern address signal and the color address symbol and outputs the pattern address signal (YCC'l). Target r (reads out. Chip ψ select circuit 1
4 is a circuit that generates a chip select signal for the display memory 7 in relation to the read address signal. The data read from the display memory 7 is converted into a display address signal (
DAE-1) is output as pattern information Y and input to the color matrix decoder 17. On the other hand, color information C from the display memory 7 is input to the color latch circuit 16 and latched. By the way, the circuit shown in FIG. 4 is provided with a color display control device 18 shown by a broken line. The color display control device [18] uses the pattern information Y to latch vertical display address data (VDA) from the display address signal generation circuit 10, and stores the address of the last line where the pattern information Y exists; Further, the vertical synchronization pulse (VP) is used to store the data in a vertical period, and it is determined whether the stored data matches the vertical display address data (VDA) from the display address signal generation circuit 10, and the next horizontal period when the data matches the vertical display address data (VDA) is determined. The control signal (1) AE-2) is outputted, and the output of the color latch circuit 16 is stopped by this control signal (DAg-2). The color display control unit u18 is controlled by receiving a display address signal (DAE-1) from the display address signal generating circuit 1°, as well as a vertical synchronizing pulse (VP) and a horizontal synchronizing pulse (HP).

FIG. 5 is a circuit diagram showing an example of the color display control device 18 shown in FIG. 4, and FIG. 6 is a timing chart illustrating its operation.

In FIG. 5, the color display control device 18 is a latch circuit 19.
．． Latch circuit 20. Comparison circuit 21° flip-flop 22. It is composed of a flip flop 23 and an OR gate 24, and inputs the pattern information Y read out from the display memory 7 to the latch circuit 19 as a latch clock, and outputs the vertical display from the display address signal generation circuit 10. Store address data (VDA). Therefore, the operation of the latch circuit 19 is stopped at the address of the last line where the pattern information Y is output, and the latch circuit 2o of the next stage is stopped.
Then, the field is stored in a vertical period by the vertical synchronization pulse (VP) from the display address signal generation circuit 10, and the stored data for that field is input to the comparison circuit 21. The comparison circuit 21 includes a display address signal generation circuit 10.
Vertical display address data (VDA) is inputted therein, a match between this data (VDA) and the stored data is detected, and a match signal (cAD) '4 is output.

The coincidence signal (cAD) is a horizontal synchronization pulse (HP
) is latched into the flip-flop 22 as a clock input. The latched signal (cAD') is flipped
The clock terminal (cK) of the flop 23 is connected to VCC, and the output terminal (Q) is set to the "H" level.The vertical synchronizing pulse (VP) is input to the clear terminal (CL"l) of the flip-flop 23. This signal (vP) becomes the output terminal Q/ii'L level.In this way,
A display gate control signal (CAG) from the vertical period is generated from the clip flop 23, and the display gate control signal (CAG) from the vertical period is generated and used for the next stage's OR game.
) 24Vc is input. The OR gate 24 performs a logical sum with the display address signal (DAE-1) to obtain a display address signal f'DAE-2). In other words, the display address signal (DAE-2) is output from the beginning of the display screen to the line where pattern information Y exists.

The display address signal f'DAE-2) is sent to the color latch circuit 16.
The color information C is input to the output limiting terminal of the color information C, and the output of the color information C is controlled.

This situation is shown in the timing e-chart of FIG. In FIG. 6, the symbol SYNC indicates the synchronization signal from the synchronization signal generation circuit 11, and V-3YNC indicates the vertical synchronization period, H
-8YNC indicates the horizontal synchronization period. Further, DAE-1 is a display address signal and is used as a display gate signal of the ORL gate 24. VP is a vertical synchronization signal, H
P is a horizontal synchronization signal. CAD shows coincidence pulse;
CAD' indicates the noculus generated in the next coincident horizontal period, and CAG indicates the display gate control signal from the vertical period. DAE-2 is the output of OR gate 24 and is the display address signal that controls color latch circuit 16. Therefore, if the circuit shown in FIG. 5 is used, the color information C can only be output up to the line of the received pattern information Y. , FIG. 7 shows an example of display by the color display control device of the present invention. Reference numeral a indicates a display area on the display screen, and a portion receiving pattern information (indicated by diagonal lines) is colored, but a portion d, which is not receiving pattern information t, is not colored. Regarding this part dVc, the color information is sent block by block, so either it actually exists as a signal, or the color data output is restricted by the line address of the pattern information, so it is not displayed on the display screen. Not done.

〔Effect of the invention〕

As described above, according to the present invention, pattern information, which is sent line by line, and color information, which is sent block by block, is received externally, and the pattern information, which is output in large quantities, is received vertically from the display memory. The display address data in the vertical direction is latched, the address of the final line where pattern information exists is stored, and the address is further stored in the vertical period, and it is determined whether the stored data matches the display address data in the vertical direction, and a match is made. A control signal is generated based on the signal, and this control signal is used to control the output of the color data that is output from the display memo round during the next horizontal period when both data match. In the part of the screen where pattern information is being received, the BG color is displayed in blocks sequentially in the pattern display, and in the part where the pattern information is not being received, the BG color is displayed in blocks.
When the G color is displayed, there is an effect that '' disappears.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional display control device, Figure 2 is a timing chart explaining the circuit operation of Figure 1, and Figure 3 is a block diagram of a conventional display control device.
FIG. 4 is an explanatory diagram showing a display screen based on the circuit of FIG. 1, FIG. 4 is a block diagram showing a color display control device according to the present invention,
Figure 5 is a circuit diagram showing an example of the color display control device shown in Figure 4.
FIG. 6 is a timing chart explaining the circuit operation of FIG. 5, and FIG. 7 is an explanatory diagram showing a display screen based on the present invention. 1...CPU, 7...Display memory, 10...
- Table bore address signal generation circuit, 11... Synchronization signal generation circuit, 15... Circuit that performs pattern launch and parallel-to-serial conversion, 16... Color latch circuit, 17...
Tomoe matrix decoder, 18... Color display control device, 19.20... Launch circuit, 21... Comparison circuit, 22.23... Clip or flop, patent applicant Tokyo Shibaura Electric Co., Ltd.

Claims (1)

[Claims] In an apparatus for receiving external luminance information and two-color information, storing the information as tod pattern data and color data in a display memory using a microprocessor, and displaying a still image on a color display, the display memory comprises: a first storage means for launching the display address data in the vertical direction, which is frequently outputted from the display address signal generating means, using the luminance information outputted frequently, and storing the address of the last line where the luminance information exists; , a second storage means for further storing the stored address data in a vertical period; and vertical display address data which is output multiple times from the data stored in the second storage means and the display address signal generation means. and means for generating a control signal based on the comparison result of the comparison means, and the control signal is generated from the next horizontal period in which both the data compared by the comparison means match. A color display control device characterized in that the output of the color data that is outputted from the display memory is stopped using the above-mentioned display memory.