JPS5975788A - Color display controller - Google Patents

Abstract

PURPOSE:To prevent colored display where pattern information is not sent out when color information is painted in background color, by providing a comparing means which compares the output data of a CPU which outputs an address signal for externally received color information with vertical color address data. CONSTITUTION:A color display controller consists of an output port 18 and a color display control circuit 19 and the output port 18 outputs the vertical display address data of color information of external receive data (EXT DATA) from a CPU1 to a color display control circuit 19. The color display control circuit 19 inputs color information C from a color latch circuit 16 synchronously with a display address signal (DAE) and inputs converted color information C' to a color matrix decoder 7. In this case, the color display control circuit 19 judges a coincidence with vertical color address data from a color address decoder 12 and inputs said converted color information C' to a color matrix decoder 17 after obtaining the coincidence.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a color display control device, and particularly to a teletext broadcasting system and a captain that receive brightness information and color information and display still images on a display screen. [Phase] This invention relates to a color display control device in a still image information system such as a system.

[Technical background of the invention]

Conventionally, in still image information systems such as teletext broadcasting systems and captain systems, there are a code transmission method used in Western European countries and a pattern transmission method used in Japan. In the code transmission method, information is sent as codes from an information center, and each terminal uses patterns and codes prepared for it.
Convert codes to characters and figures using a generator.

In the pattern transmission method, a large-scale pattern generator installed at an information center (R) is used to create patterns of characters and figures in advance, and the signals are transmitted as they are to television terminals in homes etc. for display.Pattern transmission In this method, pattern information and color information are sent independently, pattern information is sent line by line, and color information is sent by block rather than line by line.Blocks of color information are sent by characters used on the display screen. It is determined based on the font, and has a composition of, for example, 8 dots horizontally x 12 dots vertically, and its coloring units include background color C (hereinafter referred to as BG color) and designated color (hereinafter referred to as FG color). There is.

Conventionally, in still image information systems such as teletext systems and captain systems, a display control device equipped with an image memory is installed on the receiving side, and this device is used to transmit information sent from an information center to a television receiver. Convert it into a signal for display on the screen. Dot pattern data and color data are stored in the image memory, and the data is generally stored in 8-bit parallel data in correspondence with the address. When pattern information is read out during the display period, it is read out in units of display clocks, parallel-to-parallel converted, and input to a color matrix decoder along with color data.
The primary color signal and luminance signal are obtained and displayed on the display screen.

FIG. 1 is a block diagram showing a conventional display control device.

In FIG. 1, a CPUUI, a working RAM 2 for the CPU,
Buo Clam RO? A chip select circuit 4 outputs a signal to select RAM 2 and ROM 3, and an input capacitor receives externally received data (EXT DATA).
)5u, address bus (ADDRESS BUS')
The externally received data (EXT DATA') input to the input port 5 is displayed via the bus driver 6 according to CPU processing. Written to memory 7. The display memory 7 stores dots and brightness information.
Putter: / m Dot pattern that accumulates data
It consists of a memory and a color memory that stores color data for coloring each coloring block. The dot pattern memory chip and the color memory chip are chip
It is selected using a chip select signal generated from the select circuit 8. The switching circuit 9 performs switching so that the read address signal is output during the display period of the display memory 7, and the address signal from the CPU 1 is output during the non-display period. This switching is performed using the display address signal (DAE) output from the display address signal generation circuit IO. When writing data from the CPUI to the display memory 7, the bus driver 6 uses the data bus (DA
TA BUS ) data is output to the display memory 7.

The synchronization signal generation circuit 11 generates a synchronization signal (S
YNC) and display address signal generation circuit 1.
Generates a control signal to 0. Using this control signal, the display address signal generation circuit 1o generates a read address signal for the display memory 7 and various control signals (display clock signal CK, pattern latch signal PL).

A switching signal (Ycc) for switching between the color latch signal CL, pattern signal, and color address signal is output. The color address decoder 12 decodes the color address signal from the read address signal, and the next stage switching circuit 13 uses a switching signal (YCC) to switch and output the pattern address signal and the color address signal, thereby multiplexing the signal. Read data automatically. The chip select circuit 14 is a circuit that generates a chip select signal for the display memory 7 in relation to the read address signal.

The data read from the display memory 7 is output as pattern information Y in synchronization with the display address signal (DAE) by a circuit 15 for pattern latch and parallel-to-serial conversion, and is input to a color matrix decoder 17. Ru. on the other hand,
Color information C from display memory 7 is latched by color latch circuit 16 and input to color matrix decoder 17 in synchronization with display address signal (DAE). The color matrix decoder 17 combines pattern information Y and color information C, and outputs primary color signals R, G, B and luminance information Y.

In such a configuration, when the display address signal (DAE) synchronized with the synchronization signal (SYNC) is output multiple times from the display address signal generation circuit 10 as shown in FIG. , bus driver 6, pattern latch and parallel-to-serial conversion circuit 151 is input to the color latch circuit 16, pattern information Y (indicated by diagonal lines) is output from the circuit 15, and at the same timing, the color latch circuit 16 outputs color information C (indicated by diagonal lines).

However, in FIG. 2, the symbol A indicates the display period.

[Problems with background technology]

However, in the conventional display control device shown in FIG.
Since pattern information Y and color information C are output independently from the pattern latch and parallel-to-serial conversion circuit 15 and color latch circuit 16, the display address signal ( There was a drawback that the color information C was output at the timing of DAE).

That is, when the color information is BG coloring in the block unit color information and the line unit pattern information, as shown in FIG. The shaded area) is colored BG, but there is a drawback that the area C, which has not received pattern information, is also colored.

[Purpose of the invention]

The object of the present invention has been achieved in view of the above-mentioned points, and when the color information is BG coloring, it is possible to prevent portions to which pattern information is not transmitted from being displayed in color. An object of the present invention is to provide a color display control device.

[Summary of the invention]

The color display control device of the present invention receives external data including brightness information and color information from an external source, and stores the data as dot pattern data and color data in an image memory (display memory) using a CPU. This relates to a display control device for an image memory that stores and displays still images on a color display, and includes an output means for outputting an address signal of color information received from the outside from a CPU, and an output from the output means. a comparison means for comparing the data with the vertical color address data from the color address decoder; a means for generating a control signal based on the comparison result of the comparison means; converting means for converting the color information of the data, and before the two data compared by the comparing means match, the color information from the image memory is output, and after the match, the converted color information is output. It consists of:

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 4 is a block diagram showing a color display control device according to the present invention. In this figure, "j-" has the same function as in Figure 1.
In the description, the same reference numerals are given to the same parts. Therefore, the parts with the same reference numerals as in FIG. 1 are the same as the conventional circuit, and the broken line part is the color display control device of the present invention.

In Figure 4, CPUUI, work RAM2 for CPU
, program RC) M3.1°C The chip select circuit 4 that outputs a signal to select AM2 and ROM3, and the input port 5 that receives external reception data (EXTDATA) are connected to the address 0 bus (4DDRESS BUS).
) and a data bus (DATABUS), and externally received data (EXT DATA) input to the input port 5 is written to the display memory 7 via the bus driver 6 according to CPU processing. It will be done. The display memory 7 stores dots, patterns, and brightness information.
It consists of a dot-fist pattern 0 memory that stores data, and a color memory that stores color data for coloring each colored block. Dot pattern memory
The chips and color memory chips are selected using a chip select signal generated by a chip select circuit 8.

The switching circuit 9 performs switching so that the read address signal is output during the display period of the display memory 7, and the address signal from the CPU 1 is output during the non-display period. This switching is performed using the display address signal (DAE) output from the display address signal generation circuit IO. When the bus driver 6 writes data from the CPUI to the display memory 7, it outputs data (DATABUs) to the display memory 7. The synchronizing signal generating circuit 11 generates a synchronizing signal (SYNC) for television and also generates a control signal to the display address signal generating circuit 10. Using this control signal, the display address signal generating circuit 1o generates a read address signal for the display memory 7 and various control signals (display clock' signal CK, pattern latch signal PL).

It outputs a color latch signal CL and a switching signal YCC''l for switching between a butter address signal and a color address signal.The color address decoder 12 decodes the color address signal from the read address signal and outputs the color address signal YCC''l for switching between the butter address signal and the color address signal. The switching circuit 13 uses a switching signal (YCC) to switch and output the pattern address signal and color address signal,
Perform multiple reading. The chip select circuit 14 is a circuit that generates a select signal for the display memory 7 in relation to the read address signal. The data read out from the display memory 7 is sent to a display address signal (DAE) by a pattern latch and a circuit 15 for parallel-to-serial conversion.
') is output as pattern information Y and input to the color matrix decoder 17. On the other hand, display memory 7
The color information C from is input to the color latch circuit 16 and latched. By the way, the circuit shown in FIG. 4 is provided with a color display control device shown by a broken line. The color display control device is composed of an output port 18 and a color display control circuit 19, and the output port 18 outputs vertical display address data of color information of externally received data (EXT DATA) to the CPU 1 for color display control. Input to circuit 19.

The color display control circuit 19 inputs the color information C from the color latch circuit 16 in synchronization with the display address signal f'DAE)VC.
The converted color information C' is input to the color matrix decoder 12. In this case, the color display control circuit 19 determines whether the output data from the output port 18 matches the vertical color address data from the color address decoder 12, and after matching, converts the converted color information C' into input to color matrix decoder 12; Output port 18 is a chip
The color display control circuit 19 is controlled by receiving a control signal (CE) from the select circuit 4, and the color display control circuit 19 is controlled by receiving a vertical synchronizing pulse (VP) from the display address signal generating circuit 10.

FIG. 5 is a circuit diagram showing an example of the color display control circuit 19 of FIG. 4, and FIG. 6 is a timing chart illustrating its operation.

In FIG. 5, the vertical display address data of the latest received color information is transferred to the data bus (DATA BUS).
) is input to the output port 18. Output port 1
The output data of more than 8 is input to the color display control circuit 19. The color display control circuit 19 is connected to the comparison circuit 20 by a flip
It is composed of two flops and a switching circuit 22, and the vertical display address data output from the output port 18 is input to a comparison circuit 2o, and the vertical color address data input from the color address decoder 12 is input to the comparison circuit 2o. data('
CVA), and when both address data match, a match signal (CAD) is output and input to the clock terminal (CK) of the flip-flop 21.

A vertical synchronizing pulse (VP) is input to the clear terminal (CL) of the flip 70 tube 21, and the signal (vP) is used to shift the output signal (CAC') from the output terminal Q to the ゝL' level. Therefore, when the coincidence signal (CAD) is output, the output signal (cAc) becomes an ant H level.

The above output signal (CAC) is sent to the switching circuit 22 as a switching signal.
is input. Color information C is input to the switching circuit 22, and when the switching signal (CAC) reaches the 'XH// level, the color information C is switched between 4 bits of upper information and 4 bits of lower information, and the upper information is changed to 4 bits. The 4-bit data is left as is, and the lower information 4-bit outputs the same data as the upper information 4-bit. In this way, the converted color information C' is output from the color display control circuit 19 and input to the color matrix decoder 17.

This situation is shown in the timing chart of FIG. As shown in Figure 6, the switching signal (CAC) is at the 2H level at the start-up of the matching code (CAD). Color information C always outputs FG color and BG color information. but,
For color information C', when the switching signal (CAC) is at the LI level, FG color and BG color information is output, and when the switching signal (CAC) is at the HII level, FG color = BG color (-=: raster Outputs color information. Regarding pattern information Y, the left side of the broken line shows information on the previous line, and the right side shows information on the next line. FIG. 7(a), (ti indicates an example of display by the color display control device of the present invention, symbol a indicates a display area on the display screen, and as shown in FIG. With the color information that follows, only the part where the pattern information Y is present is FG colored, and when it comes to the first line of the next row, it is colored FG for the previous block unit as shown in Fig. 7 (+)).
c, BG colored. Therefore, when color information and pattern information are sequentially sent, unnecessary coloring is virtually eliminated.

〔Effect of the invention〕

As described above, according to the present invention, pattern information that is sent line by line and color information that is sent block by block are externally received, and the address and address of the received color information are
Data is pushed from the CF'U to the output port, this output data is compared with the vertical color address data from the color address Φ decoder, and when they match, a signal is output and a control signal based on that signal is used. Converting color information data (for example, switching between upper and lower bits)
Therefore, based on the color information sent in blocks on the display screen, only the part with pattern information is first colored by FC, and when the first line of the next block is reached, the color information is applied to the previous block. Since BG coloring is not performed, there is an effect that unnecessary color display is virtually eliminated.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional display control device, Figure 2 is a timing chart explaining the circuit operation of Figure 1, and Figure 3 is a block diagram of a conventional display control device.
FIG. 4 is an explanatory diagram showing a display screen based on the circuit of FIG. 1, FIG. 4 is a block diagram showing a color display control device according to the present invention,
FIG. 5 is a circuit diagram showing an example of the color display control circuit of FIG. 4;
FIG. 6 is a timing chart explaining the circuit operation of FIG. 5, and FIG. 7 is an explanatory diagram showing a display screen based on the present invention. 1...CPU, 7...Display memory, 10...
- Display address signal generation circuit, 11... Synchronization signal generation circuit, 15... Circuit that performs pattern latch and parallel-to-serial conversion, 16... Color latch circuit, 17
- Color matrix decoder, 18... Output port, 19... Color display control circuit, 2o... Comparison circuit, 21-... Flip-70 tube, 22...
- Switching circuit, Y...pattern information, C...color information, C'...converted color information, CVA...vertical color address data. Patent applicant Tokyo Shibaura Electric Co., Ltd.

Claims (2)

[Claims] (1) Receive luminance information and one color information from the outside, and
A dot pattern is stored in display memory using a processor.
In a device that stores still images as data and color data and displays still images on a color display, an output means for outputting a display address and data of color information received from an external device to the microprocessor; comparing means for comparing the output data of the color address decoding means with the vertical color address data from the color address decoding means, and means for generating a control signal based on the comparison result of the comparing means;
A conversion means is provided for converting the color information of the display memory using the blood control signal, and the color information of the display memory is output before the two data compared by the comparison means match. , a color display control device that outputs converted color information after matching. (2) The conversion means is constituted by a switching circuit that switches between upper and lower color information of the color information from the display memory based on the coincidence signal from the comparison means, and before the two data match, the display Upper level information of color information from memory,
2. The color display control device according to claim 1, wherein the color display control device outputs both the lower order information and, after matching, outputs the same data as the upper order information and the lower order information of the color information.