JPS5923388A - Color display controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] In recent years, the scope of use of television receivers has been particularly expanded, such as by superimposing text information on television signals and transmitting text information through telephone lines. There is a system to do that.

The present invention relates to a color display control device for projecting these broadcasts on a television screen. Color information is stored and read out according to colored units (also called color blocks).

The character information targeted here is the dot pattern data, which is the luminance information necessary to configure the display screen, the coloring when the specified coloring unit O, and the dot pattern data is "1". and color information data specifying coloring when the value is 0''.

[Background technology of the invention and its problems]

The color blocks commonly used today are determined based on the character fonts used on display screens, and are 8 dots horizontally by 12 dots vertically.

The size of this colored block is reasonable when the display screen consists mainly of characters, but when the display screen RFII consists mainly of graphics, finer color blocks are required. Figure 1 shows the type of color blocks, (a)
(b) is the standard 1x mode color block, (b) is the 4x mode color block with the size of 14 of the 1x mode color block, (6x mode color block with 4 horizontal dots and 4 vertical dots) show.

If the color Glock is subdivided in this way, it is natural that the color information must be increased. For this reason, in systems where an increase in transmission speed cannot be expected, such as teletext broadcasting, the time required to configure one screen increases accordingly, meaning that a large amount of information can be sent in a short period of time. One possible method is to specify the amount of data and send the corresponding amount of data.

According to this method, the color block coloring shown in Fig. 1(a) is specified for a screen mainly composed of text, and the coloring shown in Fig. 1(b) or (C) is specified for a screen mainly composed of figures, depending on the fineness of the figure. The data will be sent at the same time while specifying the size. Therefore, a device is required to receive data based on such a system, decode it, and display it on a television receiver.

However, in the above device, if the same color information data is not read for the same period during the period when one byte of dot pattern data (referred to as pattern data for ν) is read, the same address signal for reading may be used, but as shown in FIG. (
In the case of b), two types of color information data must be read out during the horizontal scanning period. Also, in the vertical direction, all of the other color information data must be read out at the position of the 7-dot line. There is a problem in that the same address signal cannot be used for reading for this purpose, which complicates the address switching operation.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is a color display that reads color information from a color information memory according to a coloring unit specified in advance on the transmitting side, and enables address switching for this purpose without increasing the amount of hardware. The purpose is to provide a control device.

[Summary of the invention]

That is, in the present invention, the horizontal color information data required when the reference coloring unit is subdivided according to the data size of the pattern data PD is stored in the second color information memory 3, etc., and read out. The color information data is selectively and alternately extracted by a switching signal generated in response to a code signal specifying coloring, and the vertical color information data is address converted by line conversion using the code signal. The coloring unit is read out according to the size of the colored unit.

[Embodiments of the invention]

FIG. 2 is a circuit diagram showing an embodiment of the present invention, for example, when it is used in a teletext television receiver. This circuit adds new writing and reading procedures when writing and reading received image information to the image memory, and supports color block designations that have been transformed into 4x mode, 6x mode, etc. This is for selecting color information data.

First, a configuration for writing image information into an image memory will be described. The image memory is composed of a pattern memory 1, a first color information memory 2, and a third color information memory 3, which share the address line MA with each other, and the data lines are connected to the pattern data 1 and the first color information memory 2.
, and only the second color information memory 3 has different data lines. Each of the memories 1, 2, and 3 is a memory that performs data input/output operations in 8-bit parallel fashion. Further, the output of the address switch 4 is supplied to each memory.

This address switch 4 is a data selector that switches between the address bus B of the CPU 5 and the read-r address RA for sequentially reading image memory data in accordance with scanning. The switching signal for this switching is generated by a timing pulse generator 8 from each output of a horizontal counter 6 that counts the display clock DCP in synchronization with horizontal scanning and a vertical counter 7 that counts horizontal synchronization pulses 0 in synchronization with vertical scanning. This is the display readout period signal DSE. When this period signal DSE is input to the address switch 4, the address line kite of the image memory selects the read address RA, which is also the output of the horizontal counter 6, and when the same signal DSE is not present, the address line kite selects the address. Select bus AB.

Next, in the data line of the image memory, the pattern memory 1, the data line D-1 of the first color information memory 2
is controlled by the first bus controller 9. In other words, the first bus controller 9 is connected to the data bus D of the CPU 5.
B, and isolates the data bus DB from the data line D-1 when selecting write data output from the data RAM 10 or serial data output from the parallel-serial converter 11. It is something. Further, the data in the second color information memory 3 is controlled in a similar manner. These control signals are the display readout period signal DSE.

Next, the address bus AB of the CPU 5 is connected to the chip selection circuit 13. This chip selection circuit 13
! This is a circuit that generates the Chiso fs selection numbers C8P, C8C1, and C8C2 that control whether to activate or deactivate the image memory, csp goes to the pattern memory 10 chip select terminal, and csc i goes to the first color. Information memory 2
and C8C2 are applied to the same terminal of the second color information memory 3, respectively. Each memory of the image memory receives these chip selection signals C3P-C8C2,
In combination with the data write control signal WR derived from the CPU 5, a write state or a read state is determined.

The chip selection circuit 13 also outputs a display readout period signal DS.
E and the third stage output 6Q3 of the horizontal counter 6 are input. These input signals form the chip selection signal.

In this way, data can be loaded into the image memory during one period (the original display readout period) when the display readout period signal DSE is not generated. For example, when writing 79th turn data to address (M-N) of turn memory 1 (corresponding to the Nth line M from the display start line) (corresponding to the item), the CPU 5G or address AP+ 32N+
M (Ap is the start address of the area occupied by pattern memory 1 in the address space controlled by the CPU.
Since the coefficient 32 is allocated a memory capacity of 256 dots per line), it simultaneously outputs the write control signal WR for each memo and outputs the pattern data PD to the data node D13G. Output this.

The CPU 5 recognizes the non-display period by the display reading period signal. As a result, the chip selection circuit 13
generates a signal C8P for selecting pattern memo 1, and pattern memo 1 becomes active. Also, during the display readout period i, the first address switch 4 selects the address bus AB by DSE and connects the address line MA common to each memo 1J.
The address signal of C address no(s) AB is derived, and the address becomes (32N+M).

At the same time, the write control signal WR makes it possible to write data into the memo 1 cell corresponding to the address (32N+M) of the no-turn memo 1 no 1. At this time, data is input to the first node (data node I of the CPU by the display readout period signal DSE of the controller 9).
Since the pattern data PD is shared with the data line D-1 of the turn memo January, the pattern data PD is stored in the previous B memo 1 cell. Thus, the 7th turn data PD writing force is performed.

Also, at the same time as writing the pattern data PD, the color scheme report data CDt according to the color block specified by the sending side is
-Accumulate. That is, when the color glock 75 is 8 dots horizontally, it is written in the first color information memo 1) 2 according to the address designation of the pattern data PD and the controller.

Also, when the color block is 4 dots horizontally, G is the number of mountains (1
Write the color information data in the first color information memo 1) 2.
In this case, the color information data numbers of odd-numbered columns are written into the second color information memory 3.

Next, a configuration related to generation of an address when reading out a display from the image memory will be described.

Pattern memory 1, 1st. Second color information memory 2, 3
The address is generated from the outputs of horizontal and vertical counters 6.7, which count in synchronization with CRT scanning. The horizontal counter 6 is a counter that is reset by a horizontal synchronizing pulse HD at the start point of display readout in each horizontal scanning period, and counts the display clock (set to the same period as one dot display time) DCP. The vertical counter 7 is a counter that is reset at the display start line of every vertical scanning period (by the vertical synchronizing pulse VD) and counts the number of horizontal synchronizing pulses.

The output of the upper 5 bits from the 4th stage of the horizontal counter 6 is the first
It is input to the address switch 4 through the address line RA'. The vertical counter 7 inputs an 8-bit count output to the second address switch 14 and line converter 15.

This line converter 15G receives the same code signal Ke from the coloring unit designation register 16 which holds the code signal K for designating the coloring unit by the JCPU 5. This line converter 15 also creates a vertical address for reading out color information data. The output value of the vertical counter 7 is converted from the vertical address of the second color information memories 2 and 3 according to the vertical size of the coloring unit. Specifically, if the output values of all stages of the vertical counter 7 are the number of vertical dots in the L1 coloring unit as ■ line, then IN
A conversion is performed such that T (L/I > The answer may be stored in ROM in advance so that the above conversion can be performed.

Further, the second address switch 14 selects the vertical address for the pattern memory l and the first address for the pattern memory l. It is a data selector that switches and outputs the vertical addresses for the second color information memories 2 and 3, and uses, for example, the third stage output of the horizontal counter 6 as the switching control signal. This third stage output is a signal that is switched every time four dots of pattern data PD are displayed. The output of the second address switch 14 is input to the first address switch 4 as a vertical address signal through the address line RA. The display readout address formed by this configuration is commonly input to each memory 1, 2, and 3 by the first address switch 4 during the display readout period.

Next, a configuration for processing all output data of the image memory will be described. The pattern data PD and the color information data CD are the output 6Q of the third stage of the horizontal counter 6 as shown in FIG.
It is switched every 30 half cycles and is led out onto the data line MA. This switching data is indicated by the symbol ma. Further, the horizontal address signal is updated every half cycle of the fourth stage output 6Q4 of the horizontal counter 6. The unit of pattern data PD appearing on data line D-1 is PMO, the unit of color information data CD is CMO1, and data line D-
The unit of the color information data CD appearing in 2 is CMO2, and each data is changed to P each time the horizontal address signal is updated.
MO(11, PMO(2)-, CMO1(0), C
MO2(IL・ , CMO2(0), CMO2
(1) The process proceeds as follows. This situation can be seen in the time chart of FIG. 3, where the data d-1 on the data line D-1. It is shown as data d-2 on data line D-2. The color information data unit CMOI, 2 is read earlier by the first four dots of the horizontal address period of the pattern data unit PM, Oj color block unit, and the valley data PMO(1) of the pattern data PD is read out in the latter four dots.

PMO(2)... is read out. This is because after the chip selection circuit 13 generates the chip selection signals C8C1 and C8C2, the signal C8P for selecting the pattern memory 1 is generated. Of the data d-1, the color information data unit CMO] is supplied to the data selector 19 via the first color data latch circuit 17 and the second color data latch circuit 18. Also, color information data unit C of data d-2
MO2 is supplied to the data selector 19 through the third color data latch circuit 20 and the fourth color data latch circuit 21. A latch pulse LP1 is applied from the timing generator 8 to the first color data latch circuit 17 and the third color data latch circuit 20, and the color information data unit CM is read out.
O1 and CMO2 are latched until the next launch pulse LP1 is applied.

Here, when the chip selection signal C8P is generated, the address from the vertical counter 7 is switched and the data line D-
Pattern data PD is read out on the 1st. This pattern data PD is applied in parallel to the parallel-serial converter 11,
This parallel-to-serial converter 11 converts the data into serial data SPO using the load pulse LP2 obtained from the timing generator 8. This load pulse LP2 is the second. It is also used as a latch pulse for the fourth color data latch circuit 18.21. The second color information data CD is further delayed for every data unit. That is, as shown in FIG.
0 as continuous data of the output kLcD4 of the fourth color data latch circuit, the color data latch output LCD1 is delayed by 4 dots and input to the data selector 19, and the color data latch output LCD3 is similarly input. The signal is input to the data selector 19 with a delay of 4 dots. As a result, each color information data CD is synchronized with the pattern data PD. At this time, the data selector 19 receives a switching signal CDS for data selection from the timing generator 8. There are two types of switching signals, CD5l and CD52, as shown in FIG.

CDS is a signal when the color block is specified as 8 horizontal dots, and is always the output data L of the second color data latch circuit 18.
CD2'? select. In addition, when the color block is specified as 4 dots horizontally, the data LCD2 of the second color data latch circuit 18 is selected during the first four dot period, and the data of the fourth color data latch circuit 21 is selected during the second half four dot period. LCD
4 is selected.

Selected color information data in case of symbol CDI+C
It is shown in D2. Each of these data LCD1. LCD2
is output from the parallel-to-serial converter 11. Since it is time-aligned with the serial pattern data PDS, it is as it is.
- The signal is input to the G-B multi-color IJ circuit 22, where it is converted into a primary color signal and output. The output of this R-G-B matrix circuit 22 is supplied to a CRT drive circuit, and each specified color block is colored and displayed. Furthermore, CPU 5
All the various processes are carried out by programs fixed in the ROM 23.

The reading operation when the color block is designated as 4 horizontal dots in the above configuration device will be described. The table shows the specified codes for each case: 1x mode when the color block is 8 dots horizontally and 12 dots vertically, 4x mode when the color block is 4 dots horizontally and 6 dots vertically, and 6x mode when the color block is 4 dots horizontally and 4 dots vertically. show.

First, when the display readout period signal DSE rises, the first address switching circuit 4 selects the address line RA. As a result, the Tesozo selection circuit 13 is separated from the control of the CPU 5 and selects each chip selection signal C8P, C8C1 according to the value of the output 6Q3 of the third stage of the horizontal counter 6.

C8C2 starts and pattern memory l, 1st. Set the second color information memory 2.3'f-reading state.

Now, when the coloring designation code "10" is generated from the CPU 5 and held in the coloring unit designation register 16, the line converter 15 creates an address corresponding to the color block designated for coloring. That is, if the color glock is the size of the 1x mode, line conversion ■NT (142) is performed, if it is 4x mode, line conversion (L/6) is performed, and if it is 6x mode, line conversion (V4) is performed. ) and perform the first step. The vertical address for reading the data of the second color information memo 1J13 is converted. The first line created by the line converter 15. Second
The vertical address for the color information memory and the vertical address for the non-turn memo 1) January are switched by the address converter 14 at the half cycle XJI of the third stage output 6Q3 of the horizontal counter 6. As a result, the 3m address line kite of the image memo 1J has an address power that changes every 4 dots of the 8 dots of 7-year turn data PD. In FIG. 3ma, symbols CA and PA indicate an address for color information and an address for pattern data, respectively. On the other hand, since the horizontal address 1'i of the horizontal counter 6 is switched (l, % is not present), the address for the turn data PD and color information data progresses at the rate of the fourth stage output 6Q4, which is the least significant bit of that address. do.

In this way, when a color block such as 4x mode or 6x mode is specified, the address is only switched according to the vertical thickness of the color block, and the pattern data P is changed horizontally.
Two color information data CD are read while D is read by one byte.
There is no need to read bytes either.

Next, do the first four dots of the first half of the color block. C3C1 and C are sent from the chip selection circuit 13 to the second color information memories 2 and 3.
3C2 is applied, so the address line 1.3C2 corresponding to the address of the kite is applied. Second color information data CMO1, CMO
2 is output. These data CM01. CM02 is the 1st. The third latch circuit 17.20 is latched by the latch pulse LP1 from the timing generator 8, and the second latch circuit 17.20 of the next stage is latched. The fourth latch circuit 18.21 delays the signal by four dots. As a result, the data selector 19 synchronously receives the latch output data LCD2+LCD4 for coloring the serial pattern data PD of the parallel-serial converter 11. Here, the data selector 19 receives a switching signal CD for data selection supplied from the timing generator 8.
A CD where S changes every 4 dots according to the coloring designation code K.
It is 52. Therefore, the latch output LCD of the second color data latch circuit 18 is
2 is selected, and the latch output LCD2 of the fourth color data latch circuit 21 is selected in the latter four dots. These selected latch output data LCD2. The LCD 4 can designate a color by switching between the first half and the second half of the color block for the one-dot data DOID1 . . . of the no-turn data PD.

In this way, the present invention makes it possible to color pattern data PD according to a designated color block without increasing the number of address switches for special color block designations. Note that the size of the color block is not limited to the 4x and 6x modes, but the present invention can also be extended to specify other sizes.

〔Effect of the invention〕

As explained above, according to the present invention, a memory is provided for storing color information when a coloring unit is subdivided and designated, and the read color information is selected according to the coloring designation. Thus, it is possible to receive character/graphic information colored and displayed in various coloring units without increasing the switching of address lines. Moreover, the time required to write and read the memory does not depend on the coloring unit.
There is also an advantage.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing a coloring unit, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a time chart showing the read operation timing of FIG. 2. 1...Pattern memory, 2.3...Color information memory, 4,14...Address switch, 5.
...CPtJ. 6゛°horizontal counter, 7°...vertical counter,
8...Timing generator, 9.12...ノ(
controller, 10.degree.RAM, 11.parallel-serial converter, 13.chip selection circuit, 1
5... Line converter, 16°°° coloring unit specification register, 17.18.20.21... Color data launch circuit, 19... Data selector, 22°°゛R・
G-B matrix circuit, K...° code signal, CDS
...Data switching signal. Figure 1

Claims (1)

[Scope of Claims] A device for displaying pattern data in color according to the size of a specified coloring unit by subdividing a reference coloring unit, comprising a pattern memory and a common address line and a data line in this memory. A first color information memory that stores first color information data for subdividing and coloring the coloring units; an address line is common to each of the memories, and a data line is independent; a second color information memory that stores all of the color information data of No. 2; a horizontal counter and a vertical counter that generate addresses for reading the data stored in each memory; and a code that specifies the size of the coloring unit. a register that holds signals; a line conversion circuit that performs line conversion of the reference coloring unit according to the code signal; a parallel-serial conversion circuit that converts the read pattern data into serial data; ．． J, second, which delays the second color information data to a timing synchronized with the serial data;
latching means; A color display control device comprising: a data selector that selects the output of the second latch means according to a designated coloring unit.