JPS58105189A - Display memory controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a display memory control device, which stores data sent as a digital signal in a memory and displays it on a display screen of a television receiver. It is used in signal processing systems to obtain signals.

[Technical background of the invention]

Recently, in consideration of the versatility of television receivers, teletext systems and systems for transmitting display data using telephone lines have been developed.

These systems are configured to superimpose digital data that serves as a display source onto a transmission medium (radio waves, dedicated frequency signals), and then sample this digital data on the television receiver side. The sampled data is classified into various types, such as program data, pattern data, color data, and control data, and is input to the corresponding memory or controlled circuit.

Of these, pattern data and color data are stored in the display memory, read out according to a program, and processed to be added to the signal system circuit of the color receiver.

A microcomputer is used for the above-mentioned signal processing, and a microcomputer as shown in Fig. 1 is being considered. The input circuit 11 is a circuit that extracts digital data sent through a transmission medium and introduces it into this system. The digital data is sampled and decoded by a central processing unit (hereinafter referred to as CPU) 12. The CPU 2 includes a read-only memory (hereinafter referred to as ROM) 1 that contains fixed programs.
3. A random access memory (hereinafter referred to as RAM) 14 used as a work area is provided.

If the decoded data is pattern data, the CPU 2 controls the bus controller 16 to store the data in the pattern memory 18.

Further, if the decoded data is color data, the CPU 12 stores it in the color information memory 19 via the bus controller 17. The write addresses of the pattern memory 18 and color information memory 19 are designated by address designation data from the CPTJ 12 via the address bus AD1 address switch 15.The address designation data from the CPU 12 is the control data sent. It is generated by program data or a program written in advance in the ROM 13, and a skip address is specified so as to form a display pattern in the pattern memory 18 and color information memory 19.

The above writing process is performed during a non-display period of the display television receiver, for example, during a vertical blanking period. Therefore, the CPU 12 needs to know the timing, and for this purpose, a timing pulse PA is introduced from the timing pulse generator 26 to notify the non-display period. A timing pulse generator 26 receives screen position information from a horizontal counter 24 which is reset by the horizontal sync pulse of the television receiver and counts the clock, and a vertical counter 25 which is reset by the vertical sync pulse and counts the horizontal sync pulse. The above-mentioned timing pulse PA and various other timing pulses can be created using the above-mentioned timing pulse PA.

Next, the reading operation during the display period of the television receiver will be described. The read addresses of the pattern memory 18 and color information memory 19 are specified by adding address data generated by the horizontal counter 24 and vertical counter 25 via the address switch J5. The read data from the pattern memory 18 is converted into serial data by a parallel-to-serial converter 21 and sent to R-
The signal is input to the G-B matrix circuit 23. Data read from the color information memory 19 is input to the R.G.B matrix circuit 23 via the latch circuit 22.

By the way, in the above signal processing device, the pattern memory 1
8, a dot capacity of 32 bytes (-25) is allocated to one line (horizontal scanning line) of the display screen in the horizontal direction, and five bit output lines of the horizontal counter 24 are used. Also, in the vertical direction, 20
Assuming 4 lines, 8 bit output lines of the vertical counter 25 are required, and the total capacity corresponding to the screen is 2.
04x32 bytes. On the other hand, since color data is specified for each sub-block (8 dots x 12 lines), it is necessary to change the address of the color information memory 19 for each sub-block (8 dots x 12 lines). Since the color information memory 19 is designated by 8 pits in the horizontal direction, there is no need to convert the address in the horizontal direction, but it is necessary to convert the address every 12 lines in the vertical direction. Line converter 20 does this. That is, if the vertical address of the pattern memory 18 is L, the vertical address N of the color information memory 1g is N=INT(L/12).

During the display period, as described above, the address of the pattern memory 18 and color information memory 19 is specified. Since the pattern memory 18 is 1 byte (8 bits in parallel), is it converted to 1-bit serial data by the clock in the parallel-serial converter 2? &m will be done. On the other hand, the output data of the color 18 report memory 19 is held by the raster circuit 22 so as to match the timing with the pattern dots corresponding to the 1-byte can. fζ・GB matrix circuit 23
Now let's input '1. The pattern data and color data are transferred to the red, green, and blue outputs and output.

[Problems with background technology]

- According to the Shingetsu processing device described in F, pattern memory 18
Since the address line and the cheater line of the color information memory 19 cannot be shared, complicated wiring is required. Furthermore, during the display period, it is necessary to separate the microcombi 1-l data buses from the pattern memory data bus and color information memory data bus, and two data bus controllers 16 and 17 are required. Therefore, the control is naturally complicated, and the reliability is also poor in terms of probability.

[Purpose of the invention]

The present invention was made in order to cope with the above-mentioned circumstances, and an object of the present invention is to provide a display memory control device that can share the address bus and data bus of a pattern memory and color information memory, and has a simplified configuration. do.

[Summary of the invention]

To this invention=1. In other words, the first female line and the fifth data line of the first memory (first memory) and the second information memory (second memory) are shared. In this case, in order to prevent the addressing data of both memories from overlapping, and to prevent the read output data from overlapping,
4. Using the vertical counter 25, line converter 34, and address switch 35, addressing data is distributed in the first period and the second period, and both memories are specified in a time-sharing manner.

Then, the third period is the sum of the first period and the second period.
period) is set so that the differential serial converter 21 converts one period's worth of data into series.

〔Example〕

An embodiment of the present invention will be described below with reference to Eko. In FIG. 2, parts common to the circuit in FIG. 1 will be explained using the same reference numerals.

(2) When writing data to the pattern memory 18 and color information memory 19, the CPU 12 mainly specifies addresses and writes data to the pattern memory 18 and color information memory 19. Address designation data is provided by address bus AD and address switch 31 through 1.
i is added to the pattern memory 18 and color information memory 19, and the pattern data and color data are input to the pattern memory 18 and color information memory 19 via the bus controller 22.

(2) When data is read from the pattern memory J8 and the color information memory 19 during the display period, the process is as follows.

2a. Let's start with addressing. For addressing the pattern memory 18 and color information memory 19,
Horizontal counter 24, vertical counter 25, line converter 3
4. Address switch 35 and address switch 3 are used. The address switch 35 selects either the output of the vertical counter 25 or the output of the line converter 34, and inputs the output to the address switch 31. As the switching signal SW of the address switch 35, the 3 of the horizontal counter 24
The bit output of the row is used. This results in switching at twice the rate of the lowest horizontal address signal. The line converter 34 compensates for the difference in storage format between the pattern memory 18 and the color information memory 19, and corrects the count of the vertical counter 25, for example. In other words, the count number of 12 horizontal lines is set as 1. As a result, the output of the horizontal counter 24 and the output of the address switching circuit 35 are input to the address switching circuit 31, and address data in the horizontal and vertical directions are created. - The switching signal SW is also used as a chip selector signal for the pattern memory 18 and color 1 information memory 19.

2b. Next, the relationship with data reading of the pattern memory 18 and color information memory 19 will be explained. Third
The figure shows the storage format of the pattern memory 18 and color information memory 19.

One character data stored in the pattern memory 18 is
It is stored in pattern block 40. One character data is set to have, for example, 8 bits x 2 = 16 bits in the horizontal direction and 12 lines x 2 = 24 lines in the vertical direction, so the number of pits for this one character data is 16 x 24 = It becomes 384 bits. Also, in the color information memory 19, the pattern block 4
oO] Four small blocks corresponding to 1/4 block are designated as one color data block 43. This color data block 43 (shaded area) is 8 bits in the horizontal direction and 1 line in the vertical direction, and consists of 8×1-8 bits. Therefore, when the data of small block 4 of pattern block 4o is read out, the data of color data block 43 is correspondingly read out. Since small block 4 contains data for 12 lines, the data in color data block 43 will be read out 12 times.

In this way, the pattern memory 18 and the color information memory 19
Since the storage formats of the two are different, a line converter 34 is provided to compensate for this difference.

Now, when the output of the line converter 34 is selected by the address switch 35, the 8-bit data of the color data block 43 is transferred to the color information memory 19 by chip selection.
is read from.

Then, it is latched by the latch circuit 36 by the fourth clock pulse L. At this fourth clock, the switching signal SW changes, so this time the address switch 3
5 directly selects the output of the vertical counter 25, whereby the 8-bit data of the 4th small block (in the pattern memory) is read out. Then, at the fourth rotary pulse L2 of the next clock, this pattern data (8 bits) is loaded into the parallel-to-serial converter and converted into serial data using eight clocks. At the timing of the rotor pulse, the color data in the latch circuit 36 is transferred to the latch circuit 37, and the timing is matched with the putter data. From this point on, a DC conversion output is obtained from the parallel-serial converter 2.

FIGS. 4(a) to 4(h) explain the three waveforms of the operating signals, and FIG. 4(a) shows the display period non-display period obtained from the dimming pulse generator 33 using the hail pulse PA. be. The high level period of this timing pulse PA is the display period. FIG. 4(b) is a waveform showing how the lowest address of the pattern memory 3 changes. Figure 4 (C
) is a switching signal SW that is required to be applied to the address switching device 35. FIG. 4(d) shows how addressing data changes in the vertical address buses of the pattern memory 18 and color information memory 19, in which addressing data for pattern data and color data are output alternately. . The period TP is for pattern data, and the period TC is for color data. Figure 4(e) shows
This shows the status of data on the data bus 0UT-D.
Pattern data and color data are output alternately. The period TPO is pattern data, and the period TCO is color data. FIGS. 4(f) and 4(g) show the latch pulse L1 and the load pulse L, and FIG. 4(h) shows the period t required to serially convert 8-bit data.

〔effect〕

According to the display memory control device described above, the pattern data (8 bits) and the color data (1 block) can be read out in a time-sharing manner during the period in which 8 bits of butter data are displayed. can be output to a common data line without overlapping. Therefore, the pattern memory 18 and the color information memory 19 can use a common bus line. In addition, the address switch 35
, by providing a line converter 34 between the vertical counter 25 and the address switch 31, the pattern memory J8
The address bus can be shared with the color information memory 19 and the color information memory 19. As a result, the pattern memory 18 and the color information memory 19 can use the same address line and data line, which simplifies the redundancy of the memory part in particular (leading to n-axis characteristics).
8. It becomes easy to house the information memory 19 in the same chip, which contributes to production and operational reliability due to a reduction in the number of parts. Furthermore, when creating a large-scale integrated circuit for controlling a stiff memory, fewer wires around the memory can make it easier to manufacture and design. In this way, the present invention allows the pattern memory and the color information memory to co-use each other's address lines and share their data lines, thereby simplifying the wiring structure of the memory element, and making it possible to simplify the design and handling of the memory. A simple display memo I+ (7) A control device can be provided.

In particular, this system is effective in preventing the conventional system from having an extremely large number of input/output terminals when attempting to incorporate the display control portion other than the memory into an LSI.

In integrated circuits, the higher the number of bins, the higher the reliability (humidity resistance, discharge resistance)
However, if the present system is used to implement a part other than the memory into an LSI, the number of bins can be significantly reduced to n=, and reliability can be improved. here,
The reason why we considered an LSI without memory is that the memory used in this system needs to have the same number of bits as the number of picture elements that make up one screen, or more, and including this memory would reduce the size of the chip. This is because the chip Tf becomes too large.
ICs with a large j1 product tend to be stiff and have a lower yield rate, necessitating high-tech investment in sophisticated ICIIM manufacturing technology. Therefore, without making the chip surface as large as it is,
It is desired to produce good quality ICs and reduce the number of bins for the ICs, and this system satisfies this requirement.

[Brief explanation of the drawing]

Figure 1 shows the conventional concept 1. An explanatory diagram of the configuration of a display memory control device, 2Jl! FIG. 2 is a configuration explanatory diagram showing an embodiment of the present invention, and FIG. 3 is a block l diagram showing a storage format in the memory.
Figures 4(a) to 4(h) are time charts 1 shown to explain the operation timing fNFI of the device of this invention. 11...Input circuit, 12...CPU, 13...Read only memory, 14...Random access memory, 18...Pattern memory, 19...Color information memory, 2...Parallel C14 column converter, 24...Horizontal counter, 25...Vertical counter, 31.35...
Address switching circuit, 32... bus controller, 33
...Timing pulse generator, 34...Line converter, 35...At/Switcher, 36.37...Latch circuit.

Claims (1)

[Claims] The first . a second memory, and means for generating address data in synchronization with a synchronization pulse for deflection of the display screen, the address data of the first memory being generated during a first period, before or after the first period; circuit means for outputting read address data specifying an address of the second memory in a subsequent second period; and circuit means for serially converting the data of the first period read from the first memory. , at least the first. g (parallel-serial converter that requires a third period including 42 periods, and the output of the parallel-serial converter and the output of the latch circuit that latches the data read in the second period) 1. A control device for a display memory, comprising circuit means for adjusting timing.