JPS5923378A - Display memory controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a display memory control device, and for example, stores data sent in the form of digital signals in a memory to control a television receiver. It is used in signal processing systems that can be displayed on a display screen.

[Technical background of the invention]

Are television receivers becoming more versatile these days? Ideas: Systems that send display data using teletext systems and telephone lines have been developed.

These systems are configured so that digital data serving as a display source is superimposed on a transmission medium (radio waves, dedicated frequency signals), and this digital data is sampled by a television receiver. .The sampled data includes program data, pattern data,
Color data.

It is classified into various types such as control data, and is stored in the corresponding memory and controlled circuit (which is handled by two people. Of these, the display memory stores pattern data,
The color data is read out in accordance with the program (=) and processed to be added to the signal system circuit of the color receiver.

Incidentally, the pattern data transmission system is generally a dot pattern transmission method in which pattern data is broken down and transmitted. However, the single character multiplex broadcasting system has an index packet, and 70) pattern data of one index packet (
That is, data indicating program information being transmitted, etc.) is sent as code data. The television receiver is provided with a character generation read-only memory (hereinafter referred to as character generation) (referred to as OM).

Based on the above character code data, the character l (
Dot pattern data is read out from the OM generation circuit and processing for creating a dot pattern (character code mode) is performed.

A microcomputer is used for the above-mentioned signal processing, and a microcomputer as shown in FIG. 1 is being considered. Incidentally, FIG. 1 shows a display memory control device capable of handling both the dot pattern transmission method and the character code transmission method. First, the input circuit 11 extracts digital data sent via a transmission medium.

This is the circuit that connects this system. The digital data is sampled and decoded by a central processing unit (hereinafter referred to as CP II) 12.

The CPT 112 includes a read-only memory (hereinafter referred to as ROM) containing fixed programs13. Random access memory (hereinafter referred to as RA) used as a work area
14 (referred to as M) is attached and provided at ℃.

If the decoded data is dot pattern data, the CP TI J 2 transfers the data to the bus controller 15.
It is stored in the dot pattern memory 16 via the dot pattern memory 16. Also, CPTI7. ? If the decoded data is color data, the CPN 12 stores it in the color information memory 18 (2) via the bus controller 17.If the decoded data is character code data, the CPN 12 stores it in the character code memory 18 (2) via the bus controller 19. Memory to 20, a
let The write addresses to the dot pattern memory 16, color information memory IFIs character code memory 20 are CP117, ? Address bus AD,
Address switch 21? Specified by addressing data via ℃.

Addressing data from the CP TI 72 may be incoming control data, program data, or
OM7;? It is generated by the loaded program and specifies the ζ2 loading address to form the dot pattern memory 16, color information memory 18, character code memory 20+2 display pattern.

The writing process described in 1E is performed during a non-display period of the display television receiver, for example, during a vertical blanking period. Therefore, CP IT l,? It is necessary to know the timing, and for this purpose, a timing pulse PA is introduced from the timing pulse generator 22 to notify the non-display period. The timing pulse generator 22 is
a horizontal J-counter 23 that is reset by the horizontal periodic pulse of the television receiver and counts the display clock;
The above timing pulse PA and various other timing pulses can be generated using screen position information from the vertical counter 24 which is reset by the vertical synchronization pulse and counts horizontal synchronization pulses.

Next, we will explain the operation during reading between the display layers (j) of the television receiver. First, we will explain the reading operation between the display layers 16 and 18 of the television receiver. The read address of the information memory 18 is designated by adding address designation data generated by the horizontal counter 23 and vertical counter 24 via the address switch 2). Most of the read data is stored in the dot pattern memory 16.
is supplied to a parallel-to-serial converter 26 via a switch circuit 25, and is converted into a series by this parallel-to-serial converter 26 (2).

φ (*G=B is input to the matrix circuit 27.

The data read from the color information memory 18 is inputted to the "' C1, o, 13 matrix circuit 27 via the latch circuit 28.

By the way, in the above signal processing device, the memory capacity of the dot pattern memory 16 is 32 bytes for one line (horizontal set meal line) C2 of the display screen in the horizontal direction (=
The dot capacity of 2') is suppressed and the horizontal counter 2
Five of the three bit output lines are used. In addition, if we include 204 lines in the vertical direction, eight bit output images of the vertical counter 24 are required, and the total capacity corresponding to one screen is 204×32 bytes.

On the other hand, since the color data is specified for each sub-block (8 dots x 12 lines), the color information memory 18 is specified for each sub-block (8 dots x 12 lines).
It is necessary to change the address on a line-by-line basis. Since the color information memory 18 is designated by 8 bits in the horizontal direction, there is no need to convert in the horizontal direction, but in the vertical and white directions, it is necessary to change the address every 12 lines. The line converter 29 does this. In other words, if the vertical address of the dot pattern memory 16 is "■", then the vertical address of the color information memory 8 is N
is N-IN'l'' (L/12).

During the display period, the addresses of the dot pattern memory 16 and color information memory 18 are designated as described above. Since the dot pattern memory 16 is 1 byte (8 pits in parallel), it is converted by the parallel-to-serial converter 26 into 1-bit serial data according to the clock. On the other hand, the output data of the color information memory 18 is transmitted to the latch circuit 2.
8, each byte is held so as to match the timing with the corresponding pattern dot.

(The 0-B matrix circuit 27 converts the input dot pattern data and color data to red.

For green and blue, decode into power and output.

'Next, reading from the character code memory 2o will be explained. In this case, the data led to the parallel-serial converter 26 is transferred from the output data of the dot pattern memory 16 to the character generation ROM 3 by the switch circuit 25.
The output data is switched to 0. This switch circuit 2
The bit output of the third stage of IJI Wfi of 5 (* horizontal counter 230 as column Sw) is used. Character generation 1 < OM 30 to character data 711/
In order to read, character code data specifying a character and line address specification data are required.

In the case of a text character 1 For example, if the size of the - character is 8 dots in the horizontal direction and 12 lines in the vertical direction (-, then the readout addressing operation for this text character is the same as the readout addressing operation for color data. It is done like this.

As explained above (2), the display memory control device shown in FIG. 1 is capable of handling pattern data transmission using both the dot pattern transmission method and the character code transmission method.

[Problems with background technology]

However, in the case of the above configuration, the dot pattern memory 1
6. Color information memory 18, character code memory 2
0. Character generation RUM30 data line, address line) are required separately (2), which has the disadvantage of complicating the wiring.This leads to a decrease in reliability and (2. When considering large-scale integration of the 'aI section, a problem arises in that the number of input/output terminals of the integrated circuit increases.

Furthermore, during the display period, the data line on the CPI 112 side, the dot pattern memory 16, the color information memory 18, the character code memory 20% character generation R
It is necessary to disconnect from the OM J O data bus, and 3
bus controllers 15+17+19 are required,
Naturally, the control is complicated, and the reliability is also stochastic accordingly. [Effects of the Invention] This invention has been made to deal with the above circumstances.
Data lines of four memories, dot pattern memory, color information memory, character code memory, and character generation ROM, can be shared, and address lines of three memories except character generation l<OM can be shared, It is an object of the present invention to provide a display memory control device that can simplify the configuration.

[Summary of the invention]

In this invention, the dot pattern memory (first memory) and the color information memory (second memory) share their address lines and data lines. In this case, horizontal counter 23, vertical counter 24, line converter 33 . Using the address switch 34, address designation data is distributed in the first period and the second period, and both memories are time-divided and designated in degrees Celsius. Further, the address line and data line of the character code memory (third memory) are shared with the shared address line and data line of the dot pattern memory and color information memory, respectively. In this case, the code data of the character code memory is read out according to the address designation data output during the first period ≦2, and this code data is used as the address data in the character generation ROM (the The dot pattern data is read out from memory No. 4). Note that the length of the first period and the second period (the third period) is set so that the parallel-to-serial converter 26 converts one period's worth of data into series. .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, parts common to the circuit in FIG. 11 will be explained using the same reference numerals.

(2) First, the writing operations of the dot pattern memory 16, color information memory 18, and character code memory 2° will be explained.

When writing data to the dot pattern memory 16, color information memory 18, and character code memory 2o, the CPTJ 12 mainly specifies addresses and writes data to the dot pattern memory 16 and color information memory 18. Address designation data is applied to the dot pattern memory 16, color information memory 18, and character code method 920 via the address bus AD and the address switch 31, and the pattern data, color data, and character code data are applied to the bus controller 3.
2 to the dot pattern memory 16, color information memory 18, and character code memory 2o.

(2) When data is read from the dot pattern memory 16° and the color information memory 18 during the display period, the process is as follows.

[2a] Let's start with address specification. For addressing the dot pattern memory 16 and the color information memory 18, a horizontal counter 23, a vertical counter 24 . A line converter 33, an address switch 34, and an address switch 3 are used.

The address switch 34 selects either the output of the vertical counter 24 or the output of the line converter 33, and uses that output as the address! , /lI converter 31. The switching signal SW of the address switch 34 and °C are determined by the horizontal counter 230.
) The bit output of the third stage is used. This results in switching at twice the rate of the lowest horizontal address signal.

The line converter 33 compensates for the difference in storage format between the dot pattern memory 16 and the color information memory 18, and corrects, for example, the count number of the vertical counter 24. In other words, the count of 12 horizontal lines? There are 1 degrees as 1.

As a result, the output of the address switch 34, such as the output of the horizontal counter 23, is input to the address switch circuit 3, and horizontal and vertical addressing data are created. - 10,000, the switching signal SW is used for the dot pattern memory 16 and the color information memory 18.
/ Also used as a kuta signal.

[2b] Next, the relationship between data reading of the dot pattern memory 16 and the color information memory 18 (both will be explained separately. FIG. 3 is a diagram showing the storage format of the dot pattern memory 16 and the color information memory 18. One character data stored in the pattern memory 16 is stored in the pattern block 40 (Z). For example, one character data is set to consist of #J horizontal dot number 8 pits x 2-16 bits and vertical direction 12 lines x 2 = 24 lines, so the bits for this one character data. The number is 16×24=384 bits. In addition, in the color information memory 18, 4 small blocks corresponding to 1/4 block of the pattern block 40 are stored as 1°C.
The color data block 43 is designated as one color data block 43. This color data block 43 (hatched area) has 8 pixels in the horizontal direction.
The bits correspond to one line in the vertical direction, and consist of 8×1=8 bits. Therefore, small block 4 of pattern block 40
When data of 1 is read out, the data of color data block 43 is correspondingly read out.

Since the small block 41 includes data for 12 lines, the color data block 43σ) data is read out 12 times. Like this (two dot pattern memory 1
6 and color information memory 18, a line converter 33 is provided to compensate for this difference.

Now, when the output of the line converter 33 is selected by the address switch 34 (2), the 8-bit data of the color data block 43 is transferred to the color information memory 1 by chip selection.
8.

And the 4th display clock is Ratsuchinoku Runu L.

is latched by the latch circuit 35. At this fourth clock, the off signal SW changes, so the address switch 35 directly selects the output of the vertical counter 24, and thereby the 8-bit data of the small block 4 (in the pattern memory) is changed. Read out. Then, at the fourth load pulse L of the next display clock, this pattern data (8
bits) are loaded in parallel-to-serial converter C2 and converted into series with eight clocks. At the timing of rotonosis L2, the color data of the previous latch circuit 35 is transferred to the latch circuit 36 (2), and the timing is matched with the pattern data.From this time, the parallel-serial converter 2
) gives the DC conversion output.

Figures 4(a) to (hl explain the timing pulse generator 3).
The display period and non-display period obtained from 7 are the hail T pulses PA. The high level period of this timing pulse PA is the display period. FIG. 4 (bl is a waveform showing the change status of the lowest address of the dot pattern memory 16. FIG. 4 (C1 is the switching signal SW applied to the address switch 34+2. FIG. 4(d) 1 shows the state of change in addressing data in the vertical addressing of the dot pattern memory 16 and the color information memory 18. Addressing data for pattern data and cutout data are alternately output C2.Period 1゛P is for pattern data 1 period TC is for color data. $4 [J (el is data bus OIJ 'I'
- What is the status of the data in D? In this example, dot pattern data and color data are output alternately. Period '1'
PO is dot pattern data, and period 1 CO is color data. Figures 4(f) and (g) show latch pulse L and load pulse 2? The same figure (hl
Is it 8 bit data? It shows the period type that requires 1 time for serial conversion.

Next, display reading in character code mode will be explained. In order to read out a desired character dot pattern, for example, from the character generation RoM 30, character specification data that specifies the character and T line address specification data that indicates the line number are required. ing. FIG. 5 is a diagram showing the timing of the contents of address specification. During the period T in which color data is read from the character code color information memory 18, character code data is read out from the character code memory 2o. This character code data is stored in the latch circuit 35.
latched to. In this way, character code data is first latched by the latch circuit 351. The output character code data of the latch circuit 35 is supplied to the address switching circuit #3].

This time, character generation h! OM, 190 is used as addressing data. Like this 42C.

Character generation RO%I 30 outputs the desired character's tone pattern data. This dot pattern data is loaded into the parallel-serial conversion circuit 261, and n-G, B
The signal is supplied to the matrix circuit 27.

FIG. 5 (al to <g) illustrates the waveform of the operating signal, and FIG. 5(a) shows the displayed chlorella counted by the horizontal kakunta 23. Figure 5 (bl is horizontal force counter 2
This is the output of the third stage bit of No. 3, that is, the switching signal SW.

FIG. 5(C) shows an 8-bit display period. Figure 5 fdl
indicates the addressing operation in dot pattern mode,
A period TC indicates an addressing period of the color information memory 18, and a period TP indicates an addressing period of the dot pattern memory 16. FIG. 5 (el indicates the addressing operation in the character code mode, period T
l" l(indicates the addressing period of character generation HOλI30. FIG.
The period TKO indicates the output data period of the character code memory 20, and the period TKO indicates the data change situation in D.
PO indicates the output data period of character generation ROM~30. Fifth factor (gl is the output data of the latch circuit 35.

In other words, T indicates character code data.

As detailed above, the circuit of this embodiment is capable of displaying dot pattern data (8 bits) and color data (1 block) during the pattern mode (2) during the period in which 8 bits of dot pattern data are displayed. Since the configuration is such that the data can be read out in a time-divided manner, each data output can be output to a common data line without overlapping.Therefore, the data lines of the dot pattern memory 16 and the color information memory 18 can be output to a common data line. I can do it.

In addition, in the character code mode, the dot pattern data and color data are read out in a time-divided manner, and the character generation 1 (8 bits of original dot pattern data from OM 30) is displayed during the period of time. , the character code data and the desired dot pattern data can be read out in a time-sharing manner.Therefore, the data lines of the character code memory 20 and character generation ROM 30 can be read out in common.From the above points, the dot pattern Memory 16, color information memory 18.
Character code memory 20, character generation ROM 3
0 data line? It is clear that we can do something in common.

Further, by providing an address switch 34 and a line converter 35 between the vertical force sensor 24 and the address switch 31, the address lines of the dot pattern memory 18, color information memory 18, and character code memory 20 are shared. be able to.

In this way, according to the circuit of this embodiment, the data lines of the dot pattern memory 16, the color information memory 18, the character code memory 20, and the character generation RO
Address lines of three memories excluding M30f? It can be made common, which simplifies the wiring in the memory part and improves reliability. Also, the dot pattern memory 18. Color information memory 19. It is also easy to house the character code memory 20 and the character generation RUM 30 in the same chip, which contributes to production and operational reliability due to a reduction in the number of parts. Furthermore, when creating a large-scale integrated circuit to control these memories, the fewer wiring lines around the memory can facilitate production and design. In this way, the present invention shares the data lines of the dot pattern memory 16 and the color information meract generation ROM 30, and also allows the character generation RIJM 30 to share the data lines.
'l Except 3 memory address lines? share it,
A display memory control device that can simplify the wiring structure of memory elements and simplify memory design and handling. Can be provided. Also, is there a bus controller for sharing data lines? One thing I can do is T.

In particular, when it comes to systems, when trying to integrate the display control part other than memory into LSI, it is effective in preventing the number of input/output terminals from becoming too large in conventional systems. It is.

In integrated circuits, the higher the number of bins, the more reliable it is (moisture resistance).

However, if this system is used to convert the part excluding the memory into ILSI, the number of bins can be significantly reduced (2) and the reliability can be improved.Here, LS I excluding memory?I thought that the memory used in this system needs to have the same number of bits as the number of picture elements that make up one screen, or more, and if this memory is included, the chip area will increase. This is because the chip area becomes too large and T is too large.If the chip area is large, the product rate will decrease accordingly and a commercial investment will have to be made in IC manufacturing technology.Therefore, if the chip area is increased It is desirable to make a 4', high-quality IC (1/2 and reduce the number of pins of the IC, but this system is indispensable).

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the configuration of the 1111 device 1 of the conventionally considered table top, and Fig. 3 is an explanatory diagram of the configuration of the 1111 unit 11 of this defense. i, block diagram showing @form, Section 4 1(a) to thl, and Fig. 5 (al to (gl) are time charts shown to explain the dynamic f″F timing of this invention device. 11...Input circuit, 12...CPII, 73...
Read-only memory, 14... Random access memory, 16... Dot pattern memory, 18... Color information memory, 20... Character code memory,
23...Horizontal counter, 24...Vertical counter, 3
0...Character generation J<OM, 26.l.Parallel-serial conversion circuit, 27..R, G, B matrix circuit, 31.34..Address switching circuit, 32..Bus controller, 33..・Line converter, 35.36...
- Latch circuit, 37...timing pulse generator. Applicant's representative Patent attorney Takehiko Suzue Figure 3 Figure 4 (b) (d) TCTP TCTP TCTP TCTP2=Ego=mouth (e)==YunYunH已YunYun2==Work (h) Figure 5 x0

Claims (1)

[Claims] In order to display a pattern on both sides of the display, mutually related data between the pattern data sent in a state where the pattern is separated into picture elements and the color data of the pattern? The first . With the second memory. In order to display the pattern on the display screen, the character code data sent after converting the pattern into a code is stored, and the address line and the data line are connected to the first. A third memory shared with the second address line and the data line stores dot pattern data corresponding to the character code data written in wI, and the data line is connected to the first address line and the data line. Second.
a fourth memory shared with the data line of the third memory; and means for generating address data in synchronization with a synchronizing pulse for deflection of the display screen, the first period being in the dot pattern mode. outputs read address designation data that designates the address of the first memory or the second memory, and outputs read address designation data that designates the address of the second memory or the first memory in a second period after the first period, and outputs a character. In the code mode, circuit means outputs addressing data specifying the address of the third memory during the first I'91 period; latch means latches read data during the first period (2); , during the first period in character code mode (- means for specifying the address of the fourth memory in the second period using the latched character code data of the third memory as address specification data; and the data read out from the first memory or the fourth memory?At least the first
．． a parallel-to-serial converter that stores a third period including a second period; 1. A control device for a display memory, comprising circuit means for synchronizing timing with data read from the second memory.