JPS61203786A - Signal receiving device - Google Patents

Signal receiving device

Info

Publication number
JPS61203786A
JPS61203786A JP60045142A JP4514285A JPS61203786A JP S61203786 A JPS61203786 A JP S61203786A JP 60045142 A JP60045142 A JP 60045142A JP 4514285 A JP4514285 A JP 4514285A JP S61203786 A JPS61203786 A JP S61203786A
Authority
JP
Japan
Prior art keywords
phase
signals
clock signals
circuits
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60045142A
Other languages
Japanese (ja)
Inventor
Hiroshi Sakai
博 酒井
Hideo Matsumoto
秀夫 松本
Hiroshi Sukunami
宿南 博史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60045142A priority Critical patent/JPS61203786A/en
Publication of JPS61203786A publication Critical patent/JPS61203786A/en
Pending legal-status Critical Current

Links

Landscapes

  • Facsimile Transmission Control (AREA)
  • Facsimile Image Signal Circuits (AREA)

Abstract

PURPOSE:To remove the effect of phase distortion of the transmission channel and to enable data to be received surely by making the phase of the input data and that of the clock signals coincident with each other by adjusting the phase of the clock signals and holding the input data by a latch circuit by clocks. CONSTITUTION:The R, G, B chrominance signals constituting the picture data are inputted to the latch circuits 11-13 while clock signals CLK are introduced to a clock generating circuit 14. Clock signals are generated in correspondence to the input CLK from the circuit 14 and supplied respectively to phase adjustment circuits 15, 16, 17. The circuits 15, 16, 17 are provided with switches 18, 19, 20 setting the phase amount of the clock signals. These switches set the phase amount suited to the phase of the signals R.G and B with respect to the input clock signals so that the clock signals CLKR, CLKG and CLKB are supplied respectively to the circuits 11, 12 and 13. Hence, the signals R, G and B and CLKR, CLKG and CLKB are coincident in phase with one another so that the R. G and B signals are received surely.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、例えはカラープリンタ装置等に適用される
信号受信装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a signal receiving device applied to, for example, a color printer device.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

周知のように、例えばカラープリンタ装置にはパーソナ
ルコンピュータ等の外部機器よりRlG、B(赤、緑、
青)信号からなるカラー画像データおよびこの1Ili
l像データに同期したクロック信号が供給され、このク
ロック信号に応じて各画像データを受信するようになっ
ている。
As is well known, for example, a color printer device receives RlG, B (red, green,
Color image data consisting of blue) signals and this 1Ili
A clock signal synchronized with the image data is supplied, and each image data is received in accordance with this clock signal.

牙5図は従来の信号受信装置を示すものである。ラッチ
回路51,52.53には図示せぬ外部機器よりカラー
画像データを構成するRlG、B信号がそれぞれ供給さ
れるとともに、クロック信号CLKが供給され、このク
ロック信号CLKによって各几、G、B信号が受信され
るようになっている。また、このクロック信号CLKは
例えばR信号を基準として位相が調整されている。
Figure 5 shows a conventional signal receiving device. The latch circuits 51, 52, and 53 are supplied with RlG and B signals constituting color image data from an external device (not shown), as well as a clock signal CLK. The signal is now being received. Further, the phase of this clock signal CLK is adjusted using, for example, the R signal as a reference.

ところで、このような信号受信回路に牙6図に示す如く
、クロックイ1号CLKと位相がすれたR、G、B信号
が供給された場合、R,G信号はラッチ回路51.52
によって受信できるものの、B信号はラッチ回路53に
より受信することができない。
By the way, when such a signal receiving circuit is supplied with R, G, and B signals that are out of phase with the clock No. 1 CLK as shown in Fig. 6, the R and G signals are sent to the latch circuits 51 and 52.
However, the B signal cannot be received by the latch circuit 53.

このように、従来の信号受信回路では外部機器や伝送路
等によってR,、G、B信号およびクロック信号の位相
がすれると、確実にカラー画像データを受信することが
できなくなる不都合を有していた。
As described above, conventional signal receiving circuits have the disadvantage of not being able to reliably receive color image data if the phases of the R, G, B signals and clock signals are shifted due to external equipment, transmission lines, etc. was.

〔発明の目的〕[Purpose of the invention]

この発明は上記事情に基づいてなされたものであり、そ
の目的とするところは、外部機器あるいは伝送路におけ
る位相歪の影響を除去して確実にデータを受信すること
が可能な信号受信装置を提供しようとするものである。
The present invention has been made based on the above circumstances, and its purpose is to provide a signal receiving device that can reliably receive data by removing the influence of phase distortion in external equipment or transmission paths. This is what I am trying to do.

〔発明の概要J この発明は例えはJG、B信号、クロック信号の位相を
それぞれ個々に]JIE’l能としたものである。
[Summary of the Invention J] This invention allows the phases of the JG, B signals, and clock signals to be controlled individually by JIE'l.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例について図面を診照して説明
する。
An embodiment of the present invention will be described below with reference to the drawings.

矛1図において、ラッチ回路11,12゜13にはそれ
ぞれ図示せぬ外部機器より、カラー画像データを構成す
る几、G、B信号がそれぞれ供給され、クロック発生回
路14にはクロック信号CLKが供給される。このクロ
ック発生回路14では入力されたクロック信号CLKに
対応したクロック信号が発生され、このクロック信号は
それぞれ例えばゲート回路やディジタル遅延素子からな
る位相調整回路75 、16゜17に供給される。これ
ら位相=aSt回路15゜16.17には入力されたク
ロック信号の位相量を設定するスイッチ18,19.2
0がそれぞれ設けられており、これらスイッチIll。
In Figure 1, latch circuits 11, 12, and 13 are supplied with L, G, and B signals constituting color image data from external devices (not shown), respectively, and a clock signal CLK is supplied to a clock generation circuit 14. be done. This clock generation circuit 14 generates a clock signal corresponding to the input clock signal CLK, and these clock signals are supplied to phase adjustment circuits 75 and 16, 17 each comprising, for example, a gate circuit or a digital delay element. These phase=aSt circuits 15, 16, and 17 have switches 18, 19, and 2 that set the phase amount of the input clock signal.
0 are provided respectively, and these switches Ill.

19.20によって入力されたクロック信号に対して前
記几、G、B信号の位相に合った位相量が設定される。
19. In step 20, a phase amount matching the phase of the above-mentioned 几, G, and B signals is set for the input clock signal.

このようにして各位相調整回路15,16.17より出
力されるR、G、B信号の位相に合ったクロック信号C
LKR,CLKo。
In this way, the clock signal C matches the phase of the R, G, and B signals output from each phase adjustment circuit 15, 16, and 17.
LKR, CLKo.

CLKBはそれぞれラッチ回路11,12.13に供給
される。したがって、矛2図に示すような位相のR,G
、B信号であってもクロック信号CLKR,CLK、 
、 CLKBがそれぞれR,G、B信号と位相が一致さ
れているため、R,、C)、B信号を確実に受信するこ
とかでさるものである。
CLKB is supplied to latch circuits 11, 12, and 13, respectively. Therefore, R, G of the phase as shown in Figure 2
, even if the B signal is the clock signal CLKR, CLK,
, CLKB are matched in phase with the R, G, and B signals, respectively, so it is important to reliably receive the R, , C), and B signals.

次に、この発明の他の実施例について説明する。尚、前
記実施例と同一部分には同一符号を何丁0 .1−3図は谷ラッチ回路II、12.13に供給され
るクロック信号CLKの位相を同一とし、入力される凡
、G、B信号の位札ケ位相調整回路31,32,33、
スイッチ34,35゜36によってクロック信号の位相
に合わせるようにしたものである。このような構成とし
ても前記実施例と同様の効果を得ることが可能であるO また、牙4図はクロック信号CLKとR、G。
Next, other embodiments of the invention will be described. The same parts as in the above embodiment are designated by the same reference numerals. In Figure 1-3, the phases of the clock signals CLK supplied to the valley latch circuits II and 12.13 are the same, and the phase adjustment circuits 31, 32, 33,
Switches 34, 35.degree. 36 are used to match the phase of the clock signal. Even with such a configuration, it is possible to obtain the same effects as in the embodiment described above.Furthermore, FIG. 4 shows clock signals CLK, R, and G.

B信号の両方をそれぞれ位相調整回路15゜16.17
,31.32.33およびスイッチ18.19,20,
34,35.36によって調整することにより、それら
の位相を一致させるようにしたものであり、図中41は
同一構成である。このような検収とすることにより一層
確実にカラー画像データを受信することがOJ−能であ
る。
Phase adjustment circuit for both B signals 15°16.17
, 31.32.33 and switches 18.19, 20,
34, 35, and 36 to match their phases, and 41 in the figure has the same configuration. By conducting such an acceptance inspection, it is possible to receive color image data more reliably.

その他、この発明の安旨を変えない範囲で櫨擁変形実施
可能なことは勿論である。
It goes without saying that other modifications can be made without changing the spirit of the invention.

〔発明の効果〕〔Effect of the invention〕

以上、詳述したようにこの発明によれは、外部機器ある
いは伝送路における位相歪のT:/書を除去して確実に
データを受信することが可能な信号受信装置を提供でき
る。
As described in detail above, according to the present invention, it is possible to provide a signal receiving apparatus capable of reliably receiving data by removing phase distortion T:/ in an external device or a transmission path.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明に係わる信号受信装置の一実施例を示
す構成図、第2図は第1図の動作を説明するために示す
図、牙3図、牙4図はそれぞれこの発明の他の実施例を
示す構成図、矛5図は従来の信号受信装置を示す構成図
、矛6図は矛5図の動作を説明するために示す図である
。 11.12.13・・・ラッチ回路、15,16゜17
.31,32.33・・・位相調整回路、1g。 19.20,34,35.36・・・スイッチ。 出願人代理人 弁理士  鈴 江 武 彦図面の浄vJ
(内容に変更なし) 第1図 第2図 第3図 第4図 第5図     第6図 6゜1.69.4・h了 1゜ ”’fii苛長官 志賀 学 殿 1 ”11件の表示 特願昭60−45142 号 2、!!明の名称 信号受信装置 3、補iEをする名 重性との関係 特許出願人 億株式会社 東 芝 4、代1g人 住所 2g宸部港区虎/閂!’Jロ26番5号 第17
虞ピル5、自発補正
FIG. 1 is a configuration diagram showing an embodiment of a signal receiving device according to the present invention, FIG. 2 is a diagram shown to explain the operation of FIG. 1, and FIG. 3 and FIG. Fig. 5 is a block diagram showing a conventional signal receiving device, and Fig. 6 is a diagram shown to explain the operation of Fig. 5. 11.12.13...Latch circuit, 15,16°17
.. 31, 32. 33... Phase adjustment circuit, 1g. 19.20,34,35.36...Switch. Applicant's agent Patent attorney Suzue Takehiko Purification of drawings vJ
(No change in content) Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6 Patent Application No. 1986-45142 No. 2! ! Ming's name signal receiving device 3, relationship with the name weight of supplementary iE Patent applicant Billion Co., Ltd. Toshiba 4, representative 1g person address 2g Shinbe Minato-ku Tora/Bar! 'Jro 26 No. 5 No. 17
Yu pill 5, spontaneous correction

Claims (2)

【特許請求の範囲】[Claims] (1)入力されたデータをクロック信号によって保持す
る保持手段と、少なくとも前記データあるいはクロック
信号の一方の位相を調整しデータおよびクロック信号の
位相を一致させる調整手段とを具備したことを特徴とす
る信号受信装置。
(1) It is characterized by comprising a holding means for holding input data using a clock signal, and an adjusting means for adjusting the phase of at least one of the data or the clock signal to match the phases of the data and the clock signal. Signal receiving device.
(2)前記データはカラー画像データを構成するR、G
、B信号からなることを特徴とする特許請求の範囲第1
項記載の信号受信装置。
(2) The data is R, G, which constitutes color image data.
, B signal.
Signal receiving device as described in section.
JP60045142A 1985-03-07 1985-03-07 Signal receiving device Pending JPS61203786A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60045142A JPS61203786A (en) 1985-03-07 1985-03-07 Signal receiving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60045142A JPS61203786A (en) 1985-03-07 1985-03-07 Signal receiving device

Publications (1)

Publication Number Publication Date
JPS61203786A true JPS61203786A (en) 1986-09-09

Family

ID=12711027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60045142A Pending JPS61203786A (en) 1985-03-07 1985-03-07 Signal receiving device

Country Status (1)

Country Link
JP (1) JPS61203786A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7145579B2 (en) 2002-01-07 2006-12-05 Nec-Mitsubishi Electric Visual Systems Corporation Display apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7145579B2 (en) 2002-01-07 2006-12-05 Nec-Mitsubishi Electric Visual Systems Corporation Display apparatus

Similar Documents

Publication Publication Date Title
EP0249985B1 (en) Video memory
JP2000354029A (en) Synchronous clock for generating circuit
US8306128B2 (en) Clocked output of multiple data streams from a common data port
JP2000357963A (en) Delay locked loop circuit
JPS5844883A (en) Method and device for adjusting digital color signal
JPS59207792A (en) Hue altering device of television signal processor
KR900017400A (en) Color image signal processing method and apparatus therefor
JPS61203786A (en) Signal receiving device
KR100231673B1 (en) High speed bit-serial systems
EP0201128A1 (en) Integrated electronic multiplex circuit and integrated electronic circuit including such a multiplex circuit
KR930001467B1 (en) Apparatus for dvp
JP2833244B2 (en) Image adjustment device
JPS61161875A (en) Miller effect generating system
JPS58121847A (en) Synchronizing signal reproducing system
GB2030740A (en) Apparatus and Method for Processing Television Picture Signals and Other information
JPS6252501B2 (en)
JPH0267667A (en) Circuit board
JPH04278613A (en) Clock device of duplex constitution
JPH049339B2 (en)
JP2974390B2 (en) Frame signal reproduction circuit
JPH04245784A (en) Image mixing/amplifying device
JPH03202917A (en) Picture signal synchronizing circuit for printer
JPS6118988A (en) Display synchronization circuit
JPH10242808A (en) Semiconductor integrated circuit device
JPS63146668A (en) Picture quality adjusting device