JPS61203720A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To attain D/A conversion even when a supplied digital signal exceeds the number of digits of input to a D/A converter by shifting the digital signal in response to the exceeded number of digits. CONSTITUTION:A control circuit 11 generates a signal E representing the exceeded number of digits when the number of digits of an input code data is larger than the reference number of digits by the prescribed number of digits. A shift circuit receiving the said signal E shifts the position of a decimal point of the input code data by the number of exceeded digits toward high-order in response to the signal E. After the output of the shift circuit is converted by a D/A converter 1, the result is fed to an LPF 12 via a switching circuit 2 controlled by the signal E. Even when the supplied digital signal exceeds the input number of digits of the D/A converter, D/A conversion is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a digital-to-analog conversion circuit, and in particular to a digital-to-analog conversion circuit that converts code data such as binary code data displayed in fixed-point format into an analog signal while suppressing glitch noise. Regarding the A conversion circuit.

A conventional circuit of this type is shown in FIG. 1
2 is a digital-to-analog (D/A) converter that converts a predetermined digital signal into an analog signal, and 2 is a control terminal 3.
This is a switching circuit that allows the output signal of the D/A converter 1 to pass intermittently according to the pulse width of the control pulse signal supplied via the control pulse signal.

The switching circuit 2 is comprised of many analog switches and the like that operate in response to control pulse signals.

The output of the switching circuit 2 is outputted through a Ronos filter 4.

Next, the operation will be explained with reference to the waveform diagram in FIG.

The D/A converter 1 outputs an analog signal as shown in Figure (B) in response to a digital signal as shown in Figure (A). Here, theft 4. A response period α is required from when the input signal (A) of the converter 10 changes until the output signal (B) becomes stable, and during this period α, large currents and peaks called glitches may occur. be. The period α of this output signal (B)
In order to eliminate the adverse effects of instability and glitches in the control signal J?, which is supplied via the control terminal 3, The pulse signal (C) generates an output signal (B) according to its pulse width.
) switching circuit 2 for a certain period of time t within the stable period of
Activate (turn on). Accordingly, the analog output signal (D) of the switching circuit 2 is the control signal (C
) becomes a pulse amplitude modulated wave of the base pulse width. The analog output signal (D) is low! is supplied to the filter 4. The locus filter 4 is formed by, for example, an integrating circuit, and obtains an analog signal from the pulse amplitude modulated wave.

Conventional circuits configured in this manner are limited to use only for digital signals having a predetermined number of bits or less; It cannot be converted.

Therefore, an object of the present invention is to make it possible to convert a digital signal into an analog signal even when a digital signal having a predetermined number of input bits or more is supplied to a D/A converter having a predetermined number of input bits. It is an object of the present invention to provide a D/A conversion circuit that has the following characteristics.

In order to achieve the above object, the D/A converter circuit of the present invention supplies a predetermined number of bits from the upper bits of the supplied digital signal data to the D/A converter, and A configuration is adopted in which the closing period of a switching circuit provided after the D/A converter is changed by a signal corresponding to the number of input digits.

An embodiment of the present invention will be described below with reference to FIG. In the figure, parts equivalent to the conventional circuit are indicated by the same symbols. A predetermined bit (for example, a binary code) from an external source (
The digital signal of the L pit (hereinafter referred to as L pit) is supplied to the shift circuit 10. Furthermore, a digital signal of a predetermined number of bits (hereinafter referred to as M bits) from the higher digits of the L-bit digital signal is supplied to the control circuit 11 . The control circuit 11 includes a logic circuit that selectively selects a predetermined time constant depending on the sign of an M-bit digital signal, and a monostable multi-channel circuit that sets a time constant corresponding to the pulse width by the output of the logic circuit. It consists of a vibrator. Further, the monostable multivibrator generates the above-mentioned pulse in synchronization with clock timing information included in the supplied digital signal or data. The output of the multivibrator and the output of the logic circuit are used as a control pulse signal (E) and a shift signal. The control/arm pulse signal (E) and shift signal are each sent to the switching circuit 2.
and each control terminal of the shift circuit 10. As shown in FIG. 4, the control pulse signal (E) has a Norus width that changes depending on the sign of the digital signal of the M pit.

The shift circuit 10 is formed by a shift register, a ring register, a multi-branch register, or the like, and temporarily stores the supplied digital signal, and shifts the digital signal by a predetermined number of digits in accordance with the shift signal, starting from the higher order (L-M ) bit digital signal is supplied to the D/A converter 1.

A converter 1 converts a (LM) bit digital signal into an analog signal and supplies it to one input terminal of a switching circuit 2. The other input terminal of switching circuit 2 is grounded. The switching circuit 2 intermittently passes the analog signal in response to the high level period of the control pulse signal (E). switching circuit 2
The output becomes a PAM and PWB II mother pulse signal. For example, the arm filter 12 integrates the output of the switching circuit 2 in synchronization with the supply of the control signal (E), and combines this integral value with the control signal (J?). The structure is such that an average value is obtained from the pulse signal generation period to generate an analog signal, which is output via a filter that removes harmonics.

Furthermore, the operation of the above circuit will be explained. For example, after converting an analog signal into a binary code digital signal using an 8-bit ~0 converter, -18 bits of each data are added to obtain 9-bit data, which is input to the circuit of the present invention. do.

If an 8-bit D/A converter is used in the D/A conversion circuit 1, (LM)=8, I,=9, and M=1.

The upper M (=1) pits of the input dinotal data are supplied to the control circuit 11, and the L pits including the M pits are supplied to the shift circuit 10. The control circuit 11 outputs the upper 2 bits of the 9-bit data when the value of the M-bit data is 0, and the upper 8 bits of the 9 bits when the value of the data is 1. A shift signal is supplied to the shift circuit IO for selection. The shift circuit 10 supplies 8-bit data to the Osaka alpha converter 1 in response to the shift signal. The analog signal output of the D/A converter 1 is supplied to a switching circuit 2. When the data supplied to the D/A converter 1 is the lower 8 bits, that is, when the data supplied to the control circuit 111C is O,
The control circuit 11 sets the dip rich pulse width of the control/4' pulse signal (E) to the reference pulse width τ.

Further, when the data supplied to the D/A converter 1 is the upper 8 bits, that is, when the data supplied to the control circuit 11 is 1, the control circuit 11 outputs the control signal (E
)'s arm lux width is set to 2×τ. Since the output of the switch circuit 2 is integrated as described above by the low bus filter 12, the pulse width of the control pulse signal (E) is 2×τ.
Low/J? The output level of the pulse filter 12 is twice that when the signal/base pulse width is τ. In this way, when the data reaches 9 bits, the shift circuit 10 shifts the data by 1 pit and uses that value, and doubles the passage time of the switch circuit 2. The result is an analog signal proportional to the original data value.

Furthermore, in the (LM) pit D/A converter,
When the upper pit that is 1 exists at the Nth bit from the lower end of the data consisting of L pits, the shift circuit 10 selects (LM) pits from the Nth bit, and 2(N-(L) -M) ) The control circuit 11 may be operated to close the switch circuit 2 during the period corresponding to xτ.

Note that the shift signal and control pulse signal (E) are signals generated based on the sign of M bits, and it is possible to replace them with a single signal.

Furthermore, it is also possible to configure the control circuit 11 using a microprocessor. In short, any configuration that can provide the required control signal or effect is sufficient.

As explained above, in the D/A conversion circuit of the present invention, when the number of digits of the supplied digital signal exceeds the number of input digits of the D/A converter, the digital signal is converted according to the number of digits exceeding the number of digits. This is D/A converted, and the resulting analog signal is integrated for a period corresponding to the number of excess digits, so the number of digits of the supplied digital signal is D/A.
This is preferable because D/A conversion is possible even if the number of input digits exceeds the number of input digits of the /A converter.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional D/A conversion circuit, FIG. 2 is a waveform diagram showing main signal waveforms of the conventional D/A conversion circuit, and FIG. 3 is a D/A conversion circuit according to the present invention. A block diagram showing an embodiment of the conversion circuit, FIG. 4 shows the control/4' pulse signal (E)
FIG. Explanation of symbols of main parts

Claims (1)

[Claims] a control circuit that generates an excess number signal indicating the excess number of digits when the number of digits of the input code data is larger than the reference number of digits by a predetermined number of digits; and a decimal point of the input code data corresponding to the excess number of digits in accordance with the excess number of digits signal. A decimal point shift circuit that shifts the position of
A D/A converter for A conversion, and the output of the D/A converter is synchronized with the clock timing of the input code data and is passed for a length corresponding to the excess number of digits according to the excess number of digits signal. A D/A characterized in that it includes a gate circuit that
conversion circuit.