JPS6120367A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the micro fabrication of elements by a method wherein the first and second semiconductor regions of the second conductivity type away from each other at a required distance are formed at the part of a semiconductor layer of the first conductivity type which corresponds to an aperture of the insulation layer. CONSTITUTION:A semiconductor region 2 (n<+> type buried layer) of the first conductivity type is formed in a semiconductor substrate 1 (p type Si substrate). An insulation layer 4 (SiO2 film) provided with apertures by corresponding to the semiconductor regions 2 is formed on the semiconductor substrate. A semiconductor layer 13 (n type Si layer) of the first conductivity type is formed on the semiconductor substrate exposed in an aperture and on the insulation layer. The first and second semiconductor regions 11 and 12 of the second conductivity type away from each other at a required distance (a p<+> type emitter region and a p<+> type collector region which are located at a distance of the width of the base region) are formed at the part corresponding to the aperture. The micro fabrication of elements is enabled, and the semiconductor device substantially parallel to the surface of the semiconductor substrate in the operating direction can be produced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device,
It is optimal for use in manufacturing lateral pnp type bipolar transistors as elements constituting high-density LSIs.

BACKGROUND ART AND PROBLEMS The present inventors proposed in Japanese Patent Application No. 58-92697 a method for manufacturing an npn type bipolar transistor that can reduce the widths of the emitter region and base region to submicron levels. Incidentally, in linear ICs and the like, in addition to npn-type bipolar transistors, pnp-type bipolar transistors are often required to construct a desired circuit. In this case, from the viewpoint of simplifying the IC manufacturing process, it is desirable to be able to simultaneously form an npn-type bipolar transistor and a pnp-type bipolar transistor on the same substrate by the same manufacturing process. However, the above patent application Sho 5L-92
In the manufacturing method proposed in No. 697, it was not possible to simultaneously form an npn-type bipolar transistor and a pnp-type bipolar transistor on the same substrate through the same manufacturing process.

OBJECTS OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a method for manufacturing a semiconductor device that corrects the above-described drawbacks of conventional methods for manufacturing a semiconductor device.

Summary of the Invention A method for manufacturing a semiconductor device according to the present invention includes forming a semiconductor region of a first NK type on a semiconductor substrate (for example, a p-type silicon substrate).
a step of forming an insulating layer (for example, a 5i02 film) having an opening corresponding to the semiconductor region of the first conductivity type on the semiconductor substrate; , forming a semiconductor layer of a first conductivity type (for example, an n-type silicon layer) on the semiconductor substrate and the insulating layer exposed in the opening of the insulating layer; and the semiconductor layer of the first conductivity type. A first layer of a second conductivity type that is in a predetermined path mutually in a portion of the layer corresponding to the opening of the insulating layer.
and a step of forming a second semiconductor region (for example, a p3 type emitter region and a p' type collector region formed apart by the width of the base region).

By doing this, it is possible to miniaturize the elements, and also to manufacture a semiconductor device whose operating direction is substantially parallel to the surface of the semiconductor substrate. It is possible to simultaneously form elements with different conductivity types.

EXAMPLE Hereinafter, an example in which a method for manufacturing a semiconductor device according to the present invention is applied to manufacturing a semiconductor device in which an npn type bipolar transistor and a lateral pnp type bipolar transistor are provided on the same substrate will be described with reference to the drawings.

First, as shown in FIG. 1A, an n-type buried layer 2 and a p-type channel stopper 3 are sequentially formed on a p-type silicon substrate 1 by selective diffusion, and then a 5iOz film is formed on the p-type silicon substrate 1. After forming the 5iOz film 4, a predetermined portion of the 5iOz film 4 is removed by etching to form openings 43 to 4C.

Next, as shown in FIG. 1B, a silicon layer 5 is deposited over the entire surface by vapor phase growth using Si II a gas. Opening 4 in 5102" film 4 of this silicon layer 5
The portions corresponding to a to 4C are epitaxially grown on the p-type silicon substrate 1 and become single crystal regions 5a, but the portions of the silicon layer 5 formed on the Sin and film 4 are polycrystalline regions 5b (pointillary). area). Furthermore, a transition region 5C from single crystal to polycrystal is formed between the single crystal region 5a and the polycrystal region 5b. Note that since the vapor phase growth of the silicon layer 5 is normally performed at a high temperature of 1000° C. or higher, impurities in the buried layer 2 diffuse upward during the growth, and as a result, the top surface of the buried layer 2 becomes as shown in FIG. 1B. Distance 1l as shown
ldl (for example, about 0.3 μm).

Next, using a predetermined photoresist pattern (not shown), selectively ion-implanting an n-type impurity, for example, As, into a portion of the silicon layer 5 corresponding to the opening 4b;
Next, after removing the photoresist pattern, a predetermined annealing is performed to convert the portion of the silicon layer 5 corresponding to the opening 5C into an n-type.

Next, as shown in FIG. 1C, a thin SjO□ film 6 and a thin Si+Na film 7 are sequentially formed on the entire surface, and then a photoresist 8 is formed on the entire surface, followed by reactive ion etching (RI).
E) performs anisotropic etching to a predetermined thickness and etches the first
Set the state as shown in Figure D. Next, after forming a photoresist 9 in a predetermined shape on the silicon layer 5, using this photoresist 9 as a mask, an n-type impurity such as boron B (or BFi) is ion-implanted into the silicon layer 5 at a high concentration. B in the middle is indicated by 0).

Next, after removing the photoresist 8.9, as shown in FIG. 1E, a predetermined portion of the silicon layer 5 is removed by etching to form silicon layers 5d to 5f having a predetermined shape. After this,
By performing a predetermined annealing, the ion-implanted B is diffused and the silicon Ji5d, 5f is turned into p-type, leaving only a portion.

Note that the p-type portion of the silicon layer 5d constitutes a p-type graft base region 10 (also serving as a base extraction electrode). Further, the p-type portion of the silicon layer 5f constitutes a p-type emitter region 11 and a collector region 12. Note that the emitter region 11
An n-type base region 13 is constituted by the silicon layer 5f existing between the collector region l2 and the collector region l2.

Next, as shown in FIG. 1F, by thermally oxidizing the silicon layers 5d to 5f using the Si3N film 7 as a mask, 5i
(hL14 is formed. After this, Si, N, and film 7 are removed by etching.

Next, as shown in FIG. 1G, after etching and removing a predetermined portion of the 5i02 film 14 to form openings 148 to 14d, the opening 14b and the emitter region 11 and collector region 12 are etched.
A photoresist (15, 16) having a predetermined shape is formed corresponding to the SiO□ film 6 between the two.

Next, using these photoresists 15 and 16 as masks, p-type impurities and
For example, after selectively ion-implanting B, then removing the photoresist 15, 16, and performing a predetermined annealing, the B is diffused to form the graft base region 10.
A p-type base region I7 is formed. Note that the n-type silicon layer 5d existing between the base region 17 and the buried layer 2 constitutes a collector region 18.

Next, after removing the SiO□ film 6 by etching, the first H
As shown in the figure, a thin polycrystalline silicon film 19 is formed.

Next, the base region 17 is
．． After ion-implanting an n-type impurity, for example, arsenic As, into the semiconductor substrate 13, a predetermined heat treatment (emitter diffusion) is performed to form an n7-type emitter region 20 and an n'-type base extraction region 21.

After this, as shown in FIG.
By sequentially etching and removing predetermined portions of 19,
As shown in FIG. 1J, the electrode 2 has a two-layer structure consisting of ^p films 22a to 22f and polycrystalline silicon films 19a to 19f.
3 to 28 are formed. In this way, eminta order page area 20. n consisting of a base region 17 and a collector region 18
A pn-type bipolar transistor 29 (operating direction is perpendicular to the surface of the p-type silicon substrate I) and an emitter ftI region 11
, a lateral pnp type bipolar transistor 30 consisting of a base region 13 and a collector N region 12 (the operating direction is p
(parallel to the surface of the p-type silicon substrate 1) to complete a semiconductor device formed on the p-type silicon substrate 1. A plan view of the semiconductor device shown in FIG. 1J with the electrodes 23 to 28 omitted is shown in FIG.
line cross-section).

According to the above embodiment, the npn bipolar transistor 29 and the lateral pnp bipolar transistor 30 can be simultaneously formed on the p type silicon substrate 1 through the manufacturing process shown in FIGS. 1A to 1J. There is no need to add a special process to form the type bipolar transistor 30, and therefore the manufacturing process does not become complicated. In addition, the widths of the base regions 17.13 and emitter regions 20 of the npn bipolar transistor 29 and the lateral pnp bipolar transistor 30 can be miniaturized to the submicron level, as in the past, and this makes it possible to miniaturize the elements. It is possible.

The present invention is not limited to the above-described embodiments, but various modifications can be made based on the technical idea of the present invention. For example, after forming the 5i3Nn film 7 in the step shown in FIG. 1C, as shown in FIG. If a resist 31 is formed and then the 5IsN4 film 7 is etched using the photoresist 31 as a mask to remove the portion of the Si:+LL12 corresponding to the opening 4c, the oxidation performed in the step shown in FIG. 5iOz thick even in parts
Since the film 14 is formed, as shown in FIG. 3B, the electrode 27 of the base region 13 is taken out from the n-type buried layer 2.
It is possible to form a lateral pnp type bipolar transistor via the base extraction region 21 of the same <n'' type.For example, after forming the 5ial14 film 7 in the step shown in FIG. 1C or in the step shown in FIG. In the state shown, if n-type impurities are selectively ion-implanted into the portion of the silicon layer 5 corresponding to the opening 4C of the film 14 to increase the impurity concentration in this portion, the punch-through breakdown voltage can be improved. It is possible.

Effects of the Invention According to the method for manufacturing a semiconductor device according to the present invention, especially the first
First and second semiconductor layers of a second conductivity type, which are separated from each other by a predetermined distance, are placed in a portion of the conductivity type semiconductor layer corresponding to the opening of the insulating layer.
Since this method forms a semiconductor region of By doing so, it is possible to simultaneously form elements of different conductivity types on the same semiconductor substrate. Therefore, it is possible to manufacture high-density and high-performance semiconductor devices.

[Brief explanation of the drawing]

1A to 1J illustrate the method for manufacturing a semiconductor device according to the present invention using an npn bipolar transistor and a lateral pnp transistor.
2 is a cross-sectional view showing the process order of an embodiment applied to the manufacture of a semiconductor device in which a type bipolar transistor is provided on the same substrate. FIG. 2 is a plan view of the semiconductor device shown in FIG. 3A and 3B are cross-sectional views similar to FIGS. 1C and 1J showing a modification of the present invention. In addition, in the symbols used in the drawings, 4--------・----SiO, film (insulating layer) 1 (
1--------------graft base area 1
3, 17---11---Base region 18---
Collector regions 23 to 2B-----one electric conductor 29---------------n p n-type bipolar transistor.

Claims (1)

[Claims] a step of forming a semiconductor region of a first conductivity type on a semiconductor substrate; a step of forming an insulating layer on the semiconductor substrate having an opening corresponding to the semiconductor region of the first conductivity type; and a step of forming the insulating layer on the semiconductor substrate. forming a first conductivity type semiconductor layer on the semiconductor substrate and the insulating layer exposed in the opening of the first conductivity type semiconductor layer; a step of forming first and second semiconductor regions of a second conductivity type that are spaced apart from each other by a predetermined distance in the portions where the semiconductor devices are formed.