JPS6120147B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a semiconductor device that can be integrated at a higher density than before.

Conventionally, a semiconductor device, for example, a static type memory circuit, as shown in FIG.
7, load transistors 8 and 9, and drive transistors 4 and 5. The disadvantage of this cell is that it has a large number of transistors, and when integrated, it occupies a large area on a chip. Therefore, it is impossible to realize a memory chip with a large degree of integration.

Therefore, an object of the present invention is to
An object of the present invention is to provide an element structure for configuring a semiconductor device such as a static type memory cell.

FIG. 2 shows a circuit diagram of an embodiment of the present invention, and FIGS. 3 and 4 show the structure of an element for concretely realizing the embodiment of FIG. 2 of the present invention. It is something that The principle of operation will be explained with reference to FIG. In FIG. 2, the switch transistors 15, 16 whose sources are connected to the data lines 11, 12 and the gates connected to the word line 10, and the drive transistors 13, 14 are the same as in FIG. , thereby forming a flip-flop type connection. The gist of this embodiment is to form parasitic bipolar transistors 17 and 18 at the drains of transistors 13 and 14 from a substrate terminal 19 supplied with a power supply voltage _VDD , and to use them in a state where a peak current flows. , which generates a weak current path, thereby making it possible to retain static stored information.

FIGS. 3 and 4 show a concrete method of forming this parasitic bipolar transistor.
In the figure, 24 and 30 are MOS transistors 1
The gate electrode is either one of No. 3 and No. 14. Board 2
0 and 25 are, for example, n-type silicon of 1 to 10 Ω·cm, on which p-type well layers 21 and 26 are formed. However, in FIG. 4, the thickness of the p-type well layer becomes thinner at a portion 27. 22,
28 is a diffusion layer that forms the drains of the MOS transistors 13 and 14, and 23 and 29 are diffusion layers that also form the sources of the n ⁺ type. Therefore, p
A parasitic bipolar transistor is formed having the type wells 21 and 26 (or 27) as a base, the n type substrates 20 and 25 as collectors, and the n ⁺ layers 22 and 28 as emitters. On the other hand, n ⁺ layer 23, 29
When current flows ^between the
(Figure), by reducing the thickness and concentration of the p-well layer directly below the n ⁺ layer 28, a leakage current is generated only in the required portion between the collector and the emitter, thereby forming the load elements 17 and 18. This is the gist of the present invention. Of course, the current required for static operation of the memory cell is about 10 ^-11 A, so even if the thickness of the p-well layer is reduced across all pairs, the circuit in Figure 2 will still operate, reducing power consumption. The increase is small.

In order to realize the structure shown in FIG. 3, the diffusion time of n region 22 may be made longer than that of 23. For example, in advance,
22 region is doped with phosphorus and heated at 1000℃ for 40℃.
Diffusion. Next, 1×10 ¹⁶ cm ^-2 of phosphorus or arsenic was implanted in the area 23, and in the case of phosphorus, 10
In the case of arsenic, diffuse at 1000℃ for 50 minutes. In this case, 22 has a depth of 2.0 μm and 23 has a depth of 0.5 μm, making it possible to create junctions with different depths.

Similarly, to realize the structure shown in FIG.
It is sufficient to pre-diffuse 27 p-wells and further diffuse 27 regions.

Next, as shown in FIG. 5, a recess 31 is formed in a part of the silicon surface that will become the drain region of the MOS transistor, and then n-type impurities are added at a high concentration to form a p-well 32 under the drain diffusion layer. The thickness of the structure can be reduced, and a structure having the same function as that shown in FIG. 4 can be realized.

In the above structure, according to the results of experiments, by setting the surface concentration of the p-well layer to 1×10 ¹⁶ cm ^{-3 and} the thickness of the thick part of the p-well layer to 5 μm, that part and n ⁺ Although the leakage current of the layer was less than 10 ^-13 A, a peak current of 10 ^-10 A was generated by providing a portion with a thickness of 3 μm. When operated at 5V, this memory cell has a holding current of 10 ^-10 A, and even if ¹⁰⁴ bits are integrated, the holding current is only 1 μA at most.

In the embodiment described above, a small current is caused to flow between the drain of the MOS transistor formed in the well and the substrate due to punch-through or leakage current between the collector and emitter of the transistor, but as shown in FIG. A heavy metal such as Au, which forms a deep impurity level only in the well region under the drain diffusion layer 33 of the MOS transistor.
The leakage current flowing between the drain diffusion layer and the substrate may be increased by adding Ag or Cu or by irradiating with an electron beam or impurity ions.

The advantage of the above embodiment is that the memory cell occupies a small area. The cell shown in Figure 1 is
whereas requiring a cell area of 70 × 120 μm ²
The memory cell of the present invention requires 1/8 of this area.
Therefore, the cost per cell can be reduced to about 1/8.

Although the present invention has been described above with respect to flip-flop type memory cells, it is of course possible to apply the present invention to logic circuits. Figures 7 and 8
The figure is an example diagram of a circuit to which the present invention is applied to a 3-input NOR gate, with transistors 35, 36, 37,
39, 40 and 41 are NMOS transistors for switches 38 and 43, which are vertical parasitic bipolar transistors having the same leakage as those shown in FIGS. 17 and 18. These act as load elements and supply a current of approximately 10 ^-10 A to the output terminal. The difference between Figure 7 and Figure 8 is
In FIG. 8, a PMOS transistor 42 for switching is added, which allows a current of about 10 to 100 .mu.A to flow only when charging the output end at high speed. In steady state, the current consumption of these circuits is
It has the advantage of low power consumption of 10 ^-10 A and less than 1/3 the area of conventional complementary cells.

[Brief explanation of the drawing]

Figure 1 is a diagram showing an example of a conventional memory cell, Figure 2 is a diagram showing an example of a conventional memory cell.
The figure is a circuit diagram showing one embodiment of the present invention, Figure 3 is a structural diagram showing a specific example of the configuration of Figure 2 of the present invention, and Figures 4, 5, and 6 are specific configurations of Figure 2. Other structural diagrams of the example, FIGS. 7 and 8, are circuit diagrams showing an embodiment in which the present invention is applied to a logic circuit.

Claims (1)

[Claims] 1. A semiconductor device having a semiconductor substrate, a well region of a conductivity type opposite to that of the substrate provided in a certain region of the semiconductor substrate, and a MOS field effect transistor provided in the well region, wherein the MOS type field effect transistor is provided in the well region. The depth of the well region under one of the source and drain regions of the field effect transistor is shallower than the depth of the well region under the other of the source and drain regions of the MOS field effect transistor, and A bipolar transistor comprising one of the source and drain regions of the MOS field effect transistor, the well region, and the semiconductor substrate is configured in a shallow portion of the well region. Semiconductor equipment.