JPS61201458A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61201458A JPS61201458A JP60042352A JP4235285A JPS61201458A JP S61201458 A JPS61201458 A JP S61201458A JP 60042352 A JP60042352 A JP 60042352A JP 4235285 A JP4235285 A JP 4235285A JP S61201458 A JPS61201458 A JP S61201458A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon layer
- silicon nitride
- nitride film
- polysilicon
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 49
- 229920005591 polysilicon Polymers 0.000 claims abstract description 49
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims 2
- 238000005530 etching Methods 0.000 abstract description 15
- 230000003647 oxidation Effects 0.000 abstract description 9
- 238000007254 oxidation reaction Methods 0.000 abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- 238000007493 shaping process Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000003068 static effect Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔−明の技術分野〕
本発明はＥ／Ｒ（エンへンスメント／抵抗）型ＣＭＯＳ
スタチックＲＡＭ（ランダム・アクセス・メモリ）の高
抵抗形成Ｃ：適した半導体装置の製造方法に関する。[Detailed description of the invention] [Technical field of the present invention] The present invention relates to an E/R (enhancement/resistance) type CMOS
HIGH RESISTANCE FORMATION OF STATIC RAM (RANDOM ACCESS MEMORY) C: Concerning a method of manufacturing a suitable semiconductor device.
従来のＥ／Ｒ型ＣＭＯＳスタティックＲＡＭのメモリセ
ル回路図を第３因に示す。図中Ｒ１）Ｒ−はポリシリコ
ン抵抗＊ ”１ ｓ”！は駆動用トランジスタ＊ Ｔ
”ａ ｔ Ｔｒ４はトランスファ素子、ＤＬ 、ＤＬ
はデータ線、ＷＬはワード線、ｖｃｃ、ｖｓｓは電源で
ある。このＥ／Ｒ型ＣＭＯ８スタティックＲＡＭはスタ
ンドパイ電流が小さいのが大きな特徴であり、このこと
を達成するために、Ｅ／Ｒ型メセメモリセルいてはポリ
シリコン抵抗Ｒの高抵抗化が問題となっている。A memory cell circuit diagram of a conventional E/R type CMOS static RAM is shown as the third factor. In the figure, R1) R- is a polysilicon resistance* “1 s”! is the driving transistor *T
"a t Tr4 is a transfer element, DL, DL
is a data line, WL is a word line, and vcc and vss are power supplies. A major feature of this E/R type CMO8 static RAM is that the standby current is small, and in order to achieve this, the problem is that the resistance of the polysilicon resistor R in the E/R type mesememory cell is increased. .
従来のポリシリコン抵抗の形成法を第４図に示す。まず
第４図（ａｌの如く、シリコン基板１上のシリコン酸化
膜２上にポリシリコン層３を形成後、フォトレジスト４
を塗布し、抵抗部分のレジストのパターニングを行なう
。次に第４図（ｂｌの如く、レジスト４をマスクにポリ
シリコン層３のエツチングを行ない、最後に第４図（Ｃ
）の如くマスクのレジスト４を除去するものである。A conventional method of forming a polysilicon resistor is shown in FIG. First, as shown in FIG. 4 (al), after forming a polysilicon layer 3 on a silicon oxide film 2 on a silicon substrate 1, a photoresist 4
, and pattern the resist portion of the resistor. Next, as shown in FIG. 4 (BL), the polysilicon layer 3 is etched using the resist 4 as a mask, and finally, as shown in FIG.
), the resist 4 of the mask is removed.
ところでポリシリコン層３の高抵抗化のためには、この
ポリシリコン抵抗の幅を小さくすればよいのであるが、
従来のポリシリコン抵抗形成法には１次の２つの問題点
がある。（イ）レジストのパターニングの最小線幅が現
在のところ。By the way, in order to increase the resistance of the polysilicon layer 3, it is sufficient to reduce the width of this polysilicon resistance.
The conventional polysilicon resistor formation method has two primary problems. (a) The current minimum line width for resist patterning.
段差のあるところで１．５μｍ前後６段差のないところ
で１．２μｍ前後であるため、レジスト３を極線に細く
パターニングできない。（０１ポリシリコン層のエツチ
ングは等１件ドライエツチング法（いわゆるＣＤＥ）で
行なっているため。It is around 1.5 μm where there is a step difference and around 1.2 μm where there is no step difference, so it is not possible to pattern the resist 3 extremely thinly. (This is because the etching of the 01 polysilicon layer is performed by the dry etching method (so-called CDE).
エツチングの制御性、再現性があまりよくなく。Etching controllability and reproducibility are not very good.
そのためポリシリコン層３の幅にばらつきを生じてしま
う。This causes variations in the width of the polysilicon layer 3.
本発明は上記実情に鑑みてなされたもので。 The present invention has been made in view of the above circumstances.
微細なポリシリコン抵抗を再現性よく形成できる半導体
装置の製造方法を提供しようとするものである。The present invention aims to provide a method for manufacturing a semiconductor device that can form fine polysilicon resistors with good reproducibility.
本発明はポリシリコン抵抗を、エツチングで細く形成す
るのではなく、酸化で細く形成するようにしたものであ
る。In the present invention, the polysilicon resistor is formed not by etching but by oxidation.
′以下図面を参照して本発明の一実施例を説明する。第
１図（ａ）に示される如く、シリコン基板１）上のシリ
コン酸化膜１２上にポリシリコン層１３を形成後、その
上にシリコン窒化膜１４を形成する。次に第１図（ｂｌ
に示す如くフォトレジスト１５を塗布すると共にパター
ニングを行なう。次に第１図（Ｃ）に示す如く、フォト
レジスト１５をマスクにしてシリコン９化Ｗｘ４のエツ
チングを、異方性エツチング（ＲｅａｃｔｉｖｅＪｏｎ
Ｅｔｃｈｉｎｇ 略してＲＩＥ）により行なう。'One embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 1(a), after a polysilicon layer 13 is formed on a silicon oxide film 12 on a silicon substrate 1), a silicon nitride film 14 is formed thereon. Next, Figure 1 (bl
A photoresist 15 is applied and patterned as shown in FIG. Next, as shown in FIG. 1(C), using the photoresist 15 as a mask, the etching of the silicon 9 oxide Wx4 is performed by anisotropic etching (Reactive Jon etching).
Etching (abbreviated as RIE) is used.
次にフォトレジスト１５及びシリコン窒化膜１４をマス
クにして、ポリシリコン＄１３のエツチングをＲＩＢに
より行なう、ここで段差のある部分のポリシリコンのエ
ツチングは１段差のない場合より長いエツチング時間が
必要である。その際フォトレジストのエツチングもある
程度進行し、そのためポリシリコン幅のばらつきが大き
くなる。本発明ではポリシリコン層１３のエツチングに
対するマスクとして、フォトレジスト１５及びシリコン
窒化膜１４を使用し、かつ従来のＣＤＥに対しＲＩＥに
よるエツチングを行なっているので、再現性、制御性よ
くポリシリコン抵抗を形成できる。ポリシリコン層１３
のエツチング終了後、第１図（ｄｌの如くフォトレジス
トを除去し、第１図（ｅｌの如くシリコン窒化膜１４を
マスクとして、ボ、リシリコン層１３の酸化を行なう、
このポリシリコンの酸化は、非常に再現性、制御性良く
行なえ、またポリシリコン層１３の幅は酸化時間を長く
することにより、基本的にいくらでも微細にすることが
できる。但し高温、長時間の酸化即ち熱処理は、半導体
基板中の不純物の再分布を促進し＋
（例えばＮ 拡散層の接合深さや、低抵抗ポリシリコン
からの燐の半導体基板への拡散）、トランジスタ特性（
二悪影響を及ぼす恐れがあるので、酸化方法としては、
低温で酸化速度の速い方法を用いる必要がある。最後に
第１図（ｆ）の如くシリコン窒化膜１４を除去し１例え
ばＲＩＥ法により表面を平担化するものである。Next, using the photoresist 15 and the silicon nitride film 14 as a mask, etching the polysilicon $13 is performed by RIB. Etching the polysilicon in the portion with a step requires a longer etching time than in the case where there is no step. be. At this time, etching of the photoresist also progresses to some extent, which increases the variation in the polysilicon width. In the present invention, the photoresist 15 and the silicon nitride film 14 are used as a mask for etching the polysilicon layer 13, and etching is performed by RIE as opposed to conventional CDE, so that the polysilicon resistance can be etched with good reproducibility and controllability. Can be formed. Polysilicon layer 13
After completing the etching, the photoresist is removed as shown in FIG. 1 (dl), and the silicon layer 13 is oxidized using the silicon nitride film 14 as a mask as shown in FIG. 1 (el).
This oxidation of polysilicon can be performed with very good reproducibility and controllability, and the width of the polysilicon layer 13 can basically be made as fine as desired by increasing the oxidation time. However, high-temperature, long-term oxidation, or heat treatment, promotes the redistribution of impurities in the semiconductor substrate (e.g., the junction depth of the N diffusion layer, the diffusion of phosphorus from low-resistance polysilicon into the semiconductor substrate), and the transistor characteristics. (
The oxidation method is as follows:
It is necessary to use a method that has a high oxidation rate at low temperatures. Finally, as shown in FIG. 1(f), the silicon nitride film 14 is removed and the surface is flattened by, for example, RIE.
第２図は本発明の他の実施例で、第１図げ）の表箇平担
化を行なわずに、ポリシリコン上を平担化する方法であ
る。この場合第２図（ａｌまでの工程は、第１図（ａ）
ないし第１図（ｅｌまでの工程と同じである。即ちシリ
コン窒化膜１４をマスクにしたポリシリコン層１３の酸
化がある程度進んだところで、第２図（ｂｌの如くシリ
コン窒化膜１４を除去し、第２図（ｃｌの如く再度ポリ
シリコン層１３の酸化を行なうことにより、ポリシリコ
ン層１３上の酸化膜の平担化を図る。この方法では、ポ
リシリコン１３上に酸化膜１２が形成されるので、ポリ
シリコン層１３上に導電体を形成↑る際、該ポリシリコ
ンと導電体との絶縁を行なうための絶縁体を形成する工
程を追加する必要がないし、またポリシリコン層１３が
酸化されてその厚さが減少するので、更に高抵抗のポリ
シリコン抵抗が得られるものである。FIG. 2 shows another embodiment of the present invention, which is a method of planarizing the surface of polysilicon without performing the planarizing of the surface area as shown in FIG. 1. In this case, the steps up to Figure 2 (al) are as shown in Figure 1 (a).
The steps from FIG. 1 to EL are the same. That is, when the oxidation of the polysilicon layer 13 using the silicon nitride film 14 as a mask has progressed to a certain extent, the silicon nitride film 14 is removed as shown in FIG. By oxidizing the polysilicon layer 13 again as shown in FIG. 2 (cl), the oxide film on the polysilicon layer 13 is planarized. Therefore, when forming a conductor on the polysilicon layer 13, there is no need to add a step of forming an insulator for insulating the polysilicon and the conductor, and the polysilicon layer 13 is not oxidized. Since the thickness of the polysilicon resistor is reduced, a polysilicon resistor with even higher resistance can be obtained.
以上説明した如く本発明によれば、酸化でポリシリコン
層を細く形成するので、再現性、制御性よく微細な幅を
もつポリシリコン抵抗が形成できるものである。As explained above, according to the present invention, since the polysilicon layer is formed thin by oxidation, a polysilicon resistor having a fine width can be formed with good reproducibility and controllability.
＄１図は本発明の一実施例の工程図、第２図は本発明の
他の実施例の工程図、第３図はル１型ＣＭＯＳスタティ
ックＲＡＭのメモリセル回路図、ｆｌＩＪ４図は従来の
ポリシリコン抵抗を得る工程図である。
１ノ・・・シリコン基板、１２・―・シリコン酸化膜。
１３・・・ポリシリコン層、１４・・・シリコン窒化膜
。
１５・・・フォトレジスト膜。
出願人代理人 弁理士 鈴 江 武 彦第１図
＜ｃ＞
第２図
（ａ） （ｃ）（ｂ）
第３図
第４因
（ａ）
（ｃンｌ。
（ｂ）Figure 1 is a process diagram of one embodiment of the present invention, Figure 2 is a process diagram of another embodiment of the present invention, Figure 3 is a memory cell circuit diagram of a Le1 type CMOS static RAM, and Figure flIJ4 is a diagram of a conventional one. FIG. 3 is a process diagram for obtaining a polysilicon resistor. 1...Silicon substrate, 12...Silicon oxide film. 13... Polysilicon layer, 14... Silicon nitride film. 15...Photoresist film. Applicant's representative Patent attorney Takehiko Suzue Figure 1 <c> Figure 2 (a) (c) (b) Figure 3 Factor 4 (a)
(cnl. (b)
Claims (4)
層上にシリコン窒化膜を形成し該ポリシリコン層及びシ
リコン窒化膜を同形状にパターニングする工程と、前記
シリコン窒化膜をマスクにして前記ポリシリコン層を酸
化する工程とを具備したことを特徴とする半導体装置の
製造方法。(1) A step of forming a silicon nitride film on a polysilicon layer formed on an insulating film of a semiconductor substrate and patterning the polysilicon layer and the silicon nitride film in the same shape, and using the silicon nitride film as a mask to 1. A method for manufacturing a semiconductor device, comprising the step of oxidizing a polysilicon layer.
アクティブ・イオン・エッチングにより行なうことを特
徴とする特許請求の範囲第１項に記載の半導体装置の製
造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the step of patterning the polysilicon layer is performed by reactive ion etching.
層上にシリコン窒化膜を形成し該ポリシリコン層及びシ
リコン窒化膜を同形状にパターニングする工程と、前記
シリコン窒化膜をマスクにして前記ポリシリコン層を酸
化する工程と、前記シリコン窒化膜除去後更に前記ポリ
シリコン層の酸化を行なう工程とを具備したことを特徴
とする半導体装置の製造方法。(3) forming a silicon nitride film on the polysilicon layer formed on the insulating film of the semiconductor substrate and patterning the polysilicon layer and the silicon nitride film in the same shape; and using the silicon nitride film as a mask, A method for manufacturing a semiconductor device, comprising the steps of: oxidizing a polysilicon layer; and further oxidizing the polysilicon layer after removing the silicon nitride film.
アクティブ・イオン・エッチングにより行なうことを特
徴とする特許請求の範囲第３項に記載の半導体装置の製
造方法。(4) The method of manufacturing a semiconductor device according to claim 3, wherein the step of patterning the polysilicon layer is performed by reactive ion etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60042352A JPS61201458A (en) | 1985-03-04 | 1985-03-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60042352A JPS61201458A (en) | 1985-03-04 | 1985-03-04 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61201458A true JPS61201458A (en) | 1986-09-06 |
Family
ID=12633638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60042352A Pending JPS61201458A (en) | 1985-03-04 | 1985-03-04 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61201458A (en) |
-
1985
- 1985-03-04 JP JP60042352A patent/JPS61201458A/en active Pending
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