JPS61200460A - Apparatus for removing steady pattern noise in scanning signal - Google Patents

Abstract

PURPOSE:To remove the steady pattern noise in a scanning signal at a high S/N ratio, by performing the processing of a digital signal. CONSTITUTION:An adder 4 is equipped with two input terminal groups of which the number of figures are more than by at least 2N-bits than the number of output bits of a holding means 3 and the output signal of the holding means 3 is successively applied to the terminal lower than the (N+1)th terminal from the upper rank of one input terminal group while the output of a first subtractor 8 is successively applied to the other terminal group from the terminals of the upper rank of the former terminal group. The addition output before one scanning applied from a data accumulation means 6 is respectively applied to two input terminal groups of the first subtractor 8. Addition output is successively applied to an input side to be subtracted from the terminals of the upper rank but addition output is successively applied to a subtrahend input side from the terminal being (N+1)th from the terminals of the upper rank. By this method, a scanning signal of a steady state is accumulated in the data accumulation means 6 and subtracted from an hourly scanning signal by a second subtractor 9.

Description

[Detailed Description of the Invention] 2nd Minute in the Industry This invention detects a steady pattern of noise mixed in a flaw detection signal with a constant period and various communication signals, and removes it from a scanning signal. The present invention relates to a stationary pattern noise removal device.

For example, an electronic transfer type eddy current flaw detection device arranges a plurality of detection coils close to the surface of a material to be inspected, and sequentially applies an excitation signal to the detection coils. Disturbances in eddy currents on the surface of the inspected material are detected without rotating or swinging the inspected material. The terminal voltages of the respective detection coils are added together to form a scanning signal, but this signal contains a certain pattern of noise due to errors in the arrangement or shape of each of the detection coils. Therefore, in order to remove such stationary pattern noise, the scanning signal is passed through a CCD 1l extension element or a BBD delay element to provide a time-delayed signal and a detection signal with no time delay is differentiated. This eliminates stationary pattern noise.

However, according to conventional devices using CCD, etc.,
Residual noise is generated due to residual charge peculiar to CCDs, zero point drift, nonlinearity of amplification characteristics, phase delay, etc.
It was difficult to obtain a high S/N ratio.

This invention was made in view of the above circumstances, and an object of the present invention is to provide a device for removing stationary pattern noise in a scanning signal, which can remove stationary pattern noise in a scanning signal with a high S/N ratio. There is.

11" One way to make a 11" divination "16L and 1"Y technique.And for that purpose, this invention has the following features.

The scanning signal is applied to the signal holding means which is the first stage of the device of this invention. The signal holding means converts the scanning signal into/D,
This is held for a certain period of time and given to the next stage adding means.

The adding means includes two groups of input terminals each having at least 2N bits (N is an arbitrary integer) of digits greater than the number of output nodes of the holding means. The output signal of the holding means is sequentially applied to the terminals lower than the N+1-th terminal from the upper end of one input terminal group.

The other input terminal group is supplied with the output of the first subtracting means, which will be described later, in order from the higher-order terminals.

The output of the addition means is given to the data N product means, where the addition output for -scanning is divided and stored in each storage area. This data storage means sequentially updates the contents of the storage area when a new addition output is input, and sequentially provides the addition output stored in the storage area before scanning.

The pre-scan addition outputs provided from the data storage means are respectively provided to two input terminal groups of the first subtracter means. However, one input terminal group, that is, the minuend input side, is given the addition output in order from the higher-order terminals, but the other input terminal group, that is, the subtrahend input side, is given the addition output from the higher-order terminals.
Addition outputs are given in order from the +1st terminal.

The output of the first subtraction means is given as one input to the addition means as described above, so that a steady state scanning signal is stored in the data storage means.

A steady state scanning signal outputted from the data storage means is subtracted from the momentary scanning signal outputted from the signal holding means by a second subtraction means, whereby a steady state pattern is obtained from the momentary scanning signal. Noise is removed, and an autobalanced output including signals showing steep changes such as flaw signals can be obtained.

FIG. 1 is a block diagram schematically showing the configuration of an embodiment of the present invention.

For example, in an electronic transfer type eddy current flaw detection device, the terminal voltages of the detection coils constituting the detection coil group are added together, a constant alternating current component is subtracted, and then the voltage is applied to the sample and hold circuit 1 as a scanning signal. The output of the sample and hold circuit l is given to an A/D converter 2. This A/D converter 2 converts the input signal into a 12-bit digital signal.

The scanning signal converted into a digital signal is given to the latch circuit 3. The output of launch circuit 3 is 1.1/2 from the upper
．． Each weighting is 1/22, 1/23, . . . 1/2 I+. The sample hold circuit 1, A/D converter 2, and latch circuit 3 described above constitute a signal holding means that A/D converts the scanning signal and holds it.

The output of the latch circuit 3 is given to a 32-bit adder 4. This adder 4 has two input terminal groups A and B, A1-A32 and B1-B32.

Each terminal of the input terminal group A and B of the adder 4 is 1 in order from the top.
．． Each weighting is 1/2, 1/22, . . . 1/2''.

The output of adder 4 is given to launch circuit 5.

The launch circuit 5 is composed of, for example, a 32-bit three-state latch. Latch circuit 5 is connected to memory 6 and launch circuit 7 via a data bus. The memory 6 is an RA with a data storage area up to 256 addresses.
M, and each address has a storage capacity of 32 bits.

The latch circuit 7 is connected to a 32-bit subtracter 8 and a 12-bit subtracter 9 via a data bus. The subtracter 8 includes two input terminal groups A and B for subtractive numbers A1 to A32 and subtractive numbers B1 to B32.

On the other hand, the subtractor 9 uses the minuends A1 to A12 and the subtrahends B1 to
It has two input terminal groups A and B of B12.

The output of the subtracter 8 is applied to one input terminal group B composed of terminals 81 to B32 of the adder 4. Also,
The output of subtracter 9 is given to latch circuit 10. The output of the launch circuit 10 is converted into an analog signal by a 12-bit D/A converter 11 and output as an autobalance signal.

Next, the operation of the apparatus shown in FIG. 1 will be explained. Second
The figure shows operating waveforms of each part of the device.

The sample hold circuit 1 samples the input scanning signal at a frequency that is an integral multiple of the scanning frequency. In this example, the - period scanning signal is divided into 256. The sampled scanning signal is converted into a 12-bit digital signal by the A/D converter 2, and further held in the launch circuit 3 for a certain period of time.

A momentary scanning signal represented by a 12-bit digital signal is applied to input terminal group A of adder 4.

However, the 12-bit signal is sequentially input to input terminals All to A22 of input terminal group A. Therefore, O is set to the terminals A1 to AIO and A23 to A32 to the input terminal group. In this way, the output S of the latch circuit 3 is applied to the input terminal group A of the adder 4 with a shift of 10 bits from the higher order bits, which is equivalent to the signal S being multiplied by 1/21O and applied to the adder 4. .

On the other hand, the input terminal group B of the adder 4 is supplied with the output of the subtracter 8 expressed by the following formula (%). Here, T indicates the output of the launch circuit 7 in a steady state. The output of the subtracter 8 is a 32-bit digital signal, and the signals are B1 to B in order from the higher order.
32 input terminals.

The output of the adder 4 is held by a latch circuit 5 and is sequentially applied to each address of the memory 6. The memory 6 sequentially updates the contents of each address by being given the new addition output. However, before the addition output is given, the addition output from the previous scan stored at the address is given to the latch circuit 7. The above operation will be explained in chronological order using FIG.

First, as shown in FIG. 6(a), an address to which the output of the adder 4 is to be written is specified in the memory 6. The T1 section shown in the figure is the section where the addition output obtained in the second scan is written to the first address, T2 is the section where it is written to the second address, and T3 is the section where the addition output is written to the third address. are shown respectively.

As shown in FIG. 6C, before a part of the addition output obtained by the second scan is written to the second address of the memory 6, it is written to the second address during the first scan. The data stored is read out. The read data is held in the latch circuit 7 at the timing shown in FIG. As a result, as shown in FIG. 3(g), the output of the latch circuit 7 changes from the addition output at the first address obtained through the first scan to the addition output at the second address.

Then, as shown in FIG. 6(h), in synchronization with the operation of the latch circuit 7, the launch circuit 3 latches the addition output obtained by the second scan. As a result, as shown in the figure (+), the output of the launch circuit 3 is the second signal obtained by the second scan.

This second signal is added to the output of the subtracter 8 and applied to the latch circuit 5. The launch circuit 5 latches this addition output at the timing shown at tb+ in the figure. The latch circuit 3 then outputs the second signal obtained by the second scan, as shown in fcl of the figure.

Then, the memory 6 receives the write command at the timing shown in FIG.
By invading the address, the contents of the second address are updated.

In this way, the contents of each address in the memory 6 are updated sequentially, and the addition output of each address one scan ago is given to the latch circuit 7.

The output T of the launch circuit 7 is sequentially input to each terminal A1 to A32 of the minuend input terminal group A of the subtracter 8. Further, the output T is inputted to Bll to B32 of the other subtraction input terminal group B of the same subtracter 8 in order from the most significant bit. Therefore, input terminals 81 to B12 are set to 0. In this way, the output T of the latch circuit 7 is connected to one input terminal group B.
By shifting the bits and inputting the input, the subtracter 8 inputs (1
-1/210)・T gives the subtraction power. As mentioned above, this subtraction output is
It is applied to the input terminals 1 to B32 in order.

By repeating the above-described operation 256 times for one scan, the output of the adder 4 converges in a steady state, and the output T of the adder 4 in the steady state is stored in the memory 6. That is, in a steady state, the relationship expressed by the following equation holds.

(However, M=210). From the above equation, it can be seen that S=T, that is, the output of the latch circuit 3 and the output of the launch circuit 7 are equal in the steady state.

Therefore, the subtracter 9 for subtracting the data of the latch circuit 7 from the data of the latch circuit 3 outputs 0 in the steady state. This indicates that the steady pattern noise has been removed from the output of the launch circuit 3 which provides the momentary scanning signal.

On the other hand, if the output of the launch circuit 3 includes a component that shows a steep change, such as a scratch signal, the steady state output is subtracted from the output of the launch circuit 3 at this time, and the subtracter 9 outputs only steeply changing components such as scratch signals, which do not include stationary pattern noise. By holding the output of the subtracter 9 at the timing shown in the second scan, the latch circuit 10 adjusts the first balance obtained by the second scan as shown in the figure (kl). The output is switched to the second balanced output.The output of the latch circuit 10 is converted into an analog signal by the D/A converter 11 at the next stage and output as an autobalancer signal.

In the embodiments described above, processing is performed by an adder or a subtracter without using arithmetic means such as a computer or a multiplication/division circuit, so that the signal processing speed can be extremely high.

As explained in connection with the adder 4 and the subtracter 8, the number of transition bits N of one input data is related to the time constant of the entire device according to the present invention, and the integer N is It is configured so that it can be selected more arbitrarily. Incidentally, as the integer N becomes smaller, the time constant of the device also tends to become smaller. Conversely, by increasing N, the time constant of the device can be increased.

Therefore, after the launch circuit 3, the adder 4 shown in FIG.
By installing multiple sets of the following circuits in parallel and setting the integer N of each circuit installed in parallel to a different integer, it is possible to detect a signal according to the rate of change over time. In equipment, etc., it becomes possible to sort out whether the flaws to be detected are long or short.

Furthermore, the memory 6 described in the embodiment is not limited to being configured with a RAM, but is, for example, a first-in first-out (FIFO) memory.
) Alternatively, it may be configured using a shift register. Further, the apparatus shown in FIG. 1 can also be constructed by a computer, a sequencer, or a bit slicer.

Further, the first subtracting means shown in FIG. 1 is not limited to the subtracter 8, but may be a multiplier, a divider, or a product-sum integrated circuit that performs the same function.

Further, instead of the adder 4 as shown in FIG. 1, a product-sum integrated circuit may be used.

Wataru Hatan: As is clear from the above explanation, since the device according to the present invention obtains an autobalanced output through digital signal processing, it is less prone to drift and phase shift compared to conventional devices that perform analog processing. Therefore, a good S/N ratio can be obtained.

Furthermore, since the apparatus according to the present invention does not perform so-called rounding of answers during digital calculation processing, there is no calculation error, and therefore the generation of residual noise can be further reduced.

Further, according to the present invention, steady pattern noise can be removed with a relatively simple configuration, so a relatively inexpensive device can be provided.

In addition, the response time of the device can be arbitrarily set by shifting one of the data input to the addition means and the first subtraction means constituting the device by an arbitrary number N of bits from the higher order. Response time can be easily changed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing the configuration of an embodiment of the present invention, and FIG. 2 shows operational waveforms of each part of the apparatus shown in FIG. DESCRIPTION OF SYMBOLS 1... Sample hold circuit, 2... A/D converter, 3.5.1o... Latch circuit, 4... Adder, 6
...Memory, 8.9. Eye subtractor, 11...D/Δ converter.

Claims (1)

[Claims] (1) A signal holding means for A/D converting a scanning signal and holding it; and two input terminal groups having at least 2N bits (N is an arbitrary integer) of digits greater than the number of output bits of the holding means. The signal from the holding means is sequentially given to the terminals lower than the N+1st terminal from the upper end of one input terminal group, and the output of the first subtracter means to be described later is applied to the upper end of the other input terminal group. an adding means that is sequentially applied from a terminal of the adding means; and time-divisionally dividing the addition output for one scan that is applied from the adding means and sequentially storing it in a storage area at a predetermined address for each scan;
data storage means that sequentially updates the contents of each of the storage areas when a new addition output is input, and sequentially provides the addition output of the previous scan; and input terminals that receive the output of the data storage means in order from the upper terminal. a first subtraction means for subtracting the data of another input terminal group, which is given in order from the N+1st terminal to the upper terminal, from the output of the group; and subtracting the output of the data storage means from the output of the signal holding means. and second subtraction means for providing an autobalance output from which stationary pattern noise has been removed based on the subtraction.