JPS6042515B2 - correlator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a correlator as illustrated in FIG. 9, which is used, for example, in a ghost removal device, and is effective for integration and reduction in the number of elements.

Devices have been developed to eliminate ghosts in television signals, and the use of correlators has been proposed. An object of the present invention is to provide a correlator that is suitable for small-sized integrated circuits and is useful for reducing the number of elements.

Examples of the present invention will be described below.

FIG. 1 shows an example of a ghost removal device used, for example, in a television receiver.

1 is a video signal input end, and 2 is a video signal output end.

The video signal input from the input terminal 1 undergoes ghost cancellation in the transpersal filter Al, and the video signal is sent to the output terminal 2.
is derived. The transpersal filter Al has a function of eliminating ghosts by adding ghosts of opposite polarity to a video signal containing ghosts.
(This will be explained in detail in FIG. 2.) In order to eliminate ghosts, it is necessary to know the phase difference between the ghost and the normal video signal and the amplitude of the ghost.

The output video signal of transversal filter A1 is input to subtractor A2. This differentiator A2 has a function of differentiating the video signal. The output of this differentiator A2 is applied to one input terminal of a comparator A3 and compared with a reference level. Output 00r1 of comparator A3 is input to buffer register A4. Here, the buffer register A4 introduces and stores the output of the comparator A3 for a predetermined period from the leading edge of the vertical synchronizing signal. The data stored in the buffer register A4 is read out cyclically within the vertical synchronization signal period and applied to one input terminal of the correlator A7. The output of the digital difference device A6 is input to the other input terminal of the correlator A7.

The video signal is input to a waveform integrator A5, where the leading edge portion of the vertical synchronization signal is waveform integrated and its digital data is stored within this waveform integrator A5. The digital data of this waveform integrator A5 is stored in the buffer register A.
In synchronization with the timing of the read data of No. 4, the difference device A
6 to the correlator A7. The correlator A7 is
It has the function of detecting the noise signal, and the buffer register A
The output of the digital difference device A6 is cumulatively added according to the output of the digital difference device A6.

Then, the polarity of the cumulatively added result is determined, 0 or 1 is outputted, and the output is inputted to the tap gain memory unit A8. The tap gain memory section A8 has a storage section corresponding to a plurality of taps of the transversal filter A1.

The data in each storage section is incremented by -1 or +1 depending on the output 0 or 1 of the correlator A7. Data in each storage section of the tap gain memory section A8 is input to the corresponding weighted voltage memory section (included in the transversal filter A1) via a digital-to-analog converter (hereinafter referred to as a D/A converter) A9. At this time, polarity data for identifying data for removing positive polarity ghosts and data for removing negative polarity ghosts is also read from the tap gain memory unit A8, and is sent to the control terminal of transversal filter A1. Added. The input video signal is also input to the timing pulse generator AlO, and a synchronization signal separation process is performed.

This timing pulse generator AlO is provided with various circuits for generating each driving pulse and timing pulse of the system. FIG. 2 specifically shows the transversal filter A1. Bl is a tapped analog delay line using, for example, a charge-coupled device CCD. This tapped delay line B1 has j stages of delay elements 101 to 10j. First and second weighting circuits are connected to the taps of each delay element. B2 is a weighting circuit group, B3 is a weighted voltage memory group, B4 is a tap selection switch group, B5 is a weighted voltage input switch group, B6 is a shift register,
Controls tap selection switch group B4. Delay element 10j
I will explain this on behalf of the lineage.

The output terminals of the first and second weighting circuits 11j, 11j'' are connected to the taps of the delay element 10j.The input terminals of each one of the first and second weighting circuits 11j, 11j'' are connected to a video signal. The input terminal 1 is connected, and the output terminals of the first and second weighted voltage memories 12j, 12j'' are connected to the other input terminals.The first and second weighted voltage memories 12j, 12j
At the input end of ``, there are first and second tap selection switches 13.
The output terminals of the first and second tap selection switches 13j and 13j'' are connected to each other.The first and second tap selection switches 13j and 13j'' select one of the systems by the output of the transfer pulse from the j-th stage of the j-bit shift register B6. is turned on. The output terminals of the first and second weighted voltage input switches 14j and 14j'' are connected to the input terminals of the first and second tap selection switches 13j and 13j''. These first and second weighted voltage input switches 14j
, 14', the output of the D/A converter A9 is applied to the input terminal B9 of the D/A converter A9. Also, the control end of the first weighted voltage input switch 14j and the second weighted voltage input switch 14'
The polarity data is applied from the tap gain memory unit A8 to the control terminal of the first group of weighted voltage switches. is applied to the control end of the group of weighted voltage switches via an inverter B8.Another delay element 10
The systems 2 to 10j are configured similarly, and the input terminal 1
, B9, and B10 are common. In the above transversal filter A1, the time axis position of the ghost with respect to the original video signal is determined by the delay elements 101+x to 10j (
(horizontal direction on the drawing), and the size of the ghost is
Weighted voltage corresponds to the voltage of the memory.

The output of analog delay line B1 is output via amplifier B7. FIG. 3 shows a subtractor A2, a comparator A3, and a buffer register A4. The subtractor A2 obtains a differentiated output of the video signal. This differential output is compared with a reference voltage in comparator A3. Comparator A
The output 0 or 1 of 3 is stored in the buffer register A4 for a predetermined period from the leading edge of the vertical synchronization signal. This stored data is ghost information for a predetermined period from the leading edge of the vertical synchronization signal. The data read into the buffer register A4 is then sequentially read out and input into the correlator A7. FIG. 4 specifically shows the waveform integrator A5.

A video signal from video signal input terminal 1 is input to one input terminal of comparator C1. This comparator C
The other input terminal of the waveform integration memory C4 receives data from each storage section of the waveform integration memory C4 via a digital-to-analog converter C5. The output 0 or 1 of comparator C1 is stored in buffer memory C2. The output of the buffer memory C2 is input to the arithmetic unit C3. This arithmetic unit C3 performs an arithmetic operation of -1 or +1 on the data in each storage section of the waveform integral memory C4 in accordance with the output of the buffer memory C2. The calculation result of the calculation unit C3 is stored again in the waveform integral memory C4. The output of the waveform integration memory C4 is differentiated by a differentiator A6 and input to a correlator A7. In the waveform integrator A5, the leading edge of the synchronizing signal is digitally converted and stored for each vertical synchronizing signal.

Therefore, the converged digital data of the leading edge of the vertical synchronization signal is stored at the address of the waveform integral memory C4. FIG. 5 shows correlator A7. In this correlator A7, the reference signal from the subtractor A6 and the buffer . A correlation signal with the ghost information from the register A4 is obtained, and its output 0 or 1 is input to the tap gain memory section A8. The data in each storage section of the waveform integrator A5 is sequentially differentiated from the output data of the buffer register A4 via a differentiator A6, and is input to the polarity control circuit D1 and multiplied. Then, the multiplication results corresponding to each storage section are accumulated in an accumulator D2. In the accumulator D2, a negative or positive output is obtained as a result of the accumulation, and this is determined as 0 or 1 in the polarity determination circuit D3. This cumulative result is obtained the same number of times as the number of taps of the tapped delay line B1.

The output 0 or 1 of the polarity determination circuit D3 is sequentially output in correspondence with the taps of the tapped delay line B1, and serves as information on increases and decreases in the data in each storage unit (included in the tapgay memory unit A8) corresponding to this tap. .

Further, the output 0" or 1 of the polarity determination circuit D3 indicates a ghost of negative polarity or positive polarity. FIG. 6 shows the tap gain memory section A8.

The output 0 or 1 of the correlator A7 is input to the arithmetic unit E1. The arithmetic unit E1 performs a calculation of -1 or +1 on the data in each storage section of the tap gain memory section E2, depending on the correlation output. Assuming that the number of taps is j, the storage section of the tap gain memory E2 has j areas, and 'bit data is formed for one area. The data in each area of the tap gain memory E2 also includes polarity data to identify whether it represents positive or negative ghost data.

In FIG. 7, the input video signal showing the timing pulse generator AlO is input to the system clock generator F1 and the synchronization separation circuit F2.

The system clock generator F1 generates stable clock pulses, and the synchronization separation circuit F2 separates horizontal synchronization signals and vertical synchronization signals. The horizontal synchronization signal is input to the synchronization circuit F4 via the self-frequency control circuit F3. The synchronization circuit F4 outputs the pulse output timing of the horizontal timing pulse generation circuit F5 in synchronization with the horizontal synchronization signal. Further, the horizontal timing pulse generation circuit F5 can also generate pulses with twice the horizontal frequency by using the output of the system clock generator F1, and includes a counter and a ROM.

The vertical synchronization signal separated by the synchronization separation circuit F2 is input to the synchronization circuit F6. This synchronization circuit F6 synchronizes with the vertical synchronization signal to generate a vertical timing pulse generation circuit F7.
control. This vertical timing pulse generation circuit F7 operates at the leading edge of the vertical synchronizing signal or for a predetermined period from the leading edge of the vertical synchronizing signal.
Control 5. As described above, in this ghost removal device, the data in each storage section of the tap gain memory section A8 is converted into analog data by the analog-to-digital converter A9, and the converted data is stored in the corresponding weighted voltage memory.

In the weighted voltage memory, voltage 1 is rewritten every horizontal synchronization. As a result, the transfer characteristic of the transversal filter A1 for one horizontal period is set, and a video signal with ghosts eliminated is output from the video signal output terminal 2.
Furthermore, if ghosts still remain in the video signal output from transversal filter A1,
This ghost is detected during the vertical synchronization signal period.

If ghost information is detected, the data in each storage section of the tap gain memory section A8 will be corrected during the vertical synchronization signal period, as described above. Tap gain memory section A
Modifying the data in each of the 8 storage units means the following.

The sample value of the differentiator A6 is Xi (1=1, 2,...)
, the output of the transversal filter A1 is differentiated and the sample value stored in the buffer register A4 is y1, then the output DK of the correlator A7 (K=1, 2,...j)
, where K is the tap number of the transversal filter, m is the number to be cumulatively added, and Sgn is a symbol indicating the sign of the value in parentheses.

Now, let the Kth storage part data of the tap gain be C,
Furthermore, the CK after the Nth correction is C? Then N+1
The second tap gain C-1 is given by a as an appropriate normal number.
I will make a hail.

When the ghost is eliminated and Y becomes zero, da also becomes zero, and at that point the tap gain CK settles into a steady state.

By the way, the above-mentioned waveform integrator A5 and digital difference device A
6. A configuration as shown in FIG. 8 has been considered as the configuration of the correlator A7.

That is, the waveform integration memory C4 stores the leading edge portion (hereinafter referred to as a reference signal) of the digitized vertical synchronization signal.

The accuracy of digitizing this waveform integral memory C4 is n
If the interval corresponding to the time axis of the bit and reference signal is m bits, then this waveform integral memory C4 has a storage capacity of (n×m) bits. DO the digital value of each section
, Dl, D2...Dm-1. 11 is an n-bit latch circuit, 12 is a group of n inverters, and 13 is an n-bit full adder.

These latch circuit 11, inverter group 12, and full adder 13 can perform difference calculations on reference signals. That is, X shown in equation (1) can be calculated and derived. X,=DO-o-Di (1=1, 2,...m). Therefore, DO-1) is the n-bit latch circuit 1
It is temporarily held at 1. D, read out from the waveform integral memory C4 is converted into one's complement by the inverter group 12, and then added to the full adder 13. In the full adder 13, the complements of DO-1) and D are added together and added to +1 to obtain .

The output X1 of the full adder 13 is input to an exclusive OR circuit group 14. The exclusive OR circuit group 14 also includes the output of a buffer register A4 holding the differential signal of the output of the transversal filter A1. The exclusive OR output obtained from the exclusive OR circuit group 14 is input to the full adder 15. In this full adder 15, each time an output is obtained from the exclusive OR circuit group 14, the previous data is temporarily held in the latch circuit 16.
6 and the output of exclusive OR circuit group 14 are added. In other words, it is a cumulative addition. The full adder 15 also holds polarity data of 0 or 1 output from the buffer register A4. in this way,
The exclusive OR circuit group 1, full adder 15, latch circuit 16, etc., is calculated by formula (1) 1, that is, DK=. Tx,S
grl(Yi+K) 1-y correlation calculation will be performed.

XKsgrl(y1+K) in equation (1) is Sgn(y1
+K) is only O or 1, so it is replaced with Xi or -X1 and Sue. L-Jko TrA- Upper base Y. Sσ
This is equivalent to adding and subtracting and accumulating n(V.l)l dimension Y2.

In this way, in the exclusive OR circuit group 14, if Sgn(Yi+K) is 1, X is inverted (ie, 1's complement), and if it is 0, it is derived as is. Then, the full adder 15 adds and subtracts and accumulates, and the result is derived as a correlation calculation output. According to the above-described correlator of FIG. 8, an element with a fast memory response operation (that is, a fast write time) is required as the waveform integration memory circuit C4.

Furthermore, an n-bit latch circuit 11 is always required to perform a differential calculation. In addition, in advance, the latch circuit 11,
In step 12, elements to be differentiated are prepared and the settings are input to the full adder 13. The result of the difference in the full adder 13 is processed in the exclusive OR circuit group 14 based on the value of Sgn(Yi+K), and then cumulatively added in the full adder 15. For this reason,
The circuit configuration is complicated, and the control timing is also complicated.
Therefore, in the present invention, the correlator is configured as follows. In FIG. 9, 21 and 22 are waveform integration memories included in the waveform integrator A5.

The storage capacity of each waveform integral memory 21, 22 is NxW bits. Here, n is the number of bits in the amplitude direction when the reference signal is digitized, and m is the number of segments when the reference signal is segmented in the time axis direction. D the digital value of each category. , Dl, D2...Dm-,. The waveform integral memory 21 stores digital values D of even number divisions. ,D2,D
4...Dm-2 is performed. In addition, the waveform integral memory 22
, digital values Dl, D3, D5...D of odd number division
．． -1 is stored. With this setting, the response time of the memory element of each waveform integral memory 21, 22 can be twice as long as the response time of the element when one waveform integral memory is used. Become. In other words, by using a two-phase memory, it is possible to use a memory element with a slow response speed. Therefore, the write and read frequencies applied to each waveform integral memory 21 and 22 are lower than the write and read frequencies applied to the waveform integral memory C4 in FIG. The respective outputs of the waveform integration memories 24 and 22 are input to exclusive OR circuit groups 23 and 24, respectively.

The outputs of the exclusive OR circuit groups 23 and 24 are input to the full adder 25. In the full adder 25, the outputs of the exclusive OR circuit groups 23 and 24 are matched and added. The output of this full adder 25 is further input to a full adder 26. In this full adder 26, every time an output is obtained from the full adder 25, the data held until now is temporarily held in the latch circuit 27,
The output of this latch circuit 27 and the output of full adder ζ-25 are added. In other words, it is cumulatively added. The exclusive OR circuit groups 23 and 24 each receive an output from the difference calculation control circuit 28.

This difference calculation control circuit 28 is supplied with the output of the buffer register A4 that holds the differential signal of the output of the transversal filter A1, that is, Sgrl (Yi+K), and the frequency of the read pulse applied to the waveform integral memories 21 and 22. A timing signal SW of twice the frequency is added. The outputs of the difference calculation control circuit 28 are inverted in phase with each other. The specific difference calculation control circuit 28 is constituted by an exclusive OR circuit 30, an inverter 31, etc., as shown in FIG. The direct output of the exclusive OR circuit 30 is input to the exclusive OR circuit group 23, and the output after passing through the inverter 31 is input to the exclusive OR circuit group 24. FIG. 11 is a time chart shown to explain the calculation operation of the above-mentioned correlator.

Focusing on equation (1), we get There is.

It is.

This means that the difference operation (4)i-1-D,) can be changed to Sgn(
Sgn(Yi+K) without performing cumulative addition while switching addition and subtraction signs from i=1 to m.
When is 1, (D, -1-D,), Sgn(Yi+K)
When is -1, it means that even if the order of the elements is changed and cumulative addition is performed, the result is the same as (Dl-D,-1).

The address change point when reading data from the differential memory 21 is 2n1t0 (m=0, 1, 2...) Waveform integral memory 2
Address change point when reading data in 2 (2m1+1)
Let TO (m=0, 1, 2...).

In other words, Figure 11a shows the time axis, Figure 11b shows address changes when reading data from the waveform integral memory 21, and Figure 11c shows address changes when reading data from the waveform integral memory 22. . As a result, from the waveform integral memory 21, Dm2=DO, D2, D4, . . . D in a period of 2rr1t0 to 2(m+1). -2 data is read. Also, from the waveform integral memory 22, (2
D during the period from n1+1)TO to ((2m+1)+1)TO
(2m+1)0D1? Data of D39D59 is read. The output data of the waveform integral memories 21 and 22 is the first
It will appear as shown in 1e and f. On the other hand, Sgrl(Y
i+K) is set to be input during the period from (m+1)TO to (m+2)TO.

(Fig. 11g) Furthermore, the timing signal SW is set as a signal in which 0 and 1 are alternately repeated for each calculation reference time (Fig. 11d). The above timing signals SW and Sgn (
Yi+K) is input to the exclusive OR circuit 30.

As a result, the correlation element is simultaneously added to the difference calculation. Normal difference operation X, =Di-D,
-1, when the timing signal SW is 1, DO
-Dl, D2-D3, D4-D5..., (subtract the contents of the waveform integral memory 22 from the contents of the waveform integral memory 21)
, when the timing signal SW is O, D1-D2, D3-D
4, D5-D6... (subtracting the contents of the waveform integral memory 21 from the contents of the waveform integral memory 22).

However, according to this correlator, the correlation element Sgn(Yi+K) is simultaneously input when performing the difference calculation.

Therefore, when Sgrl(Yi+K) is positive (digital value 0), the calculation is performed according to the timing signal SW, and when Sgn(Yi+K) is negative (digital value 1) obtains the arithmetic operation by inverting the timing signal SW. This operation is obtained by the configuration of the exclusive OR circuit group 23, the two-way difference calculation control circuit 28, and the full adder 25.The correlation signal can be obtained by cumulatively adding the outputs of the full adder 25 in the full adder 26. According to the above-mentioned correlator shown in FIG. 9, first of all, the write time to the waveform integral memory that stores the digital value of the reference signal is twice that of the correlator shown in FIG. 8, and the control circuit can be simplified. .

Moreover, the elements used for the waveform integral memory can be inexpensive and low-speed. Furthermore, since the configuration of the exclusive OR circuit groups 23, 24 and the full adder 25 adds a correlation element to perform the difference calculation, the exclusive OR circuit group 14 required in the correlator of FIG. is unnecessary, the overall configuration is simplified, and it is effective in reducing the number of elements, integrating circuits, and increasing the degree of freedom in design. As described above, the present invention provides a correlator that is small, suitable for integration into an integrated circuit, and useful for reducing the number of elements.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing a ghost removal device for a television receiver, FIG. 2 is a diagram showing an example configuration of the transversal filter in FIG. 1, and FIG. 3 is a diagram showing a configuration example of the transversal filter in FIG. 1. , FIG. 4 is a diagram showing an example of the configuration of the waveform integrator in FIG. 1, FIG. 5 is a diagram showing an example of the configuration of the correlator in FIG. 1, and FIG. 1, FIG. 7 is a diagram showing an example of the configuration of the timing pulse generator of FIG. 1, FIG. 8 is a diagram showing an example of the configuration of the correlator used in the present invention, FIG. 9 is a configuration explanatory diagram showing a correlator according to an embodiment of the present invention, FIG. 10 is a diagram showing the difference calculation control circuit of FIG. 9, and FIG.
Figures a to g are time charts shown to explain the operation of the correlator in Figure 9. A7... Correlator, 21, 22... Waveform integral memory, 23, 24... Exclusive OR circuit group, 25, 26... Full adder, 27・
...Latch circuit, 28...Difference calculation control circuit.

Claims (1)

[Claims] 1 Divide the reference signal that arrives periodically in the time axis direction, and calculate the amplitude of the reference signal in each section by n bits (
n is a positive integer), the digital data of every other division in the time axis direction is stored in the first waveform integral memory, and the digital data of other divisions is stored in the second waveform integral memory. It consists of means for storing in a memory, and first and second groups of exclusive OR circuits into which digital data for each section of the first and second waveform integral memories is introduced in parallel, each group being means for inputting the digital data in parallel to one input terminal of each exclusive OR circuit, and a signal that requires correlation with the reference signal; is converted into 0 or 1 data in the time axis direction and inputted to one input terminal, and a timing signal of a constant period is inputted to the other input terminal. The first inversion of the output of the circuit
a correlation calculation control circuit for deriving a control signal and a non-inverted second control signal, and each of the exclusive OR circuits in one group of the first and second exclusive OR circuit groups means for inputting the first control signal in common to the other input terminal, and inputting the second control signal in common to the other input terminals of each exclusive OR circuit of the other group; 1. Correlation comprising a first full adder that adds the output data of the second exclusive OR circuit group in half cycles of the timing signal, and a second full adder that cumulatively adds the outputs of the first full adder. vessel.