JPS61199300A - Semiconductor memory evaluating device - Google Patents

Abstract

PURPOSE:To evaluate a semiconductor memory by counting the number of defective bits at every word line, and comparing the number of counts with preset allowable limit value. CONSTITUTION:Addresses of a line and column are shown by i, j, respectively and the address of a memory cell is shown by (i, j). Cells up to (M-1, N-1) address are written successively in a total memory cell, such as from cell (0, 0) to (0, N-1), from (1, 0) to (1, N-1). Data are read out from (0, 0) cell, and compared with expected value data by a comparator. When the coincidence of data is obtained, column address is increased, and advanced to (M-1, N-1) address, and when there is not discordance, it is judged as an acceptable product and the evaluation is completed. If the discordance occurs on the ray, the counter 11 is increased, and the content of the counter 11 is compared with a set value by a comparator 12 at every N-1 address of column address, and when the set value is exceeded, a Fail signal is generated and the evaluation is terminated. Thus, the number of defective bits can be checked at every word line.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor memory evaluation device.

(Prior Art) IC memories have become denser and faster in recent years, and memories with strong custom elements are being developed in parallel with conventional general-purpose RAMs. An example of such is memory reserved for video still images.

For still images of video, a method was adopted in which the tape was paused and the video signal was repeatedly obtained by rotating the tape at the same position on the VTR.

However, compared to this method, an electronic method using an IC memory can be used which is superior in terms of cost and reliability. This electronic still image creation system is shown in FIG. 3. Composite and topideo signals from a VTR tape head are input to an A/D converter 1 and converted into digital signals. The sampling frequency during conversion is the sampling ratio IMK
In fact, it is required to be twice or more, and the larger this ratio is, the higher the coincidence rate of the reproduced output signal with the input signal becomes. For example, the two major color broadcasting systems, NTSC and PAL, each have a frequency of 3.58MHz.

Since it is 4.43 MHz, if the sampling ratio is tripled, the sampling frequency becomes 100 NS, and the input signal is carved every 100 N8 and subjected to A/D conversion. The converted digital signal is continuously stored in the video memory 2. Since the video memory 2 has a capacity sufficient to store video information for one screen, once the screen information is stored, the same image can be played back many times thereafter.

By repeatedly and sequentially accessing the addresses of the video memory 2, the same video signal is always supplied to the video memory 2. The D/A converter 3 converts this signal back into an analog signal, thereby reproducing the video signal and reproducing a still image on the screen. In addition, controller 4
generates a control clock for the VTR head.

A diagram of such a video memory 2 is shown in the fourth color. A memory cell array 5 that is a collection of storage elements, a row address buffer 76 that determines the address of the storage element in the row direction, a row decoder 7, and a column address buffer 8 that determines the address in the column direction.
, a column decoder 9, and a block (not shown) that controls writing and reading. When using the video memory 2 shown in FIG. 4 in the electronic still image creation system shown in FIG. The design is made to accommodate the numbers.

Generally speaking, human vision cannot immediately detect a defect in the image quality of just a few dots on the screen. From a video memory standpoint, this means that it is possible to use even a few bits defective, rather than selecting and using only good bits as in conventional general-purpose RAM.

Conventionally, IC testers have been used to evaluate memory, and with the recent improvements in memory performance, the performance of IC testers has improved considerably, but this video memory evaluation Kti
A so-called bit map memory, which stores information on whether each memory bit is good or bad, is required.

The information stored in the map memory is judged to determine whether the product is good or defective.

(Problems to be Solved by the Invention) In the memory evaluation method using bit map memory as described above, the bit map memory is highly dependent on the degree of integration of the video memory to be evaluated, and the The problem is that the capacity must be increased to keep up with the increase in density.

Therefore, the present invention provides a semiconductor mesh evaluation device that reduces costs without adding a large amount of bit map memory.

(Means for Solving the Problems) The device of the present invention provides at least one row or column of memory cells read from a semiconductor memory having a memory cell configuration of M rows and N columns (M and N are natural numbers). a first comparison means that compares the data and the expected value of the memory cell data for each of the memory cell data and generates a mismatch signal when there is a mismatch; a counting means that is reset for each at least one row or column that has been counted, and a second comparing means that compares the counted value of the counting means with a predetermined value and generates a match signal when they match. configured.

(Example) Hereinafter, an example of the present invention will be described with reference to FIG. (2).

The video memory mentioned above will be taken as an example of the semiconductor memory to be evaluated. Since the row address and column address of this video memory correspond to the horizontal line position of the TV screen and the sampling number of A/D conversion, respectively, most of the N memory cells hanging from the word line selected by the row address are defective. If this is the case, one scanning line on the screen will not be displayed, resulting in a fatal defect. Therefore, every word line <7F
If the evaluation sample is good, the evaluation sample is determined to be defective if the number of counters exceeds a value set in advance as an allowable limit.

A block diagram of essential parts of an embodiment of the present invention is shown in FIG.
The evaluation flowchart is shown in FIG.

Figure 1 shows the main circuit features that should be added to conventional evaluation equipment.

The main parts of the semiconductor memory evaluation device shown in FIG.
Counter 1 that counts the number of times a signal is generated from
1. It is composed of a comparator 12 that compares the numerical value recorded on the counter IIK with the set value of the allowable limit for the number of defective pits.

The evaluation operation shown in FIG. 1 will be explained with reference to FIG.・Second
In the figure, the partial flow separated by dashed lines and marked with ■ is the flow for writing initial data that becomes the expected value in the evaluation memory, and ■
The partial flow shown in is the evaluation memory 1 using the circuit shown in Figure 1.
Bad bits per word line.

This is a flow for checking and comparing counts. Let the row and column addresses be ttJ, and the address of a certain memory cell be ('$
j) is shown in FIG. 4, and the 9MxN memories 7 contain (0,0), (0,1), . . . -.

(0, N-1), (1, O), ......, (1
, N-1), . . . , (M-1, N-1).

First, in partial flow ■, from cell (0,0) to (0,N-1)
Then, sequentially from (1, 0) to (1, N-1) (M-1
Initial data is loaded into all memory cells up to the cell at address ゜N-1). Then, it enters the partial flow ① and reads out the data written in from the cell at (0°0) to the comparator 10.
Compare with expected value data. If the data match, proceed to the YES flow, increment the column address, and proceed to address (M-1, N-1). If there is no mismatch, pa
An ss signal is generated, the product is determined to be non-defective, and the evaluation ends. If a mismatch occurs on the way, proceed to NO flow and counter 1
1 is incremented, and the comparator 12 always compares the contents of the counter 11 with the set value every column address up to address N-1. If the set value is exceeded, Fai is immediately
The evaluation ends by generating a t signal. The counter 11 is cleared every time a row changes.

In this manner, by using this embodiment, it is possible to check the number of defective bits for one word line and determine whether it is a good product or a defective product.

In this embodiment, a case has been described in which a pass/fail judgment is made for each row, but it is clear that the present invention is not limited to this, but can also be applied to a case where a pass/fail judgment is made for each column.

(Effects of the Invention) The present invention allows defective bits to be checked for each row or column address and by varying the number of addresses to be looked at, and also minimizes the cost without adding a large amount of memory for bit map. This has the effect of allowing evaluation to be carried out.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a main part of an embodiment of the present invention, FIG. 2 is a flowchart showing the evaluation operation of a semiconductor memory by the device shown in FIG. 1, and FIG. 3 is an electronic still image creation system using a semiconductor memory. professional. FIG. 4 is a block diagram of a semiconductor memory. 1...A/D converter, 2...Video memory, 3...D/A converter, 4...Controller, 5... ...Memory cell array, 6...
...Row address buffer, 7...Row decoder, 8...Column address buffer, 9...
・Column decoder, 10.12... Comparator, 11.
·····counter. ζn1, Agent Patent Attorney Susumu Uchihara i'i', ”: Engineering, 0te...'

Claims (1)

[Claims] Memory cell data in at least one row or column read from a semiconductor memory having a memory cell configuration of M rows and N columns (M and N are natural numbers) and an expected value of the memory cell data. a first comparison means that compares each of the memory cell data and generates a mismatch signal when there is a mismatch; and a first comparing means that receives the mismatch signal and counts the number of times the mismatch signal is supplied, and resets each of the at least one read row or column. 1. A semiconductor memory evaluation device comprising: a counting means for comparing the counted value of the counting means with a predetermined value and generating a match signal when the counted value of the counting means matches a predetermined value.