JPS61198818A - Preset type synchronous programmable counter - Google Patents

Abstract

PURPOSE:To attain double high speed operation by providing a frequency divider frequency-dividing a basic clock into 1/2, a preset type synchronous programmble counter, a means inputting a clock thereto and a means retarding the frequency division operation of the first frequency divider by one period's share of the basic clock. CONSTITUTION:When the frequency division ratio is an add number, a frequency division control signal DC fed to an input terminal 103 is set to logical H. A frequency division ratio setting signal DET fed to an input terminal 101 is set to a value of (frequency division ratio - 5). Suppose that the frequency division ratio is an odd number '131', the frequency division ratio set signal DET is '126'. In this case, when a counter 2 counts '126', that is, a PSPC 112 (counter 1) counts '63', the DET pulse having a width of one period of the frequency division clock DCLK synchronously with the trailing of the basic clock FCLK is fed to the input terminal 101.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides a preset type synchronous programmable counter, more specifically, a preset type synchronous programmable counter, which has twice the delay time of the conventional one without using basic elements with small delay times. This invention relates to a preset type synchronous programmable counter capable of high-speed operation.

[Conventional technology]

A preset type synchronous counter that generates an output when the count value of the input clock reaches a preset value takes advantage of this property and uses a frequency divider or means to generate a control signal when the count value reaches a predetermined count value. It is widely used. Among these preset type synchronous counters, one in which the preset value can be arbitrarily set by a control signal is called a preset type synchronous programmable counter.

FIG. 3 shows a conventional preset type synchronous programmable counter, which is used as a frequency divider.

In FIG. 3(A), reference numeral 300 is a preset type % type % (PC) having a configuration having P stages of counter stages (3031 to 303p). 301 is a frequency division ratio setting signal (DE
This frequency division ratio setting signal DET is generated at the input terminal of T) when the set frequency division ratio matches the value (count number of PSPC 300 - 1). 302 is a clock input terminal to which an input clock is applied, and 304 is an output terminal to which a frequency-divided output is sent.

Each stage constituting the PSPC300 is shown in Figure 3 (B
It has the same configuration as the counter stage 303 shown in )°.

In the counter stage 303, 305 is a previous stage detection circuit;
Each counter stage in the previous stage outputs a detection signal when it is detected that the previous stage is at a high level “H”.
is applied to one input terminal of 6. EX-NOR circuit 3
The output of 06 is applied to the NOR circuit 307 together with the DET signal input to the terminal 301. The output of the NOR circuit 307 is applied to the input terminal of a D-type flip-flop (DFF) 308. An input clock is applied to the clock terminal C of this D-FF 308, and the output of the counter stage 303 generated from the output terminal Q is output to the EX-NOR 30.
6 other input terminals.

Next, the operation of FIG. 3 will be explained with reference to the time chart of FIG. 4, taking as an example the case where the input clock is divided into 1/n.

When dividing the frequency by 1/n, the DET signals other than the n-th counter stage are at a low level "L", but the frequency division ratio setting signal DET applied to the n-th counter stage is
When the count value of the PSPC 300 reaches (n-1), a DET pulse having a width of one cycle of the input clock is generated and applied to the NOR circuit 307, as shown in FIG.

Therefore, when the input clock is applied to each counter stage,
The outputs of the first counter stage 3031, that is, D-F
The output of F308 goes to "H" level.

When the count value is (n-1), that is, when all the outputs of the counter stages up to the (n-1) stage become "H", the previous stage detection circuit 305 in the n-th stage counter generates a detection signal. As a result, the output of the EX-NOR 306 becomes "L". During the period when the count value becomes (n-1) and no DET pulse is applied yet, the output of the NOR circuit 306 and the frequency division ratio setting signal DET are both "L". Therefore, “H” is applied to the input terminal of the D-FF 308. Therefore, the front stage detection circuit 30
5 generates a detection signal and when the count value reaches (n-1), the output of the D-FF 308 becomes H'' as shown in FIG. 4(C).

Subsequently, when a DET pulse is applied to the n-stage counter stage as shown in FIG.
” is added.

In this state, the input clock (n) for the count value n
When input, the output of D-FF308 becomes “
It changes from H″ to L″. By resetting each counter stage at this falling edge, the input clock can be divided into 1/H.

[Problem that the invention seeks to solve]

In the conventional PSPC, its maximum operating frequency is determined by the delay time of each circuit, that is, the pre-stage matching circuit 305, the EX-NOR circuit 306, the NOR circuit 307, and the D.FF 308. Therefore, in order to increase the maximum operating frequency, it is necessary to increase the delay and
It is necessary to reduce the delay time of each pixel by using circuit elements with time or by increasing the power supply voltage.

However, in the former method, it is difficult to design a circuit element with extremely small delay time, and even if it is obtained, it is expensive. In the latter case, there is a problem that a special high voltage source is required and that the maximum operating frequency cannot be significantly improved due to the allowable voltage and allowable loss characteristics of each circuit element.

The present invention was made in order to eliminate the above-mentioned problems in conventional PSPCs, and does not require circuit elements with smaller delay times than conventional ones or higher operating power supplies than conventional ones, and is different from conventional PSPCs. p that can operate twice as fast as conventional PSPC using the same circuit elements and operating power supply.
The purpose is to provide spc.

[Means for solving problems]

In order to solve the above-mentioned problems in the conventional PSPC and achieve the above-mentioned object, the present invention provides a preset type synchronous programmable counter that generates an output by dividing a basic clock according to a frequency division ratio setting signal. A frequency divider that divides the basic clock into 1/2,
(bl) A preset type synchronous programmable system that inputs the divided clock output from the frequency divider and generates an output by dividing this divided clock according to the division start signal corresponding to the division ratio setting signal. (c) Based on a division ratio setting signal set corresponding to a desired division ratio with respect to the basic clock frequency, count the wave number between divided clocks that is closest to 1/2 of the division ratio.
(d) means for generating a frequency-divided start signal having a width that includes a time point at which the count-up is performed, but excludes at least a previous count-up time point, and inputting the signal to the preset type synchronous programmable counter; Only when the frequency ratio is an odd number with respect to the basic clock frequency, the frequency dividing operation of the first frequency divider when the frequency division start signal is input to the preset synchronous programmable counter is divided into one period of the basic clock. In this embodiment, a means for delaying the time is provided.

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an explanatory diagram of an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of the embodiment. Note that this embodiment is an embodiment in which a PSPC is used as a frequency dividing device.

In FIG. 1, 101 is an input terminal for a frequency division ratio setting signal DET, and 102 is an input terminal for a basic clock (OCLK). 103 is an input terminal for the frequency division control signal (DO8), and the frequency division control signal DOS is "L" when the frequency division ratio is an even number.
When the frequency division ratio is an odd number, the signal becomes "H" level.

104 is a frequency divider, which is a D-type flip-flop (D-FF
), the basic clock FCLK is applied to the clock terminal C, and the input terminal and the inverted output terminal 0 are connected.

As a result, an output obtained by dividing the basic clock FCLK into 1/2 is generated at the inverting output terminal 0.

105 to 108 are D-FFs, the input terminal of the D-FF 105 receives a frequency division ratio setting signal DET, and the clock terminal C receives a frequency division clock (DCL) obtained by inverting the frequency divider 104 with an inverter 109. K) is added. D-FF1
The output of the D.FF 105 is applied to the input terminal of 06, and the basic clock FCLK is applied to the clock terminal C. D-
The output of the D-FF 106 is applied to the input terminal of the FF 107, and the clock obtained by inverting the basic clock FCLK by an inverter 110 is applied to the clock terminal C. D・FF
The output of the D-FF 107 is applied to the input terminal 108, and a clock obtained by inverting the basic clock is applied to the clock terminal C. Note that the output of the D-FFIO 7 is used as a frequency division activation signal (DSS) of the PSPC, which will be described next.

111 is a NAND circuit, and its three input sides are D-F.
F107 (7) output, D-FF10817) inverted output and frequency division control signal DC3 are applied, and the output terminal thereof is connected to reset terminal R of frequency divider 104.

112 is a PSPC, which has the same configuration as the PSPC shown in FIG. A frequency-divided clock DCLK generated by a frequency divider 104 and an inverter 109 is applied to the clock terminal CLK, and a P
Frequency division start signal D corresponding to the frequency division ratio setting signal of SF'C112
SS is added by the output of D-FF107.

Note that the same power supply as that used in the conventional PSPC is used as the operating power supply for each of these circuits.

Next, the operation shown in FIG. 1 will be explained with reference to the time chart shown in FIG.

In Figure 2, (A) shows that the frequency division ratio is the basic clock FCL.
A time chart in the case where the frequency of K is an odd number is shown, and (B) shows a time chart in the case where the frequency division ratio is an even number with respect to the frequency of the basic clock FCLK. Further, "Counter 1" indicates the counting operation of the PSPCI 12, and "Counter 2" indicates the counting operation when it is assumed that the PSPCI 12 operates with the basic clock CLK.

The operation shown in FIG. 1 will be explained below separately for the case where the frequency division ratio is an odd number and the case where the frequency division ratio is an even number.

(1) Operation when the frequency division ratio is an odd number When the frequency division ratio is an odd number, the frequency division control signal DO3 applied to the input terminal 103 is set to "H". Further, the frequency division ratio setting signal DET applied to the input terminal 101 is set to a value of (frequency division ratio - 5). rl whose frequency division ratio is odd now
31J, the division ratio setting signal DET is "1".
26".

In this case, when the counter 2 counts r126J, that is, when the PSPC 112 (counter 1) counts "63", it is synchronized with the falling edge of the basic clock FCLK, as shown in (C) of FIG. 2 (A). frequency-divided clock DCLK
The configuration is such that a DET pulse having a width of one cycle is applied to the input terminal 101.

In this configuration, the basic clock FCLK is input to input terminal 1.
02 (FIG. 2(A)(a)), the frequency divider 104
And the inverter 109 converts the basic clock FCLK by 1/
2 ((b) in FIG. 2(A)), the D-FF 105 and PSPCI 1
2 to each clock terminal.

The basic clock FCLK is applied to the clock terminal C of the D-FF 106, and is further inverted by the inverter 110.
- Also added to FF107 and FF108.

While the DET pulse is not applied, the frequency divider 104 continues to generate the divided clock DCLK, and the D-FF1
05 to 107 maintain the L” output state, and D-FF108
maintains the "H" output state.

Therefore, the PSPCI 12 performs a count-up operation similar to that shown in FIG. 3 every time the divided clock DCLK is input.

The count value of PSPC112 (counter 1) is [63]
When it reaches, the DET pulse shown in (C) of FIG. 2(A) is applied to the input terminal 101 in synchronization with the falling of the basic clock FCLK1.

As a result, the D-FF 105 uses the divided clock D CL
Rise of K 2 (counter value r64 of counter 1
J ) generates an output ((d) in Figure 2(A)
). In response to this output, the D-FFIO6 generates an output at the rising edge of the basic clock FCLK4 (count value r129J of counter 2) (Fig. 2 (A)).
(e)) Since the D-FF 107 uses the inverted basic clock FCLK as its clock, it generates an output at the falling edge of the basic clock FCLK4 ((f) in FIG. 2(A)). Since the D-FF 108 generates an inverted output, the "L" output is inverted from the previous @H" output at the falling edge of the basic clock FCLKs (as shown in FIG. 2 (A)). - The output width of the FF is one period of the divided clock DCLK.

Looking at the three forces applied to the input terminal of the NAND circuit 111, before the output of the D-FF 107 becomes "H", that is, before the falling point of the basic clock FCLK4, the output of the D-FF 107 is "L". Because there is, NAND
The output of the circuit 112 maintains the "H" state (see Fig. 2 (A)).
)(h)). Therefore, frequency divider 104 is not reset;
Continue normal frequency division operation.

At the falling edge of the basic clock FCLK4, D・FF10
7 changes from "L" to "H3", all three inputs added to the NAND circuit 111 become "H", so the NAND circuit 1
The output of 11 changes from "H" to "L". And, D-
FF108 goes “L” at the falling edge of basic clock FCLKs
The “L” state is maintained until the output is reversed (see Figure 2 (
A) (h)).

The frequency divider 104 receives the "L" output from the NAND circuit 111, and suspends the frequency division operation during this period, that is, one cycle from the fall of the basic clock FCLK4 to the fall of FCLKs. As a result, the frequency divider 104 starts the frequency division operation at the rising edge of the basic clock FCLK6, and generates the frequency divided clock DCLK3 ((b) in FIG. 2(A)).
)).

At the time when this divided clock DCLK3 is generated, the PSPC
112 (counter 1) indicates the count value "64", and counter 2 is counted up to r130J ((11, (Jl) in FIG. 2(A)).

On the other hand, the output generated by the D-FF107 at the falling edge of the basic clock FCLK4, that is, the frequency division start signal DSS, is the PSPCI
12 and becomes the frequency division ratio setting signal. Therefore, the PSPCI 12 is reset at the rising edge of the frequency dividing clock DCLK3 when this DSS is applied ((bl, (J) in FIG. 2(A)).

That is, the PSPC 112 (counter 1) is reset when the count value is counted up from "64" to "65", and the counter 2 is reset when the count value reaches rl 30.
It is reset when the count is counted up from J to rl 31J ((1) and (J) in FIG. 2(A)).

Therefore, if we look at the point in time when PSPC112 (counter 1) is reset with respect to the basic clock FCLK, 1/3
Therefore, the output terminal of the PSPCI 12 outputs a frequency-divided signal of 1/131 of the basic clock FCLK.

This operation is performed by the frequency divider 104 using the output of the NAND circuit 111.
The operation of is delayed by one cycle of the basic clock FCLK,
The reset operation of PSPCI 12, which would normally be performed at the rising edge of the basic clock FCLKs, is changed to the basic clock F.
This is due to the delay of one clock (one period) of CLK. As a result, PSPC112 (counter 1)
The period during which the count value "64" is held is longer by one period of the basic clock FCLK than the previous holding period of the count value (two periods of the basic clock FCLK).

With the above operations, using the conventional PSPCI 12,
A basic clock having twice the frequency can be divided into 1/131. The operation is similar when frequency division is performed using other odd frequency division ratios.

(2) Operation when the frequency division ratio is an even number When the frequency division ratio is an even number, the frequency division control signal DO3 applied to the input terminal 103 is set to "L". Therefore, the NA
Since the output of the ND circuit 111 is always "H", the frequency divider 104 performs normal frequency division operation, and the frequency division ratio setting signal DET
is added, there will be no temporary interruption in the frequency division operation.

Furthermore, the frequency division ratio setting signal DE applied to the input terminal 101
T is set to a value of (frequency division ratio - 4). Assuming that the frequency division ratio is r124J, which is an even number, the frequency division ratio setting signal D
ET becomes r120J.

In this case, when the counter 2 counts rl 20J, that is, when the PSPC 112 (counter 1) counts "60", as shown in FIG. frequency-divided clock DC
A DET pulse with a width of one period of LK is input to the input terminal 10.
It is configured to be added to 1.

In this configuration, the frequency divider 104, the D-FFs 105 to 1
The operation of 08 is similar to the case of (1) above.

The count value of PSPC112 (counter 1) is "60"
When the DET pulse shown in FIG. 2(B) (C) is applied to the input terminal 101 at the falling edge of the basic clock F CL K +.

As a result, in the same way as in (1) above, the D-FF10
5 is the fall of the frequency divided clock D CL K2 (counter 1 count (lr611. counter 2 count value r
122J) to generate an output at (d
>) D-FF106 is the basic clock FCLK4
(e) in Figure 2 (B)), D-FF
107 generates an output at the falling edge of the basic clock FCLK4 ((f) in FIG. 2(B)), D-FF
IO8, at the falling edge of the basic clock FCLKs,
The output width of each of these D-FFs, which is inverted from H'' to 6L'' (illustrated in FIG. 2B), is equal to one period of the frequency dividing clock 7 or DCLK.

Since the frequency division control signal DC3 is “L”, the NAND circuit 1
The output of 11 is always "H".

Therefore, if the frequency division ratio is an even number, the frequency division ratio setting signal DET
Even if the frequency divider 104 is added, the frequency divider 104 continues the normal frequency division operation.

As a result, the PSPC 112 (counter 1) inputs the frequency-divided clock DCLK and performs a count-up operation.

The output generated from the D-FF107 at the falling edge of the basic clock FCLK4, that is, the frequency division start signal DSS, is the PSPC.
When applied to I 12, PSPCI 12 uses this frequency division activation signal DSS as its division ratio setting signal, and is set at the rising edge of frequency division clock D CL K3 (as shown in FIG. 2 (B)). h)).

That is, the PSPC 112 (counter 1) is reset when the count value is counted up from "61" to "62", and the counter 2 is reset when the count value reaches r123J.
It is reset when the count is counted up from r124J ((hl, +1) in FIG. 2(B)). Therefore, if we look at the point in time when the PSPC 112 (counter 1) is reset with respect to the basic clock FCLK, it means that the frequency has been divided by 1/124, and from the output terminal of the PSPCI 12, a signal divided by 1/124 of the basic clock FCLK is output. is output.

With the above operations, using the conventional PSPCI 12,
A basic clock having twice the frequency can be divided into 1/124. The operation is similar when frequency division is performed using other even frequency division ratios.

An embodiment of the present invention has been described above, but in this embodiment, from the relationship of the frequency division ratio setting signal, when the frequency division ratio is an even number, it is 1/4, and when the frequency division ratio is an odd number, it is 115. Small frequency division is not possible, but in the case of such a small frequency division ratio, the delay in the frequency division operation is not a problem in practice, so the frequency division operation can be reduced to 2.
There is no need to double the speed. Since the delay in the frequency division operation becomes a problem when the frequency division ratio is large, such as several tens of tenths or more, there is no problem in practicality even with the above-mentioned limitations.

〔Effect of the invention〕

As explained above, according to the present invention, a preset type synchronous programmable counter and an operating power supply are used to create a preset type synchronous programmable counter that can perform frequency division operations twice as fast as conventional ones. A programmable counter can be realized. In addition, it does not require a device with a particularly short play time, and can be constructed using the same circuit elements and operating power source as conventional ones, making it easy to design and keeping costs low.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of one embodiment of the present invention, Fig. 2 is a time chart showing the operation of the same embodiment, Fig. 3 is an explanatory diagram of a conventional preset type synchronous programmable counter, and Fig. 4 is an explanatory diagram of an embodiment of the present invention. shows a time chart showing the operation of FIG. In Fig. 1, 101... input terminal of the division ratio setting signal (DET), 1
02...Basic clock (FCLK) input terminal,
103...Input terminal of frequency division control signal (DC3), 10
4... Frequency divider, 105-108... D type flip.
Flop (D-FF), 109.110... Inverter, 111... NAND circuit, 112... Preset type synchronous programmable counter (PS
PC), DCLK...divided clock signal.

Claims (1)

[Claims] A preset type synchronous programmable device that generates an output obtained by dividing a basic clock according to a frequency division ratio setting signal.
In the counter, (a) a frequency divider that divides the basic clock into 1/2, and (b)
) a preset type synchronous programmable counter which inputs the divided clock output from the frequency divider and generates an output by dividing the frequency of the divided clock according to a division start signal corresponding to the division ratio setting signal; (c) Based on the division ratio setting signal set corresponding to the desired division ratio with respect to the basic clock frequency, the time point when counting up is performed to the divided clock frequency closest to 1/2 of the division ratio. The preset type synchronous programmable circuit generates a frequency-divided activation signal having a width including at least the count-up time but not including at least the previous count-up time.
(d) only when the division ratio is an odd number with respect to the basic clock frequency, the division start signal is a preset synchronous
A preset type synchronous clock comprising means for delaying the division operation of the first frequency divider by one period of the basic clock when input to the programmable counter.
Programmable counter.