JPH0613891A - Frequency divider - Google Patents

Abstract

PURPOSE:To generate output signals equivalent to a 2XN+1 divider for which an input frequency is doubled by delaying the shift register of N+2 stages supplied while being delayed for a fixed time Td and the output of a first stage for Td to be logically operated with the output of a final stage. CONSTITUTION:The Q output of a D-FF 220 which is the output of a 3 frequency division ring counter 200 outputs frequency divided signals which are three times as much as the cycle of the input signal 110 of 5 frequency divider and whose duty ratio is 2:1. The D type FF 310 of the edge trigger of a 3-stage shift register 300 receives the Q output of the D-FF 220 as D input. The D-FFs 310 and 320 shift the Q output of the D-FF 220 at the rising edge of a clock signal 110 and the FF 330 shifts the output at the falling edge of the signal 110. The clock input of the FF 330 is delayed for the total time Td of carrier delay time from the rising edge of the CK input of the FF 320 to the D input of the FF 330 and the set up time of the FF 330. An OR gate 400 ORs a signal 401 for which the -Q output of the FF 310 is delayed for Td and the -Q output of the FF 330 and outputs the frequency 110 is frequency divided to one half.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency divider using a digital circuit, and more particularly to a frequency divider which needs to improve the toggle frequency of a device in order to obtain an output signal of a required frequency.

[0002]

2. Description of the Related Art Conventionally, when a frequency divider is constructed by using a digital circuit and a frequency-divided signal equivalent to the N + 0.5 frequency-divided signal is obtained, a 2 × N + 1 frequency divider is constructed to double the input frequency. The method of doing was generally done.

FIG. 3 shows a known example of a 2 × N + 1 frequency division ring counter (reference: ASIC logic circuit design method, 1988 CQ).
Publication). Ring counter is 2 × N
Input signal 410, which is composed of four flip-flops.
Is divided by 2 × N + 1 and a divided signal having a duty ratio of 2 × N: 1 is output to 420.

[0004]

In order to obtain a frequency-divided signal equivalent to the N + 0.5 frequency-divided signal, a method of forming a 2 × N + 1 frequency divider and doubling the input frequency is used. Since the upper limit frequency of is determined by the toggle frequency of the device, it is necessary to use a device with a high toggle frequency in order to improve the upper limit frequency of the divided signal.

Taking the known example of FIG. 3, 2 × N + 1
Set the frequency of the output signal 420 of the frequency division ring counter to f42.
Assuming 0, the frequency of the output signal 410 is f410 = (2 × N
+1) × f420, and to obtain an output frequency equivalent to N + 0.5 frequency division output, f410 = 2 × (2 × N + 1)
A frequency divider for dividing a signal having a frequency of × f420 is required. Therefore, the output signal is 4 at the toggle frequency of the device.
A frequency more than 2 × (2 × N + 1) times 20 is required, and it has been impossible to obtain a high-speed output signal due to the limit of the toggle frequency.

An object of the present invention is to provide a frequency divider that divides an input frequency by N + 0.5, and to provide means for obtaining an output signal of a required frequency without increasing the toggle frequency of the device.

[0007]

The above-mentioned object is to achieve the structure of the frequency divider described in claim 1 by
It is possible to make a frequency divider that divides the input frequency by N + 0.5 using the existing technology.

[0008]

By using the N + 0.5 frequency divider of the present invention, a signal equivalent to the output signal in the case of using the method of constructing a 2 × N + 1 frequency divider and doubling the input frequency is used. It is possible to generate the signal without increasing the voltage, and in the N + 2 stage shift register, only the clock input of the final stage flip-flop is inverted in polarity, and
By supplying the signal with a delay of Td for a certain period of time, the performance of the frequency divider can be improved up to the limit of the toggle frequency of all flip-flops constituting the frequency divider.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention and shows the configuration of a 1.5 frequency divider when N = 1. Figure 1
In the figure, 200 indicates a divide-by-3 ring counter, and 300 indicates a 3-stage shift register. 200 is composed of edge-triggered D-type flip-flops 210 and 220,
The Q output of 220, which is the output of 200, outputs a frequency-divided signal having three times the cycle of the input signal 110 of the 1.5 frequency divider and a duty ratio of 2: 1. The three-stage shift register 300 is an edge-triggered D-type flip-flop 310, 32.
0,330, and 310 has 220 Q outputs as D
Receive as input. 310 and 320 shift the Q output of 220 at the rising edge of the clock signal 110,
330 shifts on the falling edge of 110. The propagation delay time between the D input of 320 and the D input of 330 needs to be 1/2 or less of the cycle of the clock signal 110, but from the rising edge of the CK input of 320 to the D input of 330.
This can be avoided by delaying the clock input of 330 by the total time Td of the propagation delay time to the input and the setup time of 330. The OR gate 400 has 310-
The signal 401 obtained by delaying the Q output by Td and the -Q output of 330 are ORed, and the frequency division of 110 is performed by 1.5, and the duty ratio is 2:
The divided signal 120 of 1 is output. As described above, 1.5
The time chart of the frequency divider is shown in FIG.

[0010]

According to the present invention, it is possible to generate an output signal equivalent to a 2 × N + 1 frequency divider in which the input frequency is doubled by the N + 0.5 frequency divider, and the apparent frequency limit is obtained. Can be expected to improve.

[Brief description of drawings]

FIG. 1 is a diagram showing a 1.5 frequency divider according to an embodiment of the present invention.

FIG. 2 is a timing chart of the 1.5 divider of FIG.

FIG. 3 is a diagram showing a known 2 × N + 1 dividing ring counter of the prior art.

[Explanation of symbols]

 200 ... 3 division ring counter, 300 ... 3-stage shift register, 110 ... Input signal, 120 ... Output signal.

Claims (1)

[Claims] 1. A frequency divider for dividing an input signal S _IN having a predetermined frequency and a duty ratio of 1: 1 into a signal S ₀ of 2 × N + 1 frequency division (N is a natural number), and S ₀ is an input signal. , S _IN as a clock signal, the polarity of only the clock input of the final stage flip-flop is inverted, and N + 2 stages of shift registers supplied with a delay of Td and the first stage of the shift registers are supplied. The output of the shift register is delayed by Td to perform a logical operation with the output of the final stage of the shift register, and the result of the logical operation is an output signal S _OUT of N + 0.5 of S _IN. And the divider.