JPS61198355A - Multi-processor system - Google Patents

Abstract

PURPOSE:To quicken the inter-processor communciation instruction processing by applying interlock between processors so as to reduce the hardware of processors and to simplify the firmware in issuing the inter-processor communciation instruction. CONSTITUTION:When a TEST and SET instruction is executed, a processor 21 decides whether or not an FF 34 is set already depending on the signal state of a specific line on a data line of a system bus 26. When the FF 34 is set already, the processor 21 withdraws the issue of the inter-processor communication instruction while it is regarded that other processor issues the said instruction or is going to issue it. On the other hand, when the FF 34 is reset, it is regarded that the right of issue of the said instruction is given, the processor 21 issues the inter-processor communication instruction to a processor 22. When a series of processings is finished, the processor 21 executed a reset instruction resetting the FF 34.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multiprocessor system that applies a split bus control method, and particularly to an interprocessor communication command processing method.

[Technical Background of the Invention] In a multiprocessor system, each processor needs to operate in cooperation with each other.

Therefore, each processor may have to request other processors to notify their status or request some kind of processing. Therefore, inter-processor communication instructions are generally provided as a means for this purpose.

Processing of interprocessor communication commands in a conventional multiprocessor system will be explained with reference to FIG.

In the multiprocessor system shown in FIG. 3, a plurality of processors 11 to 14, for example four, are interconnected by a system bus 15 to which a split bus control method is applied. Further connected to the system bus 15 are a bus control unit (hereinafter referred to as BCU) 16 that controls the bus 15, a main memory 17 that is commonly used by each of the processors 11 to 14, and the like.

Now, in the system shown in FIG. 3, for example, processor 1
When the processor 1 issues an inter-processor communication command to the processor 12, the processing procedure for the command is as follows.

(2) The processor 11 issues an inter-processor communication command to the processor 12 via the system bus 15.

(2) When the processor 12 receives an interprocessor communication command from the processor 11, it notifies the processor 11 through the system bus 15 that it has received the command.

■ When the processor 11 confirms that the processor 12 has received the inter-processor communication command, the processor 11
Information indicating the content of the request (hereinafter referred to as a directive)
is transferred via the system bus 15.

(2) When the processor 12 receives a command from the processor 11, it performs the requested processing in accordance with the command.

(2) When the processor 12 completes the processing requested by the processor 11, it notifies the processor 11 via the system bus 15 that the processing has been completed. with this,
The processing of inter-processor communication instructions is completed.

As described above, in processing an inter-processor communication command, data is exchanged several times between the corresponding processors via the system bus 15.

On the other hand, the system bus 15 has [split t<2 II
The I m method is applied. This split bus control method differs from a method in which one processor occupies the bus until a series of procedures are all completed, and the bus is released for each data transfer (every bus cycle). Therefore, in the multiprocessor system shown in FIG. 3, the following situation may occur.

(a) A plurality of processors issue inter-processor communication commands to one processor almost simultaneously (before processing of one inter-processor communication command is completed).

(b) Two processors issue inter-processor communication commands to each other's processor almost simultaneously.

In order to deal with the situation (b) above, each processor 11
-14 have a built-in FIFO memory for storing inter-processor communication commands from other processors, and sequentially retrieve and process the inter-processor communication commands stored in the memory.

Now, when the situation (b) above occurs, if the hardware and firmware of each processor is structured so that it can only process the inter-processor communication command while it is issuing the inter-processor communication command, the inter-processor communication command issued by both processors will Because the response to the communication command is not returned forever,
You end up in a deadlock situation. Therefore, in order to avoid this situation, the processors 11 to 14 in the system shown in FIG. It has a structure.

[Problems with the Background Art] As described above, in conventional multiprocessor systems, FIFO memory 1 There was a problem in that the amount of hardware increased due to the installation of new hardware, etc., and the firmware became more complex. ``Due to the complexity of the firmware described above, there was a problem that the processing speed decreased even when processing normal (one-to-one) inter-processor communication commands, which occur frequently. Purpose] This invention was made in view of the above circumstances, and its purpose is to eliminate the contention state by interlocking between processors when issuing inter-processor communication commands, thereby reducing the Is-doware amount of each processor. It is an object of the present invention to provide a multiprocessor system that can reduce the number of processors, simplify firmware, and speed up interprocessor communication instruction processing.

[Summary of the Invention] This invention provides a bus control unit (B) of a multiprocessor system that applies a split bus control method.
CU) is provided with a flag indicating whether or not an inter-processor communication command can be issued. The processors in the system refer to the flag in the bus control unit when issuing an inter-processor communication command, and have means for issuing the command in accordance with the reference result. In other words, if each processor attempts to issue an interprocessor communication command and the flag is in the first logical state, it assumes that an interlock has been applied by another processor, waits for the command to be issued, and responds accordingly. If the flag is in the second logic state, it is assumed that it is possible to issue an interprocessor communication command, and the flag is set to the first logic state to interlock other processors. configured to issue instructions; With such a configuration, it is possible to prevent the occurrence of a race condition in which a plurality of processors issue interprocessor communication commands at the same time.

(Embodiment of the Invention) FIG. 1 shows the configuration of a multiprocessor system according to an embodiment of the invention. In the figure, 21 to 24 are processors, and 25 is a main storage device commonly used by the processors 21 to 24. 2 (system node that applies the 3G split bus control method), 27 (BCU (/< system control unit) that controls the system bus 26)
It is. The processors 21 to 24, the main storage device 25, and the BCU 27 are interconnected by a system bus 26. The system bus 261 has data lines, address lines, function lines, and control lines (all not shown). The function line (Y) is used to transfer information specifying the mode of access to the main memory 25 or BCU 27.The control line is also used to transfer memory start signal C.
Used for transferring various control signals such as MSTA.

In the BCLI 27, 31 is a decoder that decodes some information on the system bus 26 (specifically, information on the address line and the function line); 32.3
3 is a decode signal line of the decoder 31. The enable terminal EN of the decoder 31 is connected to the system bus 26 (
A memory start signal CMSTA is led from a predetermined line among the control lines of the memory start signal CMSTA. 34
is a flip-flop used as a flag indicating whether or not an inter-processor communication command can be issued, such as the JK flip 70.
Tsubu (hereinafter referred to as F/F), 35 is F / F 3
This is an output gate that outputs a Q.4 output signal to a specific line of (among the data lines of) the system bus 26 in accordance with the state of the decode signal line 32. The J input terminal of the F/F 34 is connected to the decode signal line 32, and the K input terminal is connected to the decode signal line 33.

Next, the operation of one embodiment of the present invention will be described with reference to the flowchart of FIG. 2, taking as an example a case where the processor 21 attempts to issue an inter-processor communication command to the processor 22. In this case, the processor 21 first
TEST&SE for F/F 34 in CU27
The T command is executed (step 81). This F/F
TEST & SET command for F/F 3
This command causes the F/F 34 to be set if it has been reset, leaves it in the same state if it has been reset, and notifies the processor that issued the command whether or not the F/F 34 has already been set.

The specific operation of executing the TEST&SET command on the F/F 34 will be described below.

In this example, T E S T & S E,
The T instruction is specified on the function line of the system bus 26, and the F//F 34 in the B CU 27 is specified on the address line of the system bus 26. That is, when the processor 21 intends to issue an interprocessor communication command, it sends address information specifying the F/F 34 in the 8CU 27 to the address line of the system bus 26, and also sends function information specifying the TEST & SET command to the system bus. It is sent to 26 function lines. In addition, in this embodiment, the F in the BCU 27
Execution of the TEST&SET command to /F 34 is public, similar to access to the main memory 1if 125. Therefore, the processor 21 sends the memory start signal CMSTA to a specific line in the control line of the system bus 26 when sending the address information and function information.

Sent from the processor 21 (F/F in the BCU 27
34) and the memory start signal CMSTA are guided to the decoder 31 in the B CtJ 27. The decoder 31 decodes the TEST & SET command designation information for the F/F 34 in response to the memory start signal @CMSTA, and
A decode signal of logic "1" indicating that the ST&SET command has been specified is output to the decode signal line 32. The signal of logic "1" on the decode signal line 32 is
/F 34 is guided to the J input terminal and also to the output gate 35.

As a result, the output gate 35 outputs F at that point.
/F The Q output signal indicating the status of 34 is sent to system bus 2.
It is sent to a specific line among the 6 data lines.

Depending on the state on this particular line, the processor 21
/F It is possible to recognize whether or not 34 has already been set. On the other hand, the F/F 34 has a logic 111++ signal input to the J input terminal.
It is set if it is in the reset state at that time.

If set, F/F 34 remains set.

When the processor 21 executes the TEST & SET command, it determines whether the F/F 34 has already been set based on the signal state of a specific line in the data line of the system bus 26 (step 82>.F).
/ F If 34 has already been set (i.e. YE
In the case of determination S), the processor 21 suspends issuing the inter-processor communication command, assuming that another processor has issued or is about to issue the inter-processor communication command.

The processor 21 then determines whether or not an inter-processor communication command has been received, taking into consideration the possibility that another processor that has set the F/F 34 will issue an inter-processor communication command to the same processor 21. (Step 83). If it has been received (that is, if the determination is YES), the processor 21 proceeds to inter-processor communication reception processing. On the other hand, if the inter-processor communication command has not been received (that is, if the determination is No), the processor 2
1 returns to the process of step S1 and executes the TEST&SET command for the F/F 34 again. The above sequence is repeated until the F/F 34 is reset, that is, until the other processor completes the inter-processor communication command issuing process.

On the other hand, if the determination in step S2 is NO, that is, F
/F If the F 34 has been reset, the processor 21 assumes that it has been given the right to issue an inter-processor communication command, issues an inter-processor communication command to the processor 22, and performs the processing described in the prior art. (Step 84). After completing this series of processing, the processor 21 executes a reset instruction to reset the F/F 34 (step 85). This F/
The execution of the reset command for F34 is performed by the above-mentioned TE.
This is done in the same way as the ST&SET instruction. That is, when the processor 21 wants to reset the F/F 34 in the 8 CU 27, it issues a reset command to the F/F 34 together with the memory start signal CMSTA. In this case, the decoder 31 in BC4J27
/F A logic "1" signal indicating that a reset command for 34 has been designated is output to decode signal line 33. The logic "1" signal on the decode signal line 33 is led to the input terminal of the F/F 34, thereby resetting the F/F 34 (which was in the set state).

Note that the above description of the operation is for the case where the processor 21 issues an inter-processor communication command, but the same applies to cases where the other processors 22 to 24 try to issue an inter-processor communication command.

[Effects of the Invention] As detailed above, according to the present invention, the following effects can be achieved.

■ When issuing inter-processor communication commands, interlocking between processors eliminates conflict, so multiple processors will no longer issue inter-processor communication commands to one processor. Therefore, the FIF○ memory and its control circuit are not required, and the amount of hardware can be reduced.

■ Since two processors no longer issue inter-processor communication commands to each other's processors at almost the same time, there is no need to deal with parallel processing of receiving inter-processor communication commands, which simplifies firmware and The number of steps can be reduced.

■ Since the firmware can be simplified, the processing speed of inter-processor communication commands can be increased.

In addition, in this invention, if multiple processors try to issue an inter-processor communication command at almost the same time, some processors will be forced to issue the same command; The probability of attempting to issue this command is extremely low, and it has no effect on anything other than inter-processor communication commands, so there is almost no negative impact on the performance of the entire system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiprocessor system according to an embodiment of the present invention, FIG. 2 is a flow chart for explaining the operation, and FIG. 3 is a block diagram showing a conventional example. 21 to 24... Processor, 26... System bus, 27... Bus control unit (BCU), 3
1...Decoder, 34...JK flip-flop (
F/F, flag). Applicant's agent Patent attorney Takeshi Suzue Industry 1 diagram processing each 5J Figure 3

Claims (1)

[Claims] It has a system bus to which a split bus control method is applied, a plurality of processors connected to this system bus, and a bus control unit that controls the system bus. In a multiprocessor system where communication is performed, the bus control unit has
A flag is provided to indicate whether or not the inter-processor communication command can be issued, and each processor is instructed to refer to the flag when issuing the inter-processor communication command, and when the flag is in the first logical state, issue the command. A multiprocessor system comprising means for waiting, and when the flag is in a second logic state, setting the flag to a first logic state and issuing the instruction.