JPS61196576A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61196576A JPS61196576A JP60035225A JP3522585A JPS61196576A JP S61196576 A JPS61196576 A JP S61196576A JP 60035225 A JP60035225 A JP 60035225A JP 3522585 A JP3522585 A JP 3522585A JP S61196576 A JPS61196576 A JP S61196576A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- mos transistor
- integrated circuit
- isolation
- vertical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000002955 isolation Methods 0.000 abstract description 16
- 238000002161 passivation Methods 0.000 abstract description 4
- 239000011810 insulating material Substances 0.000 abstract description 3
- 239000012212 insulator Substances 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 13
- 230000002093 peripheral effect Effects 0.000 description 9
- 238000001259 photo etching Methods 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 241000238557 Decapoda Species 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野１
この発明は、所謂縦型ＭＯＳトランジスタと集積回路と
が同一チップ上に形成ざれた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention 1] The present invention relates to a semiconductor device in which a so-called vertical MOS transistor and an integrated circuit are formed on the same chip.
［発明の技術的背景］
近年、各種電力負荷のスイッチング素子として、オン抵
抗が低くパワースイッチングに適している縦型のＭＯＳ
トランジスタの需要が高まりつつある。[Technical Background of the Invention] In recent years, vertical MOSs, which have low on-resistance and are suitable for power switching, have been used as switching elements for various power loads.
Demand for transistors is increasing.
この縦型ＭＯＳトランジスタをスイッチング素子として
使用した場合には、スイッチング作用を制御するために
種々の周辺回路を必要とする。このような周辺回路を縦
型ＭＯＳトランジスタと同一の基板上に集積化し形成す
ることは、周辺回路を個別に外部接続する場合に比べて
、周辺回路の小型化、製造工程の低減等の面で利点があ
る。そのため、縦型ＭＯＳトランジスタと周辺回路を同
一基板上に形成することが考えられる《例えば特開昭５
８−１ ６４３２３）。When this vertical MOS transistor is used as a switching element, various peripheral circuits are required to control the switching action. Integrating and forming such peripheral circuits on the same substrate as vertical MOS transistors is more effective in terms of miniaturization of peripheral circuits and reduction of manufacturing process, compared to the case where peripheral circuits are individually connected externally. There are advantages. Therefore, it is conceivable to form vertical MOS transistors and peripheral circuits on the same substrate (for example,
8-1 64323).
しかしこの場合に、縦型ＭＯＳトランジスタのドレイン
電流により周辺回路が誤動作ずる等の不具合の発生を防
止するため、周辺回路をいかに縦型ＭＯＳトランジスタ
から電気的に分離するかが重要な問題“となる。However, in this case, an important issue is how to electrically isolate the peripheral circuit from the vertical MOS transistor in order to prevent problems such as malfunction of the peripheral circuit due to the drain current of the vertical MOS transistor. .
［発明の目的］
この発明は、上記に鑑みてなされたもので、その目的と
するところは、所謂縦型ＭＯＳトランジスタと集積回路
とを確実に絶縁した状態で容易に同−チップ上に形成し
得るようにした半導体装置を提供することにある。[Object of the Invention] The present invention has been made in view of the above, and its object is to easily form a so-called vertical MOS transistor and an integrated circuit on the same chip while reliably insulating them. An object of the present invention is to provide a semiconductor device that can be obtained.
［発明の概要］
上記目的を達成するために、この発明は、絶縁体層を有
する基板に縦型ＭＯＳトランジスタと集積回路とを形成
し、該縦型ＭＯＳトランジスタと集積回路との間に基板
表面から前記絶縁体層に至る溝を形成し、該溝により縦
型トランジスタと集積回路とを分離したことを要旨とす
る。[Summary of the Invention] In order to achieve the above object, the present invention forms a vertical MOS transistor and an integrated circuit on a substrate having an insulating layer, and forms a substrate surface between the vertical MOS transistor and the integrated circuit. The gist of the present invention is to form a groove extending from the insulating layer to the insulating layer, and to separate the vertical transistor and the integrated circuit by the groove.
［発明の実施例］ 以下、図面を用いてこの発明の詳細な説明する。[Embodiments of the invention] Hereinafter, the present invention will be explained in detail using the drawings.
第１図は、この発明の一実施例に係る半導体装置の断面
構造を示す図である。同図において、ｎ＋型の基板（以
下「ｎ＋基板」と呼ぶ。）１１の上にｎ型エピタキシャ
ル層（以下「ｎエビ層」と呼ぶ。）１３を成長させ、こ
のｎエビ層１３の上に縦型ＭＯＳＦＥＴ部（以下ｒＭＯ
８ＦＥＴＪと呼ぶ。）１と、横型ＰチャンネルＭＯＳト
ランジスタ（以下ｒＰＭＯＳトランジスタ」と呼ぶ。）
５及び横型ＮチャンネルＭＯＳトランジスタ（以下［Ｎ
ＭＯＳトランジスタ１と呼ぶ。）７とで構成されている
横型ＣＭＯ８回路部（以下ｒＣＭＯ８回路部Ｊと呼ぶ。FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor device according to an embodiment of the present invention. In the figure, an n-type epitaxial layer (hereinafter referred to as "n shrimp layer") 13 is grown on an n + type substrate (hereinafter referred to as "n + substrate") 11, and on this n shrimp layer 13, Vertical MOSFET section (rMO
It is called 8FETJ. ) 1 and a lateral P-channel MOS transistor (hereinafter referred to as rPMOS transistor).
5 and lateral N-channel MOS transistor (hereinafter referred to as [N
It is called MOS transistor 1. ) 7 (hereinafter referred to as rCMO8 circuit section J).
）３が形成されている。)3 is formed.
ＭＯ８ＦＥＴＩが形成されているｎエビ層１３及びその
下部のｎ子基板１１と、ＣＭＯ８回路部３が形成されて
いる０工ビ層１３及びその下部のｎ＋基板１１とは、後
述する分離用内部酸化ｍ５１にまで達する分離溝４９に
より分離されており、この分離溝４９に埋込まれた絶縁
物及び中間絶縁膜２９により、ＭＯＳ Ｆ Ｅ Ｔ １
とＣＭＯ８回路３とは、電気的に絶縁されている。なお
、３１は半導体装置の表面を不動体化するパッシベーシ
ョン膜である。The n-layer 13 on which the MO8FETI is formed and the n-substrate 11 below it, and the 0-layer 13 on which the CMO8 circuit section 3 is formed and the n+ substrate 11 below it are separated by internal oxidation for isolation, which will be described later. The MOS FET 1
and the CMO8 circuit 3 are electrically insulated. Note that 31 is a passivation film that makes the surface of the semiconductor device passivation.
ＭＯＳＦＥＴ１はｎｘビ１１３及びｎ１基板１１をドレ
イン領域とし、ｎ″″基板１１の下部には、このｎ＋基
板１１を酸化して形成される分離用内部酸化膜５１を介
して、ｎ＋基板１１を支持しＭＯＳＦＥＴ１のドレイン
電極を構成するｎ１ポリシリＷＪ９が形成されている。The MOSFET 1 uses the nx bi 113 and the n1 substrate 11 as a drain region, and supports the n+ substrate 11 at the bottom of the n'' substrate 11 via an internal oxide film 51 for isolation formed by oxidizing the n+ substrate 11. An n1 polysilicon WJ9 forming the drain electrode of MOSFET1 is formed.
分離用内部酸化膜５１はＭＯＳＦＥＴ１のドレイン領域
となる部分において除去され、この除去された部分（以
下「コンタクト部」と呼ぶ。）のｎ＋基板１１とｎ＋ポ
リシリｗＩ９とにコンタクトがとられており、ドレイン
電流の通路となっている。またｎエビ層１３の中にはＰ
型の領域（以下「Ｐウェル」と呼ぶ。）１５が形成され
、このＰウェル１５の中にｎ＋ソース領域（以下ｒＭＯ
８ＦＥＴソース領域」と呼ぶ。）１７、Ｐ＋ソースコン
タクト領域（以下［ソースコンタクト領域Ｊと呼ぶ。）
１９が形成されている。さらにコンタクト部２３の上部
にゲート酸化膜２５を介してポリシリコンゲートが形成
されており、ＭＯ８ＦＥＴゲート電極２７を構成してい
る。The isolation internal oxide film 51 is removed in a portion that will become the drain region of the MOSFET 1, and contact is made between the n+ substrate 11 and the n+ polysilicon wI9 in this removed portion (hereinafter referred to as a "contact section"). It serves as a path for drain current. In addition, there is P in n-shrimp layer 13.
A type region (hereinafter referred to as "P well") 15 is formed, and an n+ source region (hereinafter referred to as rMO) is formed in this P well 15.
8FET source region. ) 17, P+ source contact region (hereinafter referred to as source contact region J)
19 is formed. Further, a polysilicon gate is formed above the contact portion 23 with a gate oxide film 25 interposed therebetween, and constitutes a MO8FET gate electrode 27.
ＣＭＯ８回路部３は、エピタキシャル成長によってｎ＋
基板１１上に成長したｎ工と１１１３に形成されており
、このｎエビ１ｌｆ１３の由に所定間隔だけ離れて一対
のＰ１型の領域が形成され、ＰＭＯＳトランジスタ５の
ソース領域（以下ｒＰＭ。The CMO8 circuit section 3 is made of n+ by epitaxial growth.
A pair of P1 type regions are formed at a predetermined distance apart from each other by a predetermined distance due to the n layer 1113 grown on the substrate 11, and a source region (hereinafter referred to as rPM) of the PMOS transistor 5 is formed.
Ｓソース領域Ｊと呼ぶ。）３３及び、ドレイン領域（以
下ｒＰＭＯｓドレイン領域Ｊと呼ぶ。）３５を構成し、
ＰＭＯＳソース領域３３とＰＭＯＳドレイン領域３５と
の間に生じるチャンネルの上部にゲート酸化膜３７を介
してＰＭＯＳゲート電極３９が形成され、ＰＭＯ３トラ
ンジスタ５が構成されている。またｎエビ層１３にはＰ
型の領域（以下「Ｐウェル」と呼ぶ。）４１が形成され
ており、このＰウェル４１中に所定間隔だけ離れて一対
のｎ＋型の領域が形成され、ＮＭＯ３トランジスタ７の
ドレイン領域（以下ｒ ｒＮＭＯｓドレイン領域」と呼
ぶ。）４３及び、ソース領域（以下ｒＮＭＯｓソース領
域」と呼ぶ。）４５を構成しており、ＮＭＯＳドレイン
領域４３及びＮＭＯＳソース領域４５との間に生じるチ
ャンネルの上部に、ゲート酸化膜３７を介してＮＭＯＳ
ゲート電極４７が形成され、ＮＭＯＳトランジスタ７が
構成されている。またＣＭＯ８回路部３が形成されてい
るｎ＋基板１１の下部に、前記分離用内部酸化膜５１を
介して前述したｎ＋ポリシリ層９が形成され、このｎ＋
ポリシリｗＡ９とＣＭＯ８回路部３が形成されているｎ
＋基板１１とは分離用内部酸化膜５１により電気的に絶
縁されている。It is called S source region J. ) 33 and a drain region (hereinafter referred to as rPMOs drain region J) 35,
A PMOS gate electrode 39 is formed above a channel formed between a PMOS source region 33 and a PMOS drain region 35 with a gate oxide film 37 interposed therebetween, thereby configuring a PMO3 transistor 5. Also, in the n-shrimp layer 13, P
A type region (hereinafter referred to as "P well") 41 is formed, and a pair of n+ type regions are formed in this P well 41 at a predetermined interval apart, and a drain region (hereinafter referred to as r 43 and a source region (hereinafter referred to as the "rNMOS source region") 45, and a gate is formed above the channel formed between the NMOS drain region 43 and the NMOS source region 45. NMOS through oxide film 37
A gate electrode 47 is formed, and the NMOS transistor 7 is configured. Further, the above-mentioned n+ polysilicon layer 9 is formed on the lower part of the n+ substrate 11 on which the CMO8 circuit section 3 is formed, with the isolation internal oxide film 51 interposed therebetween.
Polysilicon wA9 and CMO8 circuit section 3 are formed n
It is electrically insulated from the positive substrate 11 by an internal oxide film 51 for isolation.
このような構成を有する半導体装置にあっては、ＭＯ８
ＦＥＴＩとこのＭＯＳＦＥＴ１の周辺回路を構成する例
えばＣＭＯ８回路部３とを分離溝４９により分離し、こ
の分離溝に絶縁物を埋込むことにより両者が電気的に絶
縁状態となるため、ＭＯＳＦＥＴ１とＣＭＯ８回路部３
とを、このＣＭＯ８回路部３を単体で構成した場合と同
等の特性をもって、容易に同一基板上に集積化し構成す
ることができる。In a semiconductor device having such a configuration, MO8
The FETI and, for example, the CMO8 circuit part 3 that constitutes the peripheral circuit of this MOSFET 1 are separated by a separation trench 49, and by filling this separation trench with an insulating material, they are electrically insulated, so that the MOSFET 1 and the CMO8 circuit Part 3
can be easily integrated and configured on the same substrate with the same characteristics as when the CMO8 circuit section 3 is configured as a single unit.
次に、本実施例の半導体装置についての製造プロセスを
第２図の（Ａ）〜（Ｊ）を用いて説明する。Next, the manufacturing process for the semiconductor device of this example will be explained using FIGS. 2A to 2J.
■ｎ ＋ ％板１１の下部に、この０１基板１１を酸化
して分離用内部酸化膜５１を形成し、ＭＯＳＦＥＴ１の
ドレイン電流の通路となるコンタクト部２３の分離用内
部酸化膜５１をフォトエツチング法により除去する（第
２図（Ａ））。■ At the bottom of the n + % board 11, oxidize this 01 substrate 11 to form an isolation internal oxide film 51, and photoetch the isolation internal oxide film 51 of the contact section 23, which will become a path for the drain current of the MOSFET 1. (Fig. 2(A)).
■分離用内部酸化膜５１の下部に、ｎ＋基板１１を支持
しＭＯ８ＦＥＴＩのドレイン電極を構成するｎ＋ポリシ
リ層９を堆積させる（第２図（Ｂ））。(2) An n+ polysilicon layer 9, which supports the n+ substrate 11 and constitutes the drain electrode of the MO8FETI, is deposited under the isolation internal oxide film 51 (FIG. 2(B)).
■ｎ＋基板１１の表面を研削、研磨して、この研削、研
磨したｎ＋基板１１の上に０１１層１３をエピタキシセ
ル成長させる（第２図（Ｃ））。(2) The surface of the n+ substrate 11 is ground and polished, and an 011 layer 13 is epitaxially grown on the ground and polished n+ substrate 11 (FIG. 2(C)).
■ｎｎエピ１３の表面を酸化してＭＯＳ Ｆ Ｅ Ｔ１
のゲート酸化１１２５を形成し、このゲート酸化１１２
５の上にポリシリコン５３を堆積させ、このポリシリコ
ン５３にリン等をドープして抵抗を下げた後に、ＭＯ８
ＦＥＴＩのＰつＩル１５及びＣＭＯ８回路部３を構成す
るＮＭＯＳトランジスタ７のＰウェル４１となる部分の
上部に堆積したポリシリコン５３を、フォトエツチング
法により除去して開口部５５を形成し、この開口部５５
にボロン等のイオンを注入し埋込み拡散を行ない、ＭＯ
８ＦＥＴＩのＰウェル１５及びＮＭＯＳトランジスタ７
のＰウェル４１を形成する（第２図（Ｄ））。■nn Oxidize the surface of epi layer 13 to create MOS F E T1
Form a gate oxide 1125 of gate oxide 112
After depositing polysilicon 53 on top of MO8 and doping this polysilicon 53 with phosphorus or the like to lower the resistance,
The polysilicon 53 deposited on the portion that will become the P well 41 of the NMOS transistor 7 constituting the P well 15 of the FETI and the CMO8 circuit section 3 is removed by photoetching to form an opening 55. Opening 55
By implanting ions such as boron into the MO
8FETI P well 15 and NMOS transistor 7
A P-well 41 is formed (FIG. 2(D)).
０ＭＯ８ＦＥＴゲート電極２７を形成するポリシリコン
５３を残して、フォトエツチング法により不要となるポ
リシリコン５３を除去して、ＭＯＳＦＥＴゲート電極２
７を形成する。次に酸化膜５７及び窒化ｌｌ１５９を順
次表面に形成して、後述するＬＯＣＯ８ＩＩ化膜６１を
形成する部分の窒化１５９をフォトエツチング法により
除去する。窒化膜５９を除去した後、ＭＯＳＦＥＴ１及
びＰＭＯＳトランジスタ５、ＮＭＯＳトランジスタ７が
形成される領域に寄生ＭＯＳトランジスタの形成を防止
するために、チャンネルカット領域を形成すべくリン及
びボロン等のイオン注入を行なう（第２図（Ｅ））。The unnecessary polysilicon 53 is removed by photoetching, leaving the polysilicon 53 forming the MOSFET gate electrode 27.
form 7. Next, an oxide film 57 and a nitride film 159 are sequentially formed on the surface, and the nitride film 159 in a portion where a LOCO8II film 61 to be described later will be formed is removed by photoetching. After removing the nitride film 59, ions such as phosphorus and boron are implanted to form a channel cut region in order to prevent the formation of parasitic MOS transistors in the region where the MOSFET 1, PMOS transistor 5, and NMOS transistor 7 are to be formed. (Figure 2 (E)).
■窒化１１１５９をマスクとしてＬＯＣＯ８ＩＩｔ化膜
６１を形成した後、窒化膜５９及び酸化１１１５７をフ
ォトエツチング法により除去し、ＰＭＯＳトランジスタ
５及びＮＭＯＳトランジスタ７のゲート酸化膜３７を形
成し、ＰＭＯＳトランジスタ５及びＮＭＯＳ トランジ
スタ７において所望のしきい値電圧を得るためにボロン
等のイオン注入を行なう（第２図（Ｆ））。■After forming the LOCO8IIIt film 61 using the nitride 11159 as a mask, the nitride film 59 and the oxide 11157 are removed by photoetching, and the gate oxide film 37 of the PMOS transistor 5 and the NMOS transistor 7 is formed. In order to obtain a desired threshold voltage in the transistor 7, ions such as boron are implanted (FIG. 2(F)).
■ゲート酸化１１３７の上にポリシリコンを堆積させリ
ン等をドープして抵抗を下げた後、フォトエツチング法
によりＰＭＯＳゲート電極３９及びＮＭＯＳゲート電極
４７を形成する。次にＮＭＯＳソース領域４５、ＮＭＯ
Ｓドレイン領域４３及びＭＯＳＦＥＴソース領域１７を
形成すべくリン等のイオン注入を行なう。またＰＭＯＳ
ソース領域３３、ＰＭＯＳドレイン領域３５及びＭＯＳ
ＦＥＴ１のソースコンタクト領域１９を形成すべくボ
ロン等のイオン注入を行なう（第２図（Ｇ））。(2) After polysilicon is deposited on the gate oxide 1137 and doped with phosphorus or the like to lower the resistance, a PMOS gate electrode 39 and an NMOS gate electrode 47 are formed by photoetching. Next, the NMOS source region 45, the NMOS
Ions such as phosphorus are implanted to form the S drain region 43 and the MOSFET source region 17. Also PMOS
Source region 33, PMOS drain region 35 and MOS
Ions such as boron are implanted to form the source contact region 19 of the FET 1 (FIG. 2(G)).
０ＭＯ８ＦＥＴ１とＣＭＯ８回路部３とを分離すべく、
ＬＯＣＯ８Ｉｌｉ化膜６１をマスクとしてフォトエツチ
ング法によりｎエビＪ１１３．０１基板１１を順次エツ
チングして分離用内部酸化膜５１に達する分離溝４９を
形成する（第２図（Ｈ））。In order to separate the 0MO8FET1 and the CMO8 circuit section 3,
Using the LOCO8Ili film 61 as a mask, the n-Ebi J113.01 substrate 11 is sequentially etched by photoetching to form an isolation groove 49 that reaches the isolation internal oxide film 51 (FIG. 2(H)).
０Ｍ ＯＳ Ｆ Ｅ Ｔ １とＣＭＯ３回路部３とを電
気的に絶縁すべく、絶縁物例えばスピオングラスにより
分離溝４９を埋めるとともに中間絶縁膜２９を表面に形
成する（第２図（Ｉ））。In order to electrically insulate the 0MOS FET 1 and the CMO3 circuit section 3, the isolation trench 49 is filled with an insulating material such as spion glass, and an intermediate insulating film 29 is formed on the surface (FIG. 2(I)).
■コンタクトホールを開孔し、スパッタ法によリアルミ
ニウムを被着させ、このアルミニウムをフォトエツチン
グ法によりバターニングを行ないアルミ配線２１を形成
する。最後に半導体装置の表面全体にパッシベイション
１１３１を被着させ、ポンディングパッド部の開孔を行
ない、第１図に示す如く完成する（第２図（Ｊ））。(2) Contact holes are opened, real aluminum is deposited by sputtering, and the aluminum is patterned by photoetching to form aluminum wiring 21. Finally, a passivation layer 1131 is applied to the entire surface of the semiconductor device, and a hole is formed at a bonding pad portion to complete the semiconductor device as shown in FIG. 1 (FIG. 2 (J)).
第３図は、この発明の他の実施例に係る半導体装置を示
す一部断面図である。その特徴としては、前記第１図に
示す半導体装置に対して、分離溝４９の側壁にアルミ配
線２１を設けて、このアルミ配置１２１とＣＭＯ８回路
部３が形成されている０１基板１１とにコンタクトをと
り、アルミ配線２１をグランドに接続し、前記ｎ＋基板
１１をグランドレベルに固定するようにしたことにあり
、他の構成は第１図に示した半導体装置と同じである。FIG. 3 is a partial cross-sectional view showing a semiconductor device according to another embodiment of the invention. Its feature is that, in the semiconductor device shown in FIG. The aluminum wiring 21 is connected to the ground, and the n+ substrate 11 is fixed at the ground level.The other configurations are the same as the semiconductor device shown in FIG.
このような構成とすることにより、周辺回路例えばＣＭ
Ｏ８回路部３が形成されているｎ２基板１１を確実にグ
ランドレベルに固定して、ＭＯＳＦＥＴ１とＣＭＯ８回
路部３とを電気的に完全に分離することができるので、
ＭＯＳ Ｆ Ｅ Ｔ １のドレイン電圧の変化がＣＭＯ
８回路部３の動作に与える影響を防止することができる
。なお、第３図において、前記第１図と同符号のものは
同一物を示し、その説明は省略した。With such a configuration, peripheral circuits such as CM
Since the N2 substrate 11 on which the O8 circuit section 3 is formed can be reliably fixed to the ground level, the MOSFET 1 and the CMO8 circuit section 3 can be electrically completely isolated.
The change in drain voltage of MOS FET 1 is CMO
The influence on the operation of the 8-circuit unit 3 can be prevented. In FIG. 3, the same reference numerals as in FIG. 1 indicate the same components, and the explanation thereof will be omitted.
［発明の効果］
以上説明したように、この発明によれば、絶縁体層を有
する基板上に形成された所謂縦型ＭＯＳトランジスタと
集積回路とを、縦型ＭＯＳトランジスタと集積回路との
間に形成され、基板表面から絶縁体層に至る溝により、
縦型ＭＯＳトランジスタと集積回路とを分離したので、
両者を電気的に絶縁することが可能となる。その結果、
縦型ＭＯＳトランジスタが構成されると同一の基板に構
成されつる集積回路に限定を受けず、例えばＰチャンネ
ルＭＯＳトランジスタ、ＣＭＯ８回路等自由に集積回路
を構成することが可能となり、回路設計の自由度を大幅
に広げることができる。[Effects of the Invention] As explained above, according to the present invention, a so-called vertical MOS transistor and an integrated circuit formed on a substrate having an insulating layer are connected between the vertical MOS transistor and the integrated circuit. The grooves are formed and extend from the substrate surface to the insulator layer.
Since the vertical MOS transistor and the integrated circuit are separated,
It becomes possible to electrically insulate both. the result,
When a vertical MOS transistor is configured, it becomes possible to freely configure integrated circuits such as P-channel MOS transistors and CMO8 circuits without being limited to vertical integrated circuits configured on the same substrate, increasing the degree of freedom in circuit design. can be expanded significantly.
第１図はこの発明の一実施例に係る半導体装置の断面構
造図、第２図は第１図の半導体装置の製造プロセスを示
す図、第３図はこの発明の他の実施例に係る半導体装置
の一部断面構造図である。
（図の主要な部分を表わす符号の説明）１・・・縦型Ｍ
ＯＳＦＥＴ部
３・・・横型ＣＭＯ８回路部
５・・・ＰチャンネルＭＯＳトランジスタ７・・・Ｎチ
ャンネルＭＯＳトランジスタ９・・・ｎ＋ポリシリ層
１１・・・ｎ＋基板
４９・・・分離溝
５１・・・分離用内部酸化膜
特許出願人 日産自動車株式会社区
区
Ｎ Ｎ坏
滅FIG. 1 is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram showing a manufacturing process of the semiconductor device of FIG. 1, and FIG. 3 is a semiconductor device according to another embodiment of the invention. FIG. 2 is a partial cross-sectional structural diagram of the device. (Explanation of symbols representing main parts of the figure) 1...Vertical type M
OSFET section 3...Horizontal CMO8 circuit section 5...P channel MOS transistor 7...N channel MOS transistor 9...n+ polysilicon layer 11...n+ substrate 49...isolation trench 51...separation Internal oxide film patent applicant Nissan Motor Co., Ltd.
Ward N N Kyo
Extinction
Claims (1)
積回路とを形成し、該縦型ＭＯＳトランジスタと集積回
路との間に基板表面から前記絶縁体層に至る溝を形成し
、該溝により縦型トランジスタと集積回路とを分離した
ことを特徴とする半導体装置。A vertical MOS transistor and an integrated circuit are formed on a substrate having an insulating layer, and a groove extending from the substrate surface to the insulating layer is formed between the vertical MOS transistor and the integrated circuit, and the vertical MOS transistor and the integrated circuit are formed on a substrate having an insulating layer. A semiconductor device characterized by separating a transistor and an integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60035225A JPS61196576A (en) | 1985-02-26 | 1985-02-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60035225A JPS61196576A (en) | 1985-02-26 | 1985-02-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61196576A true JPS61196576A (en) | 1986-08-30 |
Family
ID=12435896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60035225A Pending JPS61196576A (en) | 1985-02-26 | 1985-02-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61196576A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0314465A2 (en) * | 1987-10-27 | 1989-05-03 | Nec Corporation | A semiconductor device having a vertical power mosfet fabricated in an isolated form on a semiconductor substrate |
| JPH01179456A (en) * | 1988-01-06 | 1989-07-17 | Toshiba Corp | Semiconductor device |
| JPH03245565A (en) * | 1990-02-23 | 1991-11-01 | Nippon Motoroola Kk | Manufacture of intelligent power semiconductor device |
| EP0721211A2 (en) * | 1988-02-08 | 1996-07-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
-
1985
- 1985-02-26 JP JP60035225A patent/JPS61196576A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0314465A2 (en) * | 1987-10-27 | 1989-05-03 | Nec Corporation | A semiconductor device having a vertical power mosfet fabricated in an isolated form on a semiconductor substrate |
| JPH01179456A (en) * | 1988-01-06 | 1989-07-17 | Toshiba Corp | Semiconductor device |
| EP0721211A2 (en) * | 1988-02-08 | 1996-07-10 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| EP0721211A3 (en) * | 1988-02-08 | 1996-12-27 | Toshiba Kk | Semiconductor device and method of manufacturing the same |
| JPH03245565A (en) * | 1990-02-23 | 1991-11-01 | Nippon Motoroola Kk | Manufacture of intelligent power semiconductor device |
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