JPS61196552A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS61196552A JPS61196552A JP3687785A JP3687785A JPS61196552A JP S61196552 A JPS61196552 A JP S61196552A JP 3687785 A JP3687785 A JP 3687785A JP 3687785 A JP3687785 A JP 3687785A JP S61196552 A JPS61196552 A JP S61196552A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductor layer
- film
- wiring
- wiring conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0504—14th Group
- H01L2924/05042—Si3N4
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は集積度のきわめて大きい多層配線構造の半導体
集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device having a multilayer wiring structure with an extremely high degree of integration.
（従来の技術）。(Conventional technology).
半導体集積回路装置は、その規模が益々大形化されるに
伴なって、今日では多層配線構造をとることが一般的と
なった。しかしながら、このように配Ｉ！を多層化する
場合でも、半導体装置をそれ自身は従来のプレーナ技術
を基本として製造されるので、ワイヤボンディング用の
ボンディング・パッドは、通常、最上層に位置する配線
導体と同一の構造にて形成される。この場合、一般に、
最上層に位置する配線導体は電源の幹線としての配線導
体を含むので、下層の位置する信号の配線導体（信号導
体）より厚膜とするか、または、電源幹線の線幅を広く
形成して、配線の導体抵抗を低く設定し【おくのが普通
である。特に回路動作に高速性が要求される場合には、
配線間容量の低減を考えて、最上層に位置する配線導体
は厚膜に形成される。2. Description of the Related Art As the scale of semiconductor integrated circuit devices has become larger and larger, it has become common today to adopt a multilayer wiring structure. However, in this way! Even when the semiconductor device is multilayered, the semiconductor device itself is manufactured based on conventional planar technology, so the bonding pad for wire bonding is usually formed with the same structure as the wiring conductor located on the top layer. be done. In this case, generally
The wiring conductor located on the top layer includes the wiring conductor as the main power line, so it should be made thicker than the signal wiring conductor (signal conductor) located on the lower layer, or the line width of the power main line should be made wider. It is common practice to set the conductor resistance of the wiring to a low value. Especially when high-speed circuit operation is required,
In order to reduce the capacitance between wirings, the wiring conductor located in the uppermost layer is formed to have a thick film.
（発明が解決しようとする問題点）
しかし、集積規模がそれ程に大きくなく、２層程度の多
層化ですむ間はよいが、集積規模が大きくなって３層以
上の多層構造が必要とされ、更に高速な回路動作までが
要求されるようになると。(Problem to be solved by the invention) However, while the scale of the accumulation is not that large and a multilayer structure of about two layers is fine, as the scale of the accumulation increases, a multilayer structure of three or more layers is required. Even faster circuit operation is required.
形成すべき電源配線導体の膜厚は急激に増大し。The thickness of the power supply wiring conductor to be formed increases rapidly.
信号導体との間に著しい膜厚差を生ずるようになる。す
なわち、２層程度の集積規模の間はチップ・サイズが小
さく、配線長もさ程長くなく、また、消費電力もそれ程
大きなものではないので、′電源配線抵抗によって生ず
る電源電圧変動が問題とする程に雑音余裕を減少せしめ
ることはないが、３層以上にまで集積規模があがクチツ
ブ・サイズが大きくなると、消費電力が着るしく増大し
、また、配線長も長大化するので、′ｗＬ源配線の導体
抵抗および配線間の交さ面積を余程低減しないと、電源
電圧変動による雑音余裕の低下および配線間容量の増大
という好ましからざる諸問題が生ずる。従って、集積規
模のこれ以上の大形化と高速化とが同時に要求される半
導体集積回路装置では、最上層に形成される電源配線の
導体膜厚はきわめて厚膜なものとなる。A significant difference in film thickness occurs between the signal conductor and the signal conductor. In other words, for an integrated scale of about two layers, the chip size is small, the wiring length is not very long, and the power consumption is not so large, so power supply voltage fluctuations caused by power supply wiring resistance become a problem. Although it does not significantly reduce the noise margin, as the integration scale increases to three or more layers and the chip size increases, the power consumption increases considerably and the wiring length also increases, so the 'wL source Unless the conductor resistance of the wiring and the crossing area between the wirings are significantly reduced, undesirable problems such as a reduction in noise margin due to power supply voltage fluctuations and an increase in the capacitance between the wirings will occur. Therefore, in a semiconductor integrated circuit device that is required to have a larger scale of integration and higher speed at the same time, the conductor film of the power supply wiring formed in the top layer becomes extremely thick.
ところで、このように厚膜化された最上層の配線導体に
て、従来技術に従いボンディング・パッドが形成される
と、２層程度の比較的厚膜化されていない場合と異なり
、パッド自身の膜厚がきわめて厚膜に形成されて了うの
で、圧力その他のボンディング条件の変更が要求される
。すなわち、在来品種とはボンディングの作業条件を異
にする生産技術上の新品種が生まれる。従って、従来の
配線構造をそのまま踏襲すると、多品ｍを混在させるこ
との多い現在の生産ラインの生産効率を著しく低下せし
める場合が生じるので、ボンディング条件の規格化が望
まれる。By the way, when a bonding pad is formed in accordance with the conventional technology using the thicker top layer wiring conductor, unlike the case where the film is relatively thin with only about two layers, the pad's own film becomes thinner. Because the film is so thick, changes in pressure and other bonding conditions are required. In other words, new varieties with production technology that differ from conventional varieties in bonding work conditions are created. Therefore, if the conventional wiring structure is followed as is, the production efficiency of the current production line, which often mixes a large number of products m, may be significantly reduced, so standardization of bonding conditions is desired.
本発明の目的は、上記の情況に鑑み、ボンディング条件
を在来品種の規格に合致し得るボンディング・パッド構
造を備えた厚膜化多層配線構造の半導体集積回路装置を
提供することである。In view of the above circumstances, an object of the present invention is to provide a semiconductor integrated circuit device having a thick multilayer wiring structure and having a bonding pad structure whose bonding conditions can meet the standards of conventional products.
本発明の半導体集積回路装置は、上層部に信号導体よシ
厚膜の配線導体を備える多層配線構造と。A semiconductor integrated circuit device of the present invention has a multilayer wiring structure including a signal conductor and a thick film wiring conductor in an upper layer.
前記厚膜配線導体から下層部にひき出され形成される前
記信号導体と膜厚をほぼ等しくするひき出し配線導体と
、前記ひき出し配線導体の一部に形成されるボンディン
グ・パッド部とを含む。A lead-out wiring conductor that is drawn out from the thick-film wiring conductor to a lower layer portion and has a film thickness approximately equal to that of the signal conductor, and a bonding pad portion formed in a part of the lead-out wiring conductor. .
すなわち、本発明によれば、多層配線構造の上層部に位
置する厚膜化された配線導体からは、下層の信号導体層
の位置まで配線導体がひき出され、ボンディング・パッ
ドは従来の厚膜化された配線導体に代わって、このひき
出し配線導体にて形成される。That is, according to the present invention, the wiring conductor is drawn out from the thick film wiring conductor located in the upper layer of the multilayer wiring structure to the position of the lower layer signal conductor layer, and the bonding pad is formed using the conventional thick film wiring conductor. This lead-out wiring conductor is used instead of the printed wiring conductor.
この際、このひき出し配線導体は下層の信号導体と膜厚
をほぼ等しくなし得るので、ボンディング・パッドも在
来品種と同一の膜厚に形成することができ、ボンディン
グ条件に同等に設定することができる。以下図面を参照
して本発明の詳細な説明する。At this time, since this lead-out wiring conductor can be made to have almost the same thickness as the signal conductor in the lower layer, the bonding pad can also be formed to the same thickness as the conventional product, and the bonding conditions can be set to be the same. Can be done. The present invention will be described in detail below with reference to the drawings.
第１図は本発明の一実施例を示す断面構造図であって、
ｐ形半導体基板１と、厚膜フィールド絶縁膜２と、ｎ十
埋込領域３．ｎ形のコレクタ領域４、ｐ形のベース領域
５およびｎ＋エミッタ領域６とを含み厚膜フィールド絶
縁膜の島状領域内に形成されたバイポーラ・トランジス
タと、オーム接触領域７および８を介してバイポーラ・
トランジスタと接続するアルミ配線からなる第１層目の
信号導体９と、シリコン窒化膜からなる眉間絶縁膜１０
を介し形成されたアルミ配線からなる第２層目の信号導
体１１と同じく層間絶縁膜１２を介し形成された厚膜の
アルミ配線からなる第３層目の電源の配線導体１３と、
この電源の配線導体１３から下層の第２層目信号導体１
１の位置までひき出し配線導体１４の一部に形成された
ボンディング・パッド部１５と、チップ保護膜１６とき
含む。本実施例では、ボンディング・パッド部１５が信
号導体１１と等しい膜厚のひき出し配線導体１４の一部
に形成されるので、ボンディング条件Ｆｉ２層配線構造
などの在来品種と全く同一に設定し得る。FIG. 1 is a cross-sectional structural diagram showing one embodiment of the present invention,
A p-type semiconductor substrate 1, a thick field insulating film 2, and an n-type buried region 3. A bipolar transistor formed in an island of thick field insulating film comprising an n-type collector region 4, a p-type base region 5 and an n+ emitter region 6, and a bipolar・
A first layer signal conductor 9 made of aluminum wiring connected to the transistor, and a glabella insulating film 10 made of a silicon nitride film.
A second layer signal conductor 11 made of aluminum wiring formed through the interlayer insulating film 12 and a third layer power supply wiring conductor 13 made of thick film aluminum wiring formed through the interlayer insulating film 12,
From the wiring conductor 13 of this power supply to the lower second layer signal conductor 1
It includes a bonding pad portion 15 formed on a part of the lead-out wiring conductor 14 up to the position 1, and a chip protection film 16. In this embodiment, the bonding pad portion 15 is formed on a part of the lead wiring conductor 14 having the same film thickness as the signal conductor 11, so the bonding conditions are set exactly the same as those of conventional products such as the Fi two-layer wiring structure. obtain.
第２図は本発明の他の実施例を示す断面構造図で、第１
図と共通する部分には同一符号が用いられている。FIG. 2 is a cross-sectional structural diagram showing another embodiment of the present invention.
The same reference numerals are used for parts common to the figures.
本実施例では、第３層配線は、配線抵抗を低減するため
に信号導体１７の上に導体層１３ｔ−積み重ねて厚膜化
し、電源用配線導体として用いる部分と、このように厚
膜化せず、信号導体１７だけで信号用配線導体として用
いる部分との、２種類の構造を有する。そして、引き出
し配線導体１４は信号導体１７の延長上に形成され、そ
の一部にボンディング・パッド１５が前実施例と同じよ
うに設けられる。従って、ボンディング条件も前実施例
と同様に、在来品種とほぼ同等に設定し得る。In this embodiment, the third layer wiring is made thicker by stacking a conductor layer 13t on top of the signal conductor 17 in order to reduce wiring resistance, and a portion used as a power supply wiring conductor is separated from a portion using this thicker layer. First, there are two types of structures: a portion in which only the signal conductor 17 is used as a signal wiring conductor, and a portion used as a signal wiring conductor. The lead wiring conductor 14 is formed on an extension of the signal conductor 17, and a bonding pad 15 is provided on a part thereof in the same manner as in the previous embodiment. Therefore, the bonding conditions can be set almost the same as those for conventional products, as in the previous embodiment.
第３図は現用される２層配線構造半導体集積回路装置の
断面構造図を示すもので、ボンディング・パッド部の構
造を比較するためのものである。FIG. 3 shows a cross-sectional structural diagram of a currently used two-layer wiring structure semiconductor integrated circuit device, and is used to compare the structures of bonding pad portions.
すなわち、ボンディング・パッド部１５は第２層目の配
線導体１１の一部に形成される。従って、本発明によれ
ば、３層以上に集積規模が大形化した場合でも、この在
来品種とボンディング条件においてきわめて高い整合性
ｋｖｔ！えた半纏体呆槓−Ｉ１６誠は−を４易に得るこ
とができる。That is, the bonding pad portion 15 is formed in a part of the second layer wiring conductor 11. Therefore, according to the present invention, even when the scale of integration increases to three or more layers, extremely high consistency kvt! You can easily get ``I16 Makoto'' with 4 easy steps.
以上詳廁に説明したように１本発明によれば、集積規模
を關かだ場合に生じる在来品−とのポンディ７グ作某条
件の不整合問題は完全に解決し得るので、多品種混在の
生産効率の向上に一者なる効果ｔ″萎することができる
。As explained in detail above, according to the present invention, it is possible to completely solve the problem of inconsistency in certain conditions of pondage production with conventional products, which occurs when the scale of accumulation is concerned. It is possible to have a significant effect on improving the production efficiency of mixing.
第１図は本発明の一実施例を示す断面構造図。
第２図は本発明の他の実施例を示す断面構造図。
第３図は現用される２層配線構造半導体集積回路装置の
断面構造図である。
ｌ・・・・・・半導体基板、２・・・・・・厚膜フィー
ルド絶縁膜、９・・・・・・累１ノー目の信号導体、１
１・・・・・・第２１−目の信号導体、１３・・・・・
−＠３層目の厚膜電源配縁導体、１４・・・・・・ひき
出し配線導体、１５・・・・・・ボンディング・パッド
部、１７・・・・・・第３層目の信号導体、１０，１２
・・・・・・層間絶縁膜、１６・・・・・・チップ保護
膜。FIG. 1 is a cross-sectional structural diagram showing one embodiment of the present invention. FIG. 2 is a cross-sectional structural diagram showing another embodiment of the present invention. FIG. 3 is a cross-sectional structural diagram of a currently used two-layer wiring structure semiconductor integrated circuit device. l...Semiconductor substrate, 2...Thick field insulating film, 9...1st signal conductor, 1
1...21st signal conductor, 13...
-@3rd layer thick film power supply wiring conductor, 14... Outgoing wiring conductor, 15... Bonding pad portion, 17... Third layer signal conductor, 10, 12
......Interlayer insulating film, 16...Chip protection film.
Claims (2)
層配線構造と、前記厚膜配線導体から下層部にひき出さ
れ形成される前記信号導体と膜厚をほぼ等しくするひき
出し配線導体と、前記ひき出し配線導体の一部に形成さ
れるボンディング・パッド部とを含むことを特徴とする
半導体集積回路装置。(1) A multilayer wiring structure including a wiring conductor thicker than the signal conductor in the upper layer, and a lead-out wiring conductor whose film thickness is approximately equal to that of the signal conductor formed by being drawn out from the thick-film wiring conductor to the lower layer. and a bonding pad portion formed on a portion of the lead-out wiring conductor.
とを特徴とする特許請求の範囲第（１）項記載の半導体
集積回路装置。(2) The semiconductor integrated circuit device according to claim (1), wherein the lead-out wiring conductor is also used as a signal conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3687785A JPS61196552A (en) | 1985-02-26 | 1985-02-26 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3687785A JPS61196552A (en) | 1985-02-26 | 1985-02-26 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61196552A true JPS61196552A (en) | 1986-08-30 |
Family
ID=12482010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3687785A Pending JPS61196552A (en) | 1985-02-26 | 1985-02-26 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61196552A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0191439A (en) * | 1987-06-18 | 1989-04-11 | Seiko Instr & Electron Ltd | Semiconductor device |
| JPH02170434A (en) * | 1988-12-22 | 1990-07-02 | Fuji Electric Co Ltd | Semiconductor integrated circuit device provided with bump electrode |
| JPH0330347A (en) * | 1989-06-27 | 1991-02-08 | Toshiba Corp | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51132764A (en) * | 1975-05-14 | 1976-11-18 | Hitachi Ltd | Semiconductor device |
-
1985
- 1985-02-26 JP JP3687785A patent/JPS61196552A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51132764A (en) * | 1975-05-14 | 1976-11-18 | Hitachi Ltd | Semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0191439A (en) * | 1987-06-18 | 1989-04-11 | Seiko Instr & Electron Ltd | Semiconductor device |
| JPH02170434A (en) * | 1988-12-22 | 1990-07-02 | Fuji Electric Co Ltd | Semiconductor integrated circuit device provided with bump electrode |
| JPH0330347A (en) * | 1989-06-27 | 1991-02-08 | Toshiba Corp | Semiconductor device |
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