JPS63152137A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS63152137A
JPS63152137A JP61300761A JP30076186A JPS63152137A JP S63152137 A JPS63152137 A JP S63152137A JP 61300761 A JP61300761 A JP 61300761A JP 30076186 A JP30076186 A JP 30076186A JP S63152137 A JPS63152137 A JP S63152137A
Authority
JP
Japan
Prior art keywords
chip
terminals
edge
contact
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61300761A
Other languages
Japanese (ja)
Other versions
JPH0546977B2 (en
Inventor
Tadashi Ozawa
小沢　正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61300761A priority Critical patent/JPS63152137A/en
Publication of JPS63152137A publication Critical patent/JPS63152137A/en
Publication of JPH0546977B2 publication Critical patent/JPH0546977B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent any edge short-circuit from occurring even if any chip edge corners of metallic fine wires come into contact with one another by a method wherein, within a dicing region adjacent to bonding terminals, impurity partial diffused regions forming a PNP junction are formed. CONSTITUTION:Bonding terminals 12 connected to an element by inner wirings 13 are provided on the peripheral surface of a chip 10 while one ends of Al fine wires are connected to the terminals 12 and the other ends are connected to inner ends of lead terminals of an outer container. The bonding terminals 12 are provided on a field oxide film 4; a dicing region 11 of a part of thin oxide film 5 following the chip edge of film 4 is formed into an N type epitaxial layer 2 formed on a P type substrate 1; and P type partial diffused layers 3 are formed in the layer 2. In such an IC, even if the fine wires 14 connected to the terminals 12 come into contact with a part of substrate slightly exposed from the films 5 in case of cutting chip 10 at the chip edge corners, any edge short-circuit can be prevented from occurring even if terminals come into contact with any chip corners due to the layers 3 existing in the layer 2 as well as the PNP junction laid between the terminal 12.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明半導体チップ周辺のボンディング端子と外装容器
のリード端子との間を金属細線で接続して容器入れ組立
を行ってなる半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor integrated circuit which is assembled into a container by connecting bonding terminals around a semiconductor chip and lead terminals of an outer container using thin metal wires.

〔従来の技術〕[Conventional technology]

一般の半導体集積回路（ＩＣという）は半導体基板（ウ
ェーハ）のダイシング領域によシ区切られた多数のチッ
プ領域のそれぞれにＩＣ素子が形成され、この素子完成
後、前記ダイシング領域に沿って各チップに分割され、
分割された各チップは適当な容器に入れ該チップの周辺
に設けたボンディング端子と、容器のリード端子との間
を金属細線で接続後、密封することにより作られている
。In a general semiconductor integrated circuit (IC), an IC element is formed in each of a large number of chip areas divided by a dicing area of a semiconductor substrate (wafer), and after the element is completed, each chip is divided into
Each divided chip is placed in a suitable container, and the bonding terminals provided around the chip and the lead terminals of the container are connected with thin metal wires, and then sealed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述の容器入れ組立において、チップ上のボンディング
端子と容器のリード端子との間に接続した金属細線が往
々にしてチップのエッチと接触し、いわゆるエッヂタッ
チを起す。エッヂタッチがあると、エッチタッチした金
属細線同士が共通のダイシング領域の半導体層を通して
導通状態となり、ボンディング端子間／ヨードを引起す
。あるいは、基板とのショートとなる欠点がある。In the above-described container assembly, the thin metal wire connected between the bonding terminal on the chip and the lead terminal of the container often comes into contact with the edge of the chip, causing so-called edge touch. If there is an edge touch, the etch-touched thin metal wires become electrically conductive through the semiconductor layer in the common dicing area, causing iodine between the bonding terminals. Alternatively, it has the disadvantage of shorting with the substrate.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点に対し本発明では、チップ周辺のボンデイン
ク端子近傍のダイシング領域に、このダイシング領域の
半導体層の導電哉と反対導電型の不純物を部分的に拡散
して部分的ＰＮ接合を形成し、前記ボンディング端子に
接続した金属細線のエッヂタッチがあってもエッヂタッ
チの金属細線はダイシング領域の共通の半導体層とＰＮ
接合によシ絶縁されることによシ、エッヂタッチシ田−
トを起さなくしている。In order to solve the above problem, the present invention partially diffuses impurities of a conductivity type opposite to that of the semiconductor layer in the dicing region in the dicing region near the bonding ink terminal on the periphery of the chip to form a partial PN junction. Even if there is an edge touch of the metal thin wire connected to the bonding terminal, the edge touched metal thin wire is connected to the common semiconductor layer in the dicing area and the PN
By being insulated by bonding, edge touching is possible.
I keep it from happening.

〔実施例〕〔Example〕

つぎに本発明を実施例によシ説明する。 Next, the present invention will be explained using examples.

第１図は本発明の一実施例の平面図、第２図は第１図の
Ａ−Ａ部分断面図、第３図は第１図のＢ−Ｂ部分断面図
である。第１図において、半導体チップ１０の周囲は、
ウェーハからチップに切断したときの切断線を含んだダ
イシング領域１１により囲まれている。また、チップ上
面周辺には、素子と内部配線１３でつながるボンディン
グ端子１２が設けられ、ボンディング端子１２にはアル
ミ細線１４の一端がボンディング接続され、他端は図示
されていない外装容器のリード端子の内端部に接続され
ている。ボンディング端子１２は第２図の断面図に示す
ように、フィールド酸化膜４の上に設けられ、フィール
ド酸化膜４のチップ縁端部に続く薄い酸化膜５の部分の
ダイシング領域１１は、Ｐ型基板１の上に形成されたＮ
型エピタキシャル層２となっておシ、Ｎ型エピタキシャ
ル層２には、第２図および第３図に示されているように
Ｐ型不純物が部分的に拡散されたＰ型部分拡散層３が形
成されている。1 is a plan view of an embodiment of the present invention, FIG. 2 is a partial sectional view taken along the line AA in FIG. 1, and FIG. 3 is a partial sectional view taken along the line BB in FIG. In FIG. 1, the area around the semiconductor chip 10 is
It is surrounded by a dicing area 11 that includes the cutting line when cutting the wafer into chips. Further, a bonding terminal 12 connected to the element through an internal wiring 13 is provided around the top surface of the chip, one end of a thin aluminum wire 14 is bonded to the bonding terminal 12, and the other end is connected to a lead terminal of an outer container (not shown). Connected to the inner end. The bonding terminal 12 is provided on the field oxide film 4, as shown in the cross-sectional view of FIG. N formed on the substrate 1
In the N-type epitaxial layer 2, a P-type partial diffusion layer 3 in which P-type impurities are partially diffused is formed as shown in FIGS. 2 and 3. has been done.

このような本発明のＩＣでは、ボンディング端子１２に
接続されたアルミ細線１４がチップ縁端の角で、チップ
切断の際に酸化膜５から僅かに露出した基板部分に接触
しても、この部分はＰ型部分拡散層３が存在し、隣シ合
リボンディング端子が共にチップの角に接触していても
、両端子間にはＰＮＰの二つのＰＮ接合が介在して高イ
ンピーダンスとなっているので、エッヂショートは起ら
ない。In such an IC of the present invention, even if the thin aluminum wire 14 connected to the bonding terminal 12 comes into contact with a portion of the substrate slightly exposed from the oxide film 5 at the corner of the edge of the chip when cutting the chip, this portion will be damaged. There is a P-type partial diffusion layer 3, and even if the adjacent rebonding terminals are both in contact with the corner of the chip, two PN junctions of PNP are interposed between the two terminals, resulting in high impedance. Therefore, edge short will not occur.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明では、ボンディング端子近傍
のダイシング領域に、部分的にＰＮ接合を作る不純物部
分拡散領域が形成されているので、ボンディング端子に
接続した金属細線のチップ縁端角の接触があっても、エ
ッヂショートにはならないという効果がある。As explained above, in the present invention, a partial impurity diffusion region that partially forms a PN junction is formed in the dicing area near the bonding terminal, so that the contact of the chip edge corner of the thin metal wire connected to the bonding terminal is prevented. Even if there is, it has the effect of not causing an edge short.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の平面図、第２図および第３
図はそれぞれ第１図のＡ−ＡおよびＢ　−Ｂ部分断面図
である。 １・・・Ｐ型半導体基板、２・・・Ｎ型エピタキシャル
層、３・・・ＰＮ接合形成用部分拡散層、４・・・フィ
ールド酸化膜、５・・・薄い酸化膜、１０・・・半導体
チップ、１１・−・ダイシング領域、１２・・・ボンデ
ィング端子、１３・・・内部配線、１４・・・アルミ細
線０刃 躬ｊス 第２図　　　　　　　拍３図FIG. 1 is a plan view of one embodiment of the present invention, FIG. 2 and FIG.
The figures are partial cross-sectional views taken along lines A-A and B-B in FIG. 1, respectively. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N-type epitaxial layer, 3... Partial diffusion layer for PN junction formation, 4... Field oxide film, 5... Thin oxide film, 10... Semiconductor chip, 11...Dicing area, 12...Bonding terminal, 13...Internal wiring, 14...Aluminum thin wire 0 blades Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 半導体ウェーハのダイシング領域に沿って各チップに分
割された半導体チップを外装容器に入れリード付け組立
を行ってなる半導体集積回路において、前記チップ上の
周辺に設けられているボンディング端子近傍の前記ダイ
シング領域には、部分的にＰＮ接合を作る不純物が拡散
されていることを特徴とする半導体集積回路。In a semiconductor integrated circuit in which a semiconductor chip is divided into individual chips along a dicing area of a semiconductor wafer and is placed in an outer container and assembled with leads, the dicing area is near a bonding terminal provided on the periphery of the chip. A semiconductor integrated circuit characterized in that an impurity that forms a PN junction is partially diffused.
JP61300761A 1986-12-16 1986-12-16 Semiconductor integrated circuit Granted JPS63152137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61300761A JPS63152137A (en) 1986-12-16 1986-12-16 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61300761A JPS63152137A (en) 1986-12-16 1986-12-16 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS63152137A true JPS63152137A (en) 1988-06-24
JPH0546977B2 JPH0546977B2 (en) 1993-07-15

Family

ID=17888779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61300761A Granted JPS63152137A (en) 1986-12-16 1986-12-16 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS63152137A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5159566U (en) * 1974-11-01 1976-05-11
JPS52104055A (en) * 1976-02-27 1977-09-01 Hitachi Ltd Semiconductor device
JPS60195944A (en) * 1984-03-19 1985-10-04 Hitachi Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5159566U (en) * 1974-11-01 1976-05-11
JPS52104055A (en) * 1976-02-27 1977-09-01 Hitachi Ltd Semiconductor device
JPS60195944A (en) * 1984-03-19 1985-10-04 Hitachi Ltd Semiconductor device

Also Published As

Publication number Publication date
JPH0546977B2 (en) 1993-07-15

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