JPS61195504U - - Google Patents

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Publication number
JPS61195504U
JPS61195504U JP5780885U JP5780885U JPS61195504U JP S61195504 U JPS61195504 U JP S61195504U JP 5780885 U JP5780885 U JP 5780885U JP 5780885 U JP5780885 U JP 5780885U JP S61195504 U JPS61195504 U JP S61195504U
Authority
JP
Japan
Prior art keywords
signal
input terminal
input terminals
analog switch
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5780885U
Other languages
Japanese (ja)
Other versions
JPH0535480Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5780885U priority Critical patent/JPH0535480Y2/ja
Publication of JPS61195504U publication Critical patent/JPS61195504U/ja
Application granted granted Critical
Publication of JPH0535480Y2 publication Critical patent/JPH0535480Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本考案一実施例の回路ブロツク図、
第2図はアナログスイツチを利用したミユーテイ
ング回路の回路ブロツク図、第3図はノイズの発
生を示す波形図である。 17……アナログスイツチ、R……抵抗(イン
ピーダンス素子)、C……コンデンサ。
FIG. 1 is a circuit block diagram of an embodiment of the present invention.
FIG. 2 is a circuit block diagram of a muting circuit using an analog switch, and FIG. 3 is a waveform diagram showing noise generation. 17...Analog switch, R...Resistor (impedance element), C1 ...Capacitor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 制御信号により2つの入力端子のうち一方を選
択して出力するアナログスイツチと、一方の入力
端子に信号を供給する手段と、前記2つの入力端
子間を直流的に接続するインピーダンス素子と、
信号が供給されていなろ他方の入力端子を交流的
に接地する手段とよりなるミユーテイング回路。
an analog switch that selects and outputs one of two input terminals in response to a control signal, means for supplying a signal to one input terminal, and an impedance element that connects the two input terminals in a DC manner;
A muting circuit consisting of means for AC-grounding the other input terminal to which a signal is not supplied.
JP5780885U 1985-04-18 1985-04-18 Expired - Lifetime JPH0535480Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5780885U JPH0535480Y2 (en) 1985-04-18 1985-04-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5780885U JPH0535480Y2 (en) 1985-04-18 1985-04-18

Publications (2)

Publication Number Publication Date
JPS61195504U true JPS61195504U (en) 1986-12-05
JPH0535480Y2 JPH0535480Y2 (en) 1993-09-08

Family

ID=30582691

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5780885U Expired - Lifetime JPH0535480Y2 (en) 1985-04-18 1985-04-18

Country Status (1)

Country Link
JP (1) JPH0535480Y2 (en)

Also Published As

Publication number Publication date
JPH0535480Y2 (en) 1993-09-08

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