JPH0160000U - - Google Patents
Info
- Publication number
- JPH0160000U JPH0160000U JP15579887U JP15579887U JPH0160000U JP H0160000 U JPH0160000 U JP H0160000U JP 15579887 U JP15579887 U JP 15579887U JP 15579887 U JP15579887 U JP 15579887U JP H0160000 U JPH0160000 U JP H0160000U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- input
- switching element
- output terminal
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Electronic Switches (AREA)
Description
第１図は、本考案の一実施例を示す回路図、第
２図は、第１図の回路の各部の信号を示す波形図
、第３図は、従来のサンプル・ホールド回路を示
す回路図、第４図は、第３図の回路の各部の信号
を示す波形図である。
主要部分の符号の説明、１，２……ＦＥＴ、３
……演算増幅器、４……制御信号発生回路、Ｃ１
，Ｃ２……コンデンサ、Ｒ１，Ｒ２……抵抗。
Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a waveform diagram showing signals of each part of the circuit of Fig. 1, and Fig. 3 is a circuit diagram showing a conventional sample-and-hold circuit. , FIG. 4 is a waveform diagram showing signals of each part of the circuit of FIG. 3. Explanation of symbols of main parts, 1, 2...FET, 3
...Operation amplifier, 4...Control signal generation circuit, C1
, C 2 ... Capacitor, R 1 , R 2 ... Resistor.
Claims (1)
つ制御入力端子に供給される制御信号に応じてオ
ンとなるスイツチング素子を有し、前記スイツチ
ング素子のオフ時に前記入力信号の前記スイツチ
ング素子のオフ直前の瞬時レベルに応じたレベル
を保持して出力するサンプル・ホールド回路であ
つて、前記制御信号に対して逆相の信号の微分信
号を前記スイツチング素子の他方の入出力端子に
供給する逆相信号供給手段を備えたことを特徴と
するサンプル・ホールド回路。 (2) 前記逆相信号供給手段は、前記制御信号と
振幅が等しくかつ前記制御信号に対して逆相の信
号を発生する信号発生手段と、前記信号発生手段
の出力端子と前記スイツチング素子の他方の入出
力端子間に接続されかつ前記スイツチング素子の
他方の入出力端子と制御入力端子間の浮遊容量に
等しい静電容量を有するコンデンサとからなるこ
とを特徴とする実用新案登録請求の範囲第１項記
載のサンプル・ホールド回路。[Claims for Utility Model Registration] (1) It has a switching element that is supplied with an input signal to one input/output terminal and is turned on in response to a control signal supplied to a control input terminal, and when the switching element is turned off, A sample-and-hold circuit that holds and outputs a level corresponding to the instantaneous level of the input signal immediately before the switching element is turned off, and outputs a differential signal of a signal having an opposite phase with respect to the control signal to the other switching element. A sample/hold circuit characterized in that it is provided with means for supplying a negative phase signal to an input/output terminal of the circuit. (2) The negative phase signal supply means includes a signal generating means for generating a signal having an amplitude equal to that of the control signal and having a reverse phase with respect to the control signal, and the other of the output terminal of the signal generating means and the switching element. and a capacitor connected between the input and output terminals of the switching element and having a capacitance equal to the stray capacitance between the other input and output terminal of the switching element and the control input terminal. Sample and hold circuit as described in section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15579887U JPH0160000U (en) | 1987-10-12 | 1987-10-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15579887U JPH0160000U (en) | 1987-10-12 | 1987-10-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0160000U true JPH0160000U (en) | 1989-04-14 |
Family
ID=31433745
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15579887U Pending JPH0160000U (en) | 1987-10-12 | 1987-10-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0160000U (en) |
-
1987
- 1987-10-12 JP JP15579887U patent/JPH0160000U/ja active Pending