JPS61196332U - - Google Patents

Info

Publication number
JPS61196332U
JPS61196332U JP7452885U JP7452885U JPS61196332U JP S61196332 U JPS61196332 U JP S61196332U JP 7452885 U JP7452885 U JP 7452885U JP 7452885 U JP7452885 U JP 7452885U JP S61196332 U JPS61196332 U JP S61196332U
Authority
JP
Japan
Prior art keywords
input
output
mode
terminals
switched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7452885U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7452885U priority Critical patent/JPS61196332U/ja
Publication of JPS61196332U publication Critical patent/JPS61196332U/ja
Pending legal-status Critical Current

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  • Input From Keyboards Or The Like (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案によるキイー入力回路の一実施
例を示す回路図、第2図はそのマイコン内の要部
の構成を簡略化して示す回路図、第3図は上記実
施例の動作タイムチヤートである。 1……マイコン、P〜P……入出力兼用端
子、K〜K20……キイースイツチ。
Fig. 1 is a circuit diagram showing an embodiment of the key input circuit according to the present invention, Fig. 2 is a circuit diagram showing a simplified configuration of the main parts in the microcomputer, and Fig. 3 is an operation time chart of the above embodiment. It is. 1...Microcomputer, P0 to P4 ...Input/output terminals, K1 to K20 ...Key switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力モードと出力モードとに切換可能なn個の
入出力兼用端子を備えるマイコンを使用し、その
n個の端子のうち各1個と残りの(n―1)との
間にそれぞれ1個づつキイースイツチを接続する
と共に、前記n個の端子、入力モードの状態から
一定出力を導出する出力モードの状態に1個づつ
選択的に切換えて行き、その出力モードに切換ら
れた端子から上記出力が投入されたキイースイツ
チを介して入力モードの端子に印加されるように
してなるキイー入力回路。
A microcomputer with n input/output terminals that can be switched between input mode and output mode is used, and one terminal is placed between each one of the n terminals and the remaining (n-1). While connecting the key switch, the n terminals are selectively switched one by one from the input mode state to the output mode state that derives a constant output, and the above output is input from the terminal switched to the output mode. The key input circuit is configured such that the voltage is applied to the input mode terminal via the key switch.
JP7452885U 1985-05-20 1985-05-20 Pending JPS61196332U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7452885U JPS61196332U (en) 1985-05-20 1985-05-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7452885U JPS61196332U (en) 1985-05-20 1985-05-20

Publications (1)

Publication Number Publication Date
JPS61196332U true JPS61196332U (en) 1986-12-08

Family

ID=30614914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7452885U Pending JPS61196332U (en) 1985-05-20 1985-05-20

Country Status (1)

Country Link
JP (1) JPS61196332U (en)

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