JPS61194884A - Superconductive element ic - Google Patents

Abstract

PURPOSE:To make integration of superconductive elements such as three terminals etc. at high grade by a method wherein a metallic film and an insulated film are formed on a substrate, and an element is constituted of a superconductive metallic film and a semiconductor thin film possessing a restricted region on said insulated film. CONSTITUTION:An IC is constituted of a metallic film 101, an insulated film 102, a superconductive metal 103 and an island semiconductor thin film 104, which are wiring layers, on a substrate 100. A superconductive three terminal element is designated as a gate insulated film 102t, which is a portion where the film thickness of the insulated film 102 is made selectively thin, and the metallic layer 101 on the substrate 100 side is designated as a gate electrode 101t. The island semiconductor thin film 104 on the gate insulated film 102t becomes a channel layer 104t, then the superconductive metal 103 formed so as to cover the thin film 104t becomes superconductive electrodes 103t, 103t'. A superconductive electron pair is saturated out of the electrode 103t, 103t' to the channel layer 104t and then flows over the surface of the channel layer 104t. The flow of the electron pair is controlled by voltage impressed on a gate electrode 101t.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a superconducting element integrated circuit, and in particular to highly integrating switching elements and Josephson elements that control superconducting current flowing at the interface between a semiconductor and a superconducting metal. Related to superconducting element integrated circuits.

[Background of the invention]

Superconducting switching elements are well known in the art;
It is represented by the Josephson element. A Josephson device is a device in which a zero-voltage current flows between two superconductors separated by a very thin tunnel barrier, and this can be reduced by increasing the current flowing through the device or by applying a magnetic field to the device. The device can be switched from a superconducting state to a voltage state. Josephson elements consume low power and switch at high speed, achieving high performance switching performance, but they also have drawbacks such as low circuit gain and the inability to form negative circuits. In order to compensate for these shortcomings, a superconducting three-terminal device that utilizes the interface of a conductor in a semiconductor device has been proposed (November 1, 1981).
Nikkei Sangyo Shimbun, Nikkan Kogyo Shimbun, Nippon Kogyo Shimbun, Dempa Shimbun, Nihon Keizai Shimbun) dated 0. This superconducting three-terminal element has a structure in which two adjacent superconducting electrodes are brought into contact with a semiconductor, and a control electrode is provided on the back surface of the semiconductor with an insulating film interposed therebetween.

In this element, the superconducting current flowing between the two superconducting electrodes due to the superconducting electron pairs seeping into the halves from the superconductor is controlled by the voltage applied to the control electrode. This element has performance equivalent to that of a Josephson element, can obtain a high gain, and can also be configured as a negative circuit. However, in the structure of this superconducting three terminal, a hole is formed by etching the back surface of a semiconductor wafer, and a control electrode is provided at the bottom of the hole. Generally, the thickness of semiconductor wafer is 500μ
In order to drill a hole that reaches from the back surface of a semiconductor wafer of this thickness to near the front surface, a hole size that is approximately the same as the thickness of the wafer is required. Therefore, in the conventional element structure, the element size becomes large. Furthermore, this superconducting three-terminal element does not have a planar structure. Therefore, in the conventional structure of a superconducting three-terminal element, the elements were highly integrated on the inner wall.6 [Object of the Invention] The present invention aims to highly integrate elements such as a superconducting three-terminal element. .

[Summary of the invention]

In order to achieve this object, the present invention forms a metal film and an insulating film on a substrate, and forms an element on the insulating film by a superconducting metal film and a semiconductor thin film having a limited area. By forming the element in this manner, the element has a planar structure and can be highly integrated. To form a superconducting three-terminal element, the thickness of the insulating film in the area where the element is formed is made thinner, and a metal film is used as the control electrode. Then, the semiconductor thin film portion is used as a channel layer, and the superconducting metal film is used as a source/drain electrode.

Since this superconducting three terminal has a planar structure, it can be highly integrated. Moreover, by configuring this superconducting three-terminal element, a Josephson element, a semiconductor element, etc. on the same chip, a high-performance superconducting element integrated circuit that takes advantage of their mutual characteristics can be realized.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a cross-sectional view of a superconducting element integrated circuit which is an embodiment of the present invention. In this embodiment, a superconducting three-terminal element T, a diffused resistor D, a metal thin film resistor R1, and a capacitor C are integrated on one substrate. This integrated circuit basically has the following membrane structure. That is, a substrate 100 on which each element is formed, a metal film 101 which is a wiring layer, and an insulating film 102 formed on this metal film 101.
The superconducting metal 103 formed on this insulating film 102 is made of an inorganic material such as silicon or polysilicon, or an organic material such as resin. The metal film 101 is AQ.

Insulating materials such as silicon, silicon compounds such as silicon nitride, and resins are used. As the superconducting metal 103, a pb-based gold metal material, an Nb-based metal material, or the like is used. As the semiconductor thin film 104, S i ,
G a , G a P , G a As .

Materials such as GaSb, InP, InAs, and InSb are used. These are preferably m-crystalline, but may be polycrystalline or amorphous. In addition, this semiconductor thin film was doped with impurities of 10
For example, in the case of Si, B and P are added as impurities.

As, etc. are used. In addition, in this embodiment, a protective film 105 for protecting each element and a metal film 1 as a wiring layer are also used.
An insulating film 106 and the like are formed to insulate the substrate 10o from the substrate 10o. When the substrate 100 is made of a material that becomes an insulator at extremely low temperatures, the insulating film 106 can be omitted.

Next, the configuration of the superconducting three-terminal element T, which is a basic element of the superconducting element integrated circuit of the present invention, will be explained.

In the superconducting three-terminal element, a portion where the thickness of the insulating film 102 is selectively reduced is defined as a gate insulating film 102t.

The metal film 101 on the substrate 100 side is connected to the gate electrode 101t.
shall be. Then, an island-shaped semiconductor thin film 104 on top of the gate insulating film 102' becomes a channel layer 104t, and a superconducting metal 103 formed so as to cover this semiconductor thin film 104t.
is the superconducting electrode 103t.

103t'. Superconducting electrodes 103t, 103t'
are formed at narrow intervals of, for example, 0.2 μm. A channel layer 104 is formed from the superconducting electrodes 103t and 013t'.
Superconducting electron pairs seep out at t, and these superconducting electron pairs flow on the surface of the channel layer 104t between the superconducting electrodes. The flow of superconducting electron pairs can be controlled by the voltage applied to the gate electrode 101t.

That is, in this superconducting three-terminal element, the superconducting electrode 10
3t and 103t' are connected by superconducting weak coupling when cooled below the transition temperature of the superconducting electrode material, and therefore the maximum Josephson current Im flowing between the two superconducting electrodes is I m == 4 sΔ/2eR.

is given by Here, Δ is the superconducting electrode 103t.

103t' gap energy, e is elementary charge, R, I
is the normal conducting tunnel resistance of the superconducting weak coupling. In addition,
The distance between the two superconducting electrodes 103t and 103t' is selected to be 300 nm or less in order to form a superconducting weak bond, and it is desirable that the two electrodes are spatially separated.

A superconducting electrode 103 or 103 is attached to the gate electrode 101t.
When a negative or positive voltage is applied to t', a charge is induced in the channel layer 104t and the insulating film 102t, and the state of the tunnel barrier 7 changes due to this charge, and R becomes even more Since the value changes to a large value, the maximum Josephson current In that can flow between the electrodes 103t and 103t' without generating a voltage decreases. Note that the gate electrode 101t is formed in the through hole 1 provided in the insulating film 102.
Metal film 103 formed on insulating film 102 via 07
r', and is connected to other elements. Also,
The superconducting electrodes 103t and 103t' are connected to the metal films 110 and 111 formed on the insulating film 108 through the through holes 109 and 109' of the insulating film 108 formed on the superconducting metal 103 and the semiconductor thin film 104, respectively. , and are connected to other elements.

Since the element is constructed by providing a semiconductor thin film serving as a channel layer separately from the substrate, the superconducting three-terminal element T has a planar structure and can be highly integrated.

Furthermore, integration with other elements becomes easy.

The diffused resistor integrated on the same substrate as this superconducting three-terminal element T is a semiconductor thin film [104d
Metal 111103 which is the electrode film connected to both ends of this
d and 103d', and 103d is connected to the superconducting electrode 103t'.

Further, the metal thin film resistor R is a metal film 103r as an electrode film on both ends of the metal resistive thin film 112 formed on the insulating film 102.
, 103r' are connected. As the material of the metal resistive thin film, a normal conductive metal material 5 such as A u +
A K g M o t Cr + A Q +Ta
, Nb, and W are used.

The capacitance C is made by forming a metal film 103c as an electrode above and below a portion 102C where Al 11102 is selectively thinned.

101c. In addition, metal film 1
01' is used as a wiring. In this way, the board 1
00, metal film 101, insulating film 102, superconducting metal film 10
3. By using the island-shaped semiconductor thin film 104 as a basic component of the superconducting element integrated circuit, the superconducting three-terminal element and other elements can all be formed on the surface of the substrate, making it possible to integrate them in a single hole. becomes. Furthermore, this embodiment has an ideal structure in which all the elements are embedded in an insulating cylinder, so that the parasitic capacitance is reduced and the elements operate at high speed.

Next, an example of a process for manufacturing a superconducting two-terminal element 1'', which is a basic element of the superconducting element integrated circuit shown in FIG. 1, will be explained using FIG. 2.

An oxide film layer that will become the insulating film 102 is formed on the silicon single crystal substrate 200, and a part of the oxide film layer is selectively thinned to form gate insulation n! Form the part that will become J102t.

This oxide film structure can be obtained, for example, by thermally oxidizing the silicon single crystal surface to create a thick oxide film, selectively etching the oxide film, and then creating a thin oxide film. In this example, the thickness of the insulating film 102 was 2000, and the thickness of the gate insulating film was 200 (FIG. 2(a)).

Thereafter, ions are implanted to contain boron of about 10@19 -2 to form a channel layer 104' which becomes an island-shaped semiconductor thin film 104 (FIG. 2(b)). Thereafter, a gate electrode t4101t is produced by forming 3000 metal films 101 (FIG. 2(C)). Further, a vacuum 106 and a substrate 100 are laminated on the surface thereof. The thickness of the substrate was set to about 200 μm (Figure 2 (d)).
). In this state, silicon single crystal substrate 200 is etched from the back side. For example, by using anisotropic etching of silicon, only the part with a low impurity concentration is etched, and the channel layer 104' with a high impurity concentration is etched.
You can leave only the

In this embodiment, the thickness of the channel layer 104' was set to 1000 by the above-mentioned ion implantation and etching. still,
At this point, the channel layer 104' is exposed (FIG. 2(e)
)). After that, the channel layer 104' is selectively etched,
A portion of the channel layer 104t of the superconducting three-terminal element T is formed (FIG. 2(f)). After that, the insulating film 102 is selectively etched to form a through hole 107, and a metal resistive thin film 112 is further formed (FIG. 2(g)). Thereafter, a metal ff1103r' connected to the gate electrode 102t, a superconducting electrode 103t, The metal film with a thickness of 103t' is 300
Form 0 people. Also 5 superconducting tli 103t and 10
The interval of 3t' was set to 200 nm (Fig. 2 (
h)). After this, the through 3M holes 109, 1 were selectively formed.
09' is produced. Then, superconducting electrodes 103t, 1031 are placed on the absolute R film 108;
'A gold a film 110° 111 connected to To form these shapes, a lift-off method, an etching method, etc. may be used (FIG. 2(i)). After this, the protective film 105 is
By forming this, a superconducting three-terminal element, which is a basic element of the superconducting element integrated circuit shown in FIG. 1, can be constructed. still.

The steps shown in FIG. 2 are representative examples, and the superconducting element integrated circuit shown in FIG. 1 can be manufactured by changing the order of the steps or using other methods. For example, it is possible to form the channel layer 104' by performing the ion implantation shown in FIG. 2(b) before forming the insulating film 102 shown in FIG. 2(a). Furthermore, when ion implantation is selectively performed in FIG. 2(b) and the silicon single crystal substrate 200 is etched in FIG. 2(e), it is also possible to directly form silicon single crystal islands that will become the channel layer 104t. be. Furthermore, the channel layer 104t may be formed using MBE technology, laser annealing technology, or the like.

Other embodiments of the present invention are shown in FIGS. 3 to 8.

In the embodiment shown in FIG. 3, the superconducting three-terminal element T and the island-shaped silicon single crystals 304t and 304d of the diffused resistor are made into high concentration parts, and the other part 313 is made into a low concentration single crystal. That is, the channel layer 30 of the superconducting three-terminal element T
4 etc. are embedded in the low concentration area.

The low concentration portion 313 of the silicon single crystal becomes an insulator at an extremely low temperature, for example, the temperature of liquid helium, and an insulator is sandwiched between the elements, so that element isolation is possible. For example, in FIG. 2(f), instead of etching the single crystal portion 104', this is fabricated by ion-implanting an impurity having the opposite property to the impurity of the channel layer 104t into the low concentration portion 313.

In the embodiment shown in FIG. 4, the Josephson junction J is integrated with the superconducting three-terminal element T shown in FIG. 1, etc. The Josephson junction J connects the lower electrodes 403 and 401j formed by the metal film 103 and the upper electrode 415j formed by the metal film 415 through the tunnel barrier C layer 414, and also connects the lower electrodes 403 and 401j formed by the metal film 101 to each other via the tunnel barrier C layer 414.・401j' as insulating film 1
02. The Josephson junction J can be easily created using conventional manufacturing processes such as pattern creation using a lift-off method and creation of a tunnel barrier layer using plasma oxidation. In this embodiment, a superconducting metal film 417 is formed on the insulating film 416. Superconducting metal film 417 In the embodiment shown in FIG. 5, an insulating film 518 and a superconducting metal film 519 are formed before the step in FIG. 2(d).
The superconducting metal film 519 functions as a magnetic shielding surface and a grounding surface at extremely low temperatures.

The embodiment shown in FIG. 6 is an example in which a di-MO8 element M is further integrated in the embodiment shown in FIG. An island-shaped semiconductor thin film is inserted through the through hole formed in the insulation layer.
Metal is applied to the channel layer 604m formed by 104 of
The source electrode 601m formed of the film 101, the drain
The toe-in electrode 601m' is in contact. Further, a gate electrode made of a metal film 101 is formed between the source and drain electrodes with an insulating film 102 interposed therebetween. An electrode 603m made of the metal layer 103 is provided above the channel layer 604m. Electrode 603m is channel layer 604m
It is possible to control the threshold voltage of the MO8 element by applying a bias voltage to the MO8 element. Note that the threshold value of the GeO8 element M can also be controlled by separately implanting impurity ions into the channel layer 604m and changing the impurity concentration.

Moreover, in order to connect the source electrode 601m and the rain electrode 601m' to the channel layer 604m, for example, the process shown in FIG. 2 (c) is absolutely necessary! ! 102
It is sufficient to form a through hole in the.

The embodiment shown in FIG. 7 is an example in which a junction FET 51 or S2 is further integrated in the embodiment shown in FIG. The junction FET 51 contacts the contact electrode 70181 formed of the metal film 101 from below the island-shaped semiconductor thin film 704S1 through the through hole of the insulating film 102, and above the source and drain electrodes 70181 formed of the metal film 03. 1
.

03S1' is provided. In this structure, a Schottky barrier is formed between the upper electrode 701S1 and the island-shaped semiconductor thin film 70481. Sword drain electrode 703
In order to make resistive contact between 31,703S1' and the semiconductor thin film 111704S1.

It is sufficient to further ion-implant high-concentration impurities into the portion. By having such a structure, - the upper electrode 7018
A junction FET element is obtained in which the resistance between the source and drain electrodes is controlled by the voltage applied to the junction FET. Note that if the distance between the source/drain electrodes 703S1, 703SL' is narrowed (for example, 0.2 μm), superconducting electron pairs seeping out from the source/drain electrodes 703S1, 703SL' made of superconductors into the island-shaped semiconductor thin M704S1 are reduced. It is also possible to configure a superconducting three-terminal element in which the flow is controlled by the voltage applied to the gate electrode 701S1. The junction FET 52 has the same structure as the junction FET 51, with a second gate electrode 703S2' provided between source and drain electrodes 703S2 and 703S2'. Note that the first gate electrode 701S2 is connected to the metal ff703 through a through hole in the insulating film 102, and the first
．． By connecting the second gate electrode, a high gain FET can be realized. Also number 1. If the second gate electrode is used independently as an input terminal, OR (NOR) or AND (NAND
) can perform logical operations. Note that the second gate electrode 703
Since S 2' is made of a superconductor, the flow of superconducting electron pairs leaking from the second gate electrode 703S2' to the island-shaped semiconductor thin film 704S2 is transferred to the first gate electrode 7QIS.
It is also possible to configure a superconducting three-terminal element controlled by the voltage applied to the two terminals.

The embodiment shown in FIG. 8 is an example in which a superconducting three-terminal element having a different structure from the embodiment shown in FIG. 1 is constructed.

The superconducting three-terminal element shown in this embodiment has a structure in which an electrode 803t', also formed of the metal film 103, is newly provided between the electrodes 803t, 803t' formed of the metal film 103. Since the metal film 103 is a superconducting material, the flow αg of superconducting electron pairs seeping into the electrode 803t' or the island-shaped semiconductor thin film 804t. Since a semiconductor thin film having a limited area for separately forming a superconducting three-terminal element or the like is formed, an integrated circuit-like element can have a planar structure.

Therefore, a highly integrated circuit can be realized. Furthermore, in the integrated circuit according to this embodiment, since the elements are separated by an insulating film, the parasitic capacitance thereof can be reduced, so that higher-speed switching operation can be realized.

〔Effect of the invention〕

According to the present invention, an element such as a superconducting three-terminal element can be formed into a planar structure, so that it is possible to highly integrate the elements.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a superconducting element integrated circuit that is an embodiment of the present invention, FIG. 2 is a sectional view showing an example of the manufacturing process of the superconducting element integrated circuit shown in FIG. 1, and FIGS. 3 to 8 FIG. 2 is a cross-sectional view of a superconducting element integrated circuit according to another embodiment of the present invention. 100...Substrate, 101...Metal film, 102...
Insulating film, 103...Superconducting metal film, 104...Island-shaped semiconductor thin agent Patent attorney Katsuma Ogawa figure

Claims (1)

[Claims] 1. A semiconductor thin film having at least a predetermined substrate, a metal film formed on the substrate, and an insulating film formed on the metal film, and having a superconducting metal film and a desired region. A superconducting element integrated circuit, characterized in that at least one element is constructed by forming on the insulating film. 2. A superconductor according to claim 1, comprising at least one element in which the metal film is used as a control electrode, the superconducting metal film is used as a source and drain electrode, and the semiconductor thin film is used as a channel layer. Element integrated circuit. 3. A superconducting element integrated circuit according to claim 1 or 2, characterized in that a through hole is selectively formed in the insulating film to connect the metal film and the superconducting metal film. 4. A superconducting element integrated circuit according to any one of claims 1 to 3, wherein the semiconductor thin film is a silicon single crystal thin film.