JPS6119117B2 - - Google Patents

Info

Publication number
JPS6119117B2
JPS6119117B2 JP54126114A JP12611479A JPS6119117B2 JP S6119117 B2 JPS6119117 B2 JP S6119117B2 JP 54126114 A JP54126114 A JP 54126114A JP 12611479 A JP12611479 A JP 12611479A JP S6119117 B2 JPS6119117 B2 JP S6119117B2
Authority
JP
Japan
Prior art keywords
plate
shaped molded
mold
lead frame
molded product
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54126114A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5648155A (en
Inventor
Keiji Hazama
Mitsuyoshi Nakatsuka
Shinichi Oota
Fumio Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP12611479A priority Critical patent/JPS5648155A/ja
Publication of JPS5648155A publication Critical patent/JPS5648155A/ja
Publication of JPS6119117B2 publication Critical patent/JPS6119117B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP12611479A 1979-09-27 1979-09-27 Package forming method for semiconductor Granted JPS5648155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12611479A JPS5648155A (en) 1979-09-27 1979-09-27 Package forming method for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12611479A JPS5648155A (en) 1979-09-27 1979-09-27 Package forming method for semiconductor

Publications (2)

Publication Number Publication Date
JPS5648155A JPS5648155A (en) 1981-05-01
JPS6119117B2 true JPS6119117B2 (ref) 1986-05-15

Family

ID=14926974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12611479A Granted JPS5648155A (en) 1979-09-27 1979-09-27 Package forming method for semiconductor

Country Status (1)

Country Link
JP (1) JPS5648155A (ref)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5919359A (ja) * 1982-07-23 1984-01-31 Hitachi Chem Co Ltd 半導体類のパツケ−ジ成形方法
JPS62224949A (ja) * 1986-03-27 1987-10-02 S M C:Kk Ｉｃパツケ−ジ
US5156983A (en) * 1989-10-26 1992-10-20 Digtial Equipment Corporation Method of manufacturing tape automated bonding semiconductor package
JPH06252283A (ja) * 1993-02-24 1994-09-09 Kyocera Corp 半導体装置
TW466720B (en) * 2000-05-22 2001-12-01 Siliconware Precision Industries Co Ltd Semiconductor package with flash-prevention structure and manufacture method
KR100415281B1 (ko) * 2001-06-29 2004-01-16 삼성전자주식회사 양면 실장형 회로 기판 및 이를 포함하는 멀티 칩 패키지

Also Published As

Publication number Publication date
JPS5648155A (en) 1981-05-01

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