JPS61191029A - Step exposure method - Google Patents

Abstract

PURPOSE:To prevent the influence of defect existing on a reticle onto a wafer by a method wherein when exposure is performed using a block reticle for (n) member chips, application is performed to film thickness, which is extinguished by exposure of a resist at (n-1) times but is left by exposure of the resist at (n-2) times. CONSTITUTION:When a resist 12 formed on a wafer 11 is exposed using a block reticle 41 for one - four chips 4, the resist thickness is set up so that said resist comes off and extinguished at three time exposure but does not come off at two time's exposure. At the time of exposure, the reticle 41 is stepped up at (b) distance in X direction and (a) in Y direction and exposure is performed divided by four times at each step. Accordingly, even if a chip 1 is defective and that part is not exposed, the resist 12 is exposed at three times and comes off, then influence by defect is eliminated, if the other chips 2-4 are not defective.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a step exposure method, more specifically, in exposure using two or more chips on the same reticle, defects existing on the reticle affect the wafer. Concerning an exposure method that does not give

[Conventional technology]

Conventionally, a mask was used to expose the resist on the wafer, but this is now being replaced by step exposure in which a reticle is used to expose the resist in a stepwise manner.

The main reason for this is that when a reticle is used, a good pattern can be created with good resolution.

Recently, block reticles have come into use. A block reticle is one in which two or more chip patterns are provided on the same reticle. FIG. 4(a) shows a four-chip block reticle 41 in plan view.
Patterns for four chips are formed therein, which are marked with symbols ■, ■, ■, ■. Note that the patterns for these four chips are all the same pattern. When the dimensions of the reticle are a and b in the vertical and horizontal directions as shown in the figure, when exposing a wafer using this block reticle, exposure is performed in 2b steps in the X direction and 28 steps in the Y direction.

[Problem that the invention seeks to solve]

When a wafer is exposed using the block reticle of FIG. 4 (al), the wafer is exposed by the chips shown in FIG. 4 (1). Here, if the chip in ■ is defective,
This defect is repeated in all the chips marked with (4), and the wafer becomes 1/4 defective.

Research has been conducted to find the above-mentioned defects in reticles during step exposure. According to one of them,
A glass wafer is made from quartz glass with the same dimensions as the wafer,
A thin chrome film is deposited on top of it, a resist is applied on the thin chrome film, this resist is exposed stepwise using a reticle, the resist is developed, and the thin chrome film is etched to create a chrome pattern. Inspect using a mask inspection device. However, this work is time-consuming and labor-intensive, and there is a need for efficient reticle defect countermeasures.

[Means for solving problems]

The present invention provides a step exposure method that solves the above problems, and includes a method in which a substrate coated with a resist is exposed using a block reticle for chips of flf[I, in which the resist is It disappears after (n-1) exposures, but it is applied to the remaining film thickness after (n-2) exposures, and the steps in the vertical and horizontal directions are equal to the length and width of one chip. This is done by a step exposure method characterized by exposing to light.

[Effect]

In the above method, for example, in the case of a 4-chip block reticle, the resist will come off (disappear) after three exposures, but the resist is set so that it will not come off even after two exposures, so Even if there is a defect in one chip, the probability that the same defect will exist in the same location on other chips is extremely small, so the defect will disappear or be corrected by exposing the fourth chip.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

A case will be described in which a positive resist, in which the exposed portion disappears after development and the unexposed portion remains, is exposed using a block reticle of 4 chips. Such a block reticle is the same as that shown in FIG. 4(a).

In the present invention, the thickness of the resist is set so that it disappears after three exposures, but does not come off even after two exposures.

In the exposure, referring again to FIG. 4(a), steps are performed by a distance a in the X direction and in the Y direction, and the exposure is performed so that when four exposures are performed, the exposure is equivalent to one conventional exposure.

In other words, each exposure time is reduced to 1/4 compared to the conventional method.

FIG. 1 shows a case where the defective part is not exposed to light, that is, a case where one chip out of four chips has a residue-based defect. When a certain chip has a defect and the defective portion is not exposed, when only the defective chip is developed after the first exposure, a resist 12a remains on the wafer 11 as shown in FIG.

However, when the second chip is exposed, the resist 12a
is exposed for the first time, so if only the defective chip is developed, the resist 12a becomes a small resist 12b.

When a third chip is further exposed, the resist has been exposed a second time, and resist 12b is exposed to become an even smaller resist 12c.

When the fourth chip is subsequently exposed, the resist has been exposed three times, and since the resist is set to come off after being exposed three times, the resist becomes as shown in Figure 1(d).
The effect of the defect disappears as shown in .

In the conventional example, if there is a defect, resist remains as shown in FIG. 1(e).

The case where one of the four chips has a pinhole will be explained with reference to FIG. The resist coated on the wafer 11 is represented by 13. Conventionally, as shown in FIG. 2(a), the defective portion was exposed to light and the resist was removed as shown at 14a, forming a hole 14a.

However, in the present invention, there is only one pinhole part.
As shown in the 20th peak), the thickness of the resist only becomes thinner in the area where the pinhole is located, as shown by reference numeral 14b, and the resist in the pinhole area disappears. There isn't.

The method of the present invention has been explained above using a 4-chip block reticle as an example, but the method of the present invention can also be applied to the case of a 2-chip or 3-chip block reticle as shown in FIG. This can be carried out using a block reticle with two or more chips.

Each chip of the block reticle is exposed at the same location on the wafer, so if the stepper's reduction ratio is not accurate, the patterns of each chip will not overlap correctly and the profile will be poor. Although the exposure time for each time will be shorter, the number of steps will be lower. Although there are problems such as an overall decrease in throughput and a decrease in the usable area for dicing, these problems can be solved with current technology without impairing the features of the present invention. .

〔Effect of the invention〕

As described above, according to the present invention, in step exposure using a block reticle of two or more chips, the influence of a defect existing in one chip does not become apparent, so there is no need to inspect all chips for defects.

[Brief explanation of the drawing]

FIG. 1 (al or di is a diagram showing resist development according to the method of the present invention when one chip out of four chips has a residual defect; FIG. 1 (Q) is a diagram showing resist development in a conventional example. , FIGS. 2(a) and 2(b) are diagrams showing a conventional example of resist development when the reticle has a pinhole defect and the case of the present invention, and FIG. 3 is a plan view of a 2-chip and 3-chip block reticle. FIG. 4 is a plan view of a wafer when the wafer is exposed using the block reticle shown in FIG. 4 (al is a plan view of a 4-chip block reticle, and FIG. , 12a, 12b+ 12c are resists, 13 is a resist film, 14a is a hole, and 14b is a part where the resist film thickness is reduced. Fig. 1 Fig. 2 Fig. 3 WI

Claims (1)

[Claims] In a method of exposing a substrate coated with resist using a block reticle for n chips, the resist disappears after (n-1) exposures but remains after (n-2) exposures. A step exposure method characterized in that the coating is applied to a film thickness, the vertical and horizontal steps are equal to the vertical and horizontal length of one chip, and exposure is performed for each step.