JPS61190974A - Complementary type mis field-effect semiconductor device - Google Patents
Complementary type mis field-effect semiconductor deviceInfo
- Publication number
- JPS61190974A JPS61190974A JP60263374A JP26337485A JPS61190974A JP S61190974 A JPS61190974 A JP S61190974A JP 60263374 A JP60263374 A JP 60263374A JP 26337485 A JP26337485 A JP 26337485A JP S61190974 A JPS61190974 A JP S61190974A
- Authority
- JP
- Japan
- Prior art keywords
- region
- mis
- semiconductor device
- diffusion layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 230000000295 complement effect Effects 0.000 title claims description 9
- 230000005669 field effect Effects 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 21
- 238000004519 manufacturing process Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052810 boron oxide Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- JKWMSGQKBLHBQQ-UHFFFAOYSA-N diboron trioxide Chemical compound O=BOB=O JKWMSGQKBLHBQQ-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は、相補型電界効果半導体装置に関する。[Detailed description of the invention] The present invention relates to complementary field effect semiconductor devices.
従来、ＭＩＳ電界効果半導体装置を型造するにあたり、
シリコン窒化物等の誰酸化性物質を用い半導体基板表面
の凹凸を減じ、金属配線層の欠陥を減らす方法が多用さ
れている。この方法の一例を第１図に従って説明する。Conventionally, when molding MIS field effect semiconductor devices,
A method of reducing defects in a metal wiring layer by reducing unevenness on the surface of a semiconductor substrate using an oxidizing substance such as silicon nitride is often used. An example of this method will be explained with reference to FIG.
Ｎ型シリコン基板１の一部をシリコン窒化物層２で覆い
、高温酸化性雰囲気内でシリコン窒化物１脅で覆われて
いない部分に厚い酸化シリコン喚８を成長させる（第１
図ａ）。シリコン窒化物層３を除去し、露出したシリコ
ン基板表面の一部にゲート酸化膜層４及び多結晶シリコ
ン層５を形成する（第１図ｂ）。不純物を含む雰囲気内
でソース・ドレイン拡散層６を形成する（第１図Ｃ）。A part of the N-type silicon substrate 1 is covered with a silicon nitride layer 2, and a thick silicon oxide layer 8 is grown on the part not covered with the silicon nitride layer 2 in a high temperature oxidizing atmosphere (first step).
Diagram a). The silicon nitride layer 3 is removed, and a gate oxide layer 4 and a polycrystalline silicon layer 5 are formed on a portion of the exposed silicon substrate surface (FIG. 1b). A source/drain diffusion layer 6 is formed in an atmosphere containing impurities (FIG. 1C).
ソース・ドレイン拡散層６上の酸化膜７を貫通し、ソー
ス・ドレイン拡散層６に達する孔８を開孔する（？Ｐ、
Ｉ図ｄ）。最後に金属配線層９を形成する（第１図ｅ）
。A hole 8 is opened that penetrates the oxide film 7 on the source/drain diffusion layer 6 and reaches the source/drain diffusion layer 6 (?P,
I figure d). Finally, a metal wiring layer 9 is formed (Fig. 1e)
.
以上の様に、従来の製法においては半導体基板への電気
的接続を幕板表面から取る事は困難である。なぜならば
、もし第１図ｄの工程で厚い酸化シリコン膜を貫通する
孔を開孔しようとすれば、一般にソース・ドレイン拡散
層上の酸化シリコン膜は厚いシリコン膜より数倍も薄い
為、同一の写真食刻工程では困難であった。特に相補型
ＭＩＳ電界電界製実装置いては、Ｐ＋Ｎどちらかの極性
のトランジスタの基体領域が半導体基板の裏面から絶縁
されている為に、表面から基体への電気的接続を取る事
が必要であり、これが相補型ＭＩＳ電界電界製実装置造
する場合に、シリコン９化膜等の難酸化性被膜を利用し
て等板表面の凹凸を減する方法を適用することが困難な
理由であった。又、との相補型Ｍ Ｉ Ｓ電界効果トラ
ンジスタにおいて、両極性トランジスタともに表面から
基板電極を取り出すと、該トランジスタ特有の寄生ＰＮ
ＰＮ動作すなわち、ラッチアップ現壕が発生しやすくな
る。As described above, in conventional manufacturing methods, it is difficult to make electrical connections to the semiconductor substrate from the surface of the curtain plate. This is because if an attempt is made to make a hole through a thick silicon oxide film in the process shown in Figure 1d, the silicon oxide film on the source/drain diffusion layer is generally several times thinner than the thick silicon film, so The photo-etching process was difficult. In particular, in complementary MIS electric field fabrication equipment, the base region of a transistor with either P+N polarity is insulated from the back surface of the semiconductor substrate, so it is necessary to make an electrical connection from the surface to the base. This is the reason why it is difficult to apply a method of reducing unevenness on the surface of a uniform plate by using an oxidation-resistant film such as a silicon 9ide film when manufacturing a complementary MIS electric field production device. In addition, in a complementary M I S field effect transistor, if the substrate electrode is taken out from the surface of both bipolar transistors, the parasitic PN characteristic of the transistor is
PN operation, that is, latch-up is likely to occur.
したがって本発明の目的は、上記不都合が発生しないよ
うな構成をもって、基板表面よシトランジスタの基体電
位を取り出す構造の半導体装置を提供することである。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device having a structure in which the base potential of a transistor is taken out from the surface of the substrate, and which does not cause the above-mentioned disadvantages.
本発明の特徴は、−導電型の半導体基板と、該半導体基
板に設けられたこれと逆導電型の領域と、該領域に設け
られた一方のＭＩＳトランジスタを形成するソース領域
、ドレイン領域及び接触領域と、前記半導体基板に設け
られた他方のＭＩＳトランジスタを形成するソース領域
、ドレイン領域及び接触領域とを備え、前記ＭＩＳトラ
ンジスタのうち、少なくとも一方のＭＩＳトランジスタ
に於いて、前記接触領域が前記ソース領域及びドレイン
領域よりも他方のＭＩＳトランジスタ側に位置するよう
に設けた相補型電界効果半導体装置である。ここで、前
記ＭＩＳトランジスタのうち少なくとも一方のソース領
域もしくけドレイン領域と接触領域とを少なくとも一部
分重ねて設けることができる。The present invention is characterized by - a semiconductor substrate of a conductivity type, a region of an opposite conductivity type provided on the semiconductor substrate, a source region, a drain region, and a contact forming one MIS transistor provided in the region; and a source region, a drain region, and a contact region forming the other MIS transistor provided on the semiconductor substrate, and in at least one of the MIS transistors, the contact region is connected to the source region. This is a complementary field effect semiconductor device provided so as to be located closer to the other MIS transistor than the region and the drain region. Here, the source region or the twisted drain region of at least one of the MIS transistors and the contact region can be provided to overlap at least partially.
本発明を図面を用いて詳細に説明する。The present invention will be explained in detail using the drawings.
第２図は、本発明の一実施例を工程順に示した断面図で
あｈ、Ｎ型シリコン基板１１の表面にイオン注入技術等
を用い、Ｐ型拡散層（Ｐ−ウェル）１２を選択拡散する
（第２図ａ）。基板１表面に部分的にシリコン窒化膜１
３を形成し、高温酸化性雰囲気中で厚いシリコン酸化膜
１４を成長させる（第２図ｂ）。シリコン窒化膜１３を
除去し、露出したシリコン上にＮチャネルトランジスタ
用ゲート酸化膜１５及びＰチャネルトランジスタ用ゲー
ト酸化膜１６を成長させ、その上にＮチャネルゲート電
罹用多結晶シリコン噂１７、Ｐチャネルゲート＝ｘ極用
多結晶シリコン膜１８を形成する（第２図Ｃ）。基板上
にホウ素を含んだ酸化極を成長させ、選択的にエツチン
グしてＰ−ウェル１２を覆う部分１９及び基板１を覆う
部分２ｏのみ残す。基板をリンを含む雰囲気内で熱処理
して露出したシリコン表面にＮ型拡散層２１．２２．２
４ を形成し、同時にホウ素を含んだ酸化膜１９．２０
よりホウ素を拡散し、Ｐ型拡散層２８．２５．２６ を
形成する（第２図ｄ）ｏなお、Ｎ型層２１．２２．２４
をイオン打込で形成し、Ｐ型層２Ｂ、 ２５．２６はＮ
型層とは時間的に別に形成してもよい。ホウ素を含んだ
酸化膜１９．２０ を除去した後、或いは、ホウ素を含
んだ酸化膜１９．２０を残した！！壕、拡散層２１．２
２．２３．２４．２５．２６の表面に酸化膜２７を成長
させ、拡散層２１．２２．２３．２４．２５．２６に達
する孔２８．２９．８０．８１を開孔する。酸化膜２７
は酸化膜１４より、はるかに薄いので一回の選択エツチ
ング工程で開孔可能である。開孔部２９はＮ型拡散層及
びＰ型拡散鳴への共通の開孔であり、開孔部８０はＰ型
拡散層２５及びＮ型拡散層２４への共通の開孔である。FIG. 2 is a cross-sectional view showing an embodiment of the present invention in the order of steps. A P-type diffusion layer (P-well) 12 is selectively diffused into the surface of an N-type silicon substrate 11 using ion implantation technology. (Figure 2a). Partial silicon nitride film 1 on the surface of the substrate 1
3, and a thick silicon oxide film 14 is grown in a high temperature oxidizing atmosphere (FIG. 2b). The silicon nitride film 13 is removed, and a gate oxide film 15 for an N-channel transistor and a gate oxide film 16 for a P-channel transistor are grown on the exposed silicon, and a polycrystalline silicon layer 17 for an N-channel gate current is grown thereon. A polycrystalline silicon film 18 for channel gate=x pole is formed (FIG. 2C). An oxidizing electrode containing boron is grown on the substrate and selectively etched to leave only a portion 19 covering the P-well 12 and a portion 2o covering the substrate 1. An N-type diffusion layer 21.22.2 is formed on the exposed silicon surface by heat-treating the substrate in an atmosphere containing phosphorus.
4 and at the same time contains boron oxide film 19.20
Boron is further diffused to form P-type diffusion layers 28, 25, 26 (Fig. 2 d) o In addition, N-type layers 21, 22, 24
is formed by ion implantation, P type layer 2B, 25.26 is N
It may be formed separately from the mold layer. After removing the oxide film 19.20 containing boron, or leaving the oxide film 19.20 containing boron! ! trench, diffusion layer 21.2
An oxide film 27 is grown on the surface of 2.23.24.25.26, and holes 28.29.80.81 reaching the diffusion layer 21.22.23.24.25.26 are opened. Oxide film 27
Since the oxide film 14 is much thinner than the oxide film 14, a hole can be formed in a single selective etching process. The opening 29 is a common opening to the N-type diffusion layer and the P-type diffusion layer, and the opening 80 is a common opening to the P-type diffusion layer 25 and the N-type diffusion layer 24.
Ｎ型拡散層２２．２４はＰ型拡散層２３．２６と自己整
合的に密着して形成されている為、共通の開孔部である
２９．３０は、Ｐ、Ｎ両拡散層が自己整合的でない場合
と比較して小さい面積しか必要としない（第２図ｅ）。Since the N-type diffusion layer 22.24 is formed in close contact with the P-type diffusion layer 23.26 in a self-aligned manner, the common opening 29.30 is formed so that both the P and N diffusion layers are self-aligned. It requires a smaller area compared to the non-targeted case (Fig. 2e).
最後に、金属配線層８２を選択的に形成し相互配線を行
う（第２図ｆ）。Finally, a metal wiring layer 82 is selectively formed to perform mutual wiring (FIG. 2f).
Ｎ型拡散層２２ばＮチャネルＭＩＳトランジスタのソー
スとして動作する領域で、金属配線層３２を通じて、自
己整合的に密着したＰ型拡散層２３に接続され、Ｐ−ウ
ェル１２と短絡されている。Ｐ−ウェル１２の電気的接
続をＰ型拡散層２８を通じて表面より取り出す事も容易
である。同様に、ＰチャネルＭＩＳトランジスタのソー
スとして動作するＰ型拡散層２５は、金庫配線層３２、
Ｎ型拡散層２４を通じてＮ型部板１１と短絡されている
。The N-type diffusion layer 22 is a region that operates as the source of the N-channel MIS transistor, and is connected to the P-type diffusion layer 23 in close contact in a self-aligned manner through the metal wiring layer 32, and is short-circuited to the P-well 12. It is also easy to take out the electrical connection of the P-well 12 from the surface through the P-type diffusion layer 28. Similarly, the P-type diffusion layer 25 that operates as the source of the P-channel MIS transistor is connected to the safe wiring layer 32,
It is short-circuited to the N-type part plate 11 through the N-type diffusion layer 24 .
以上のようにＰ型の高濃度領域２３をＰチャンネルトラ
ンジスタ側に位置させることにより抵抗Ｒ１が減少し、
又、Ｎ型の高濃度領域２４をＮチャンネルトランジスタ
側に位置させることによう、抵抗Ｒ２が減少する普した
がって、たとえこのように両トランジスタの某板電極を
表面から取り出しても、寄生ＰＮＰ 、寄生ＮＰＮトラ
ンジスタアクシ冒ンは発生せず、ラッチアップ現象が防
止できる。As described above, by locating the P-type high concentration region 23 on the P-channel transistor side, the resistance R1 is reduced.
Furthermore, by locating the N-type high concentration region 24 on the N-channel transistor side, the resistance R2 is reduced. NPN transistor activation does not occur, and latch-up phenomenon can be prevented.
第１図は、従来のＭＩＳ電界電界製実装置造工程を示す
図、第２図は、本発明の実施例として相補型ＭＩＳ電界
電界製実装置造工程を示す図である。
図において、１１は基板、■４は酸化膜、２１．２６は
ドレイン領域、２２．２５はソース領域、２８，２李は
某板電極取出領域、１９．２０は配線層、１５．１６は
ゲート絶縁膜、１７．１８はゲート電極をそれぞれ示す
。
茶 １ 目
第 ２１２
′／′FIG. 1 is a diagram showing a conventional MIS electric field manufacturing device manufacturing process, and FIG. 2 is a diagram showing a complementary MIS electric field manufacturing device manufacturing process as an embodiment of the present invention. In the figure, 11 is a substrate, 4 is an oxide film, 21.26 is a drain region, 22.25 is a source region, 28, 2 is a certain plate electrode extraction region, 19.20 is a wiring layer, 15.16 is a gate 17 and 18 indicate an insulating film and a gate electrode, respectively. Brown 1st 212′/′
Claims (2)
れたこれと逆導電型の領域と、該領域に設けられた一方
のＭＩＳトランジスタを形成するソース領域、ドレイン
領域及び接触領域と、前記半導体基板に設けられた他方
の ＭＩＳトランジスタを形成するソース領域、ドレイン領
域及び接触領域とを備え、前記 ＭＩＳトランジスタのうち少なくとも、一方のＭＩＳト
ランジスタに於いて、前記接触領域が前記ソース領域及
びドレイン領域よりも他方のＭＩＳトランジスタ側に位
置するように設けたことを特徴とする相補型電界効果半
導体装置。(1) a semiconductor substrate of one conductivity type, a region of the opposite conductivity type provided on the semiconductor substrate, a source region, a drain region, and a contact region forming one MIS transistor provided in the region; The semiconductor substrate includes a source region, a drain region, and a contact region forming the other MIS transistor, and in at least one of the MIS transistors, the contact region is connected to the source region and the drain region. A complementary field effect semiconductor device, characterized in that the device is located closer to the other MIS transistor than the other MIS transistor.
ソース領域もしくはドレイン領域と接触領域とを少なく
とも一部分重ねて設けたことを特徴とする特許請求の範
囲第（１）項記載の相補型電界効果半導体装置。(2) A complementary field effect semiconductor device according to claim (1), characterized in that a source region or a drain region of at least one of the MIS transistors and a contact region overlap at least partially.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60263374A JPS61190974A (en) | 1985-11-22 | 1985-11-22 | Complementary type mis field-effect semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60263374A JPS61190974A (en) | 1985-11-22 | 1985-11-22 | Complementary type mis field-effect semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP49142202A Division JPS6011471B2 (en) | 1974-12-10 | 1974-12-10 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61190974A true JPS61190974A (en) | 1986-08-25 |
Family
ID=17388600
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60263374A Pending JPS61190974A (en) | 1985-11-22 | 1985-11-22 | Complementary type mis field-effect semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61190974A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4914220A (en) * | 1972-03-20 | 1974-02-07 | ||
| JPS4917688A (en) * | 1972-06-05 | 1974-02-16 | ||
| JPS4984587A (en) * | 1972-12-19 | 1974-08-14 | ||
| JPS5168186A (en) * | 1974-12-10 | 1976-06-12 | Nippon Electric Co | Handotaisochino seizohoho |
-
1985
- 1985-11-22 JP JP60263374A patent/JPS61190974A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4914220A (en) * | 1972-03-20 | 1974-02-07 | ||
| JPS4917688A (en) * | 1972-06-05 | 1974-02-16 | ||
| JPS4984587A (en) * | 1972-12-19 | 1974-08-14 | ||
| JPS5168186A (en) * | 1974-12-10 | 1976-06-12 | Nippon Electric Co | Handotaisochino seizohoho |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4965220A (en) | Method of manufacturing a semiconductor integrated circuit device comprising an MOS transistor and a bipolar transistor | |
| US4769337A (en) | Method of forming selective polysilicon wiring layer to source, drain and emitter regions by implantation through polysilicon layer | |
| JPS63239856A (en) | Semiconductor integrated circuit device and manufacture thereof | |
| US5319234A (en) | C-BiCMOS semiconductor device | |
| US5045493A (en) | Semiconductor device and method of manufacturing the same | |
| JP2953425B2 (en) | Method for manufacturing semiconductor device | |
| JPH02101747A (en) | Semiconductor integrated circuit and manufacture thereof | |
| JPS61190974A (en) | Complementary type mis field-effect semiconductor device | |
| JP2002016158A (en) | Manufacturing method of semiconductor device | |
| JP2633559B2 (en) | Method for manufacturing bipolar CMOS semiconductor device | |
| JPH0878685A (en) | Soi-mosfet and its manufacture | |
| JP3351193B2 (en) | Method for manufacturing semiconductor device | |
| US6808999B2 (en) | Method of making a bipolar transistor having a reduced base transit time | |
| JP2722415B2 (en) | Method for manufacturing semiconductor device | |
| JPH1098111A (en) | Mos semiconductor device and manufacture thereof | |
| JP2697631B2 (en) | Method for manufacturing semiconductor device | |
| JPH11307544A (en) | Bipolar transistor and semiconductor integrated circuit device | |
| JP2573303B2 (en) | Method for manufacturing semiconductor device | |
| JPH06120431A (en) | Bipolar transistor and method of manufacturing semiconductor device | |
| JPS5856450A (en) | Complementary mos semiconductor device | |
| JPS6011471B2 (en) | semiconductor equipment | |
| JP2988067B2 (en) | Manufacturing method of insulated field effect transistor | |
| JPH0350422B2 (en) | ||
| JPS63211748A (en) | Manufacture of semiconductor device | |
| JPS632365A (en) | Manufacture of semiconductor integrated circuit |