JPS61190959A - Forming method for multilayer interconnection - Google Patents

Forming method for multilayer interconnection

Info

Publication number
JPS61190959A
JPS61190959A JP3039985A JP3039985A JPS61190959A JP S61190959 A JPS61190959 A JP S61190959A JP 3039985 A JP3039985 A JP 3039985A JP 3039985 A JP3039985 A JP 3039985A JP S61190959 A JPS61190959 A JP S61190959A
Authority
JP
Japan
Prior art keywords
hole
layer
wiring
film
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3039985A
Other languages
Japanese (ja)
Inventor
Hiroshi Ikeda
洋 池田
Mitsuhiro Yamada
山田 光弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP3039985A priority Critical patent/JPS61190959A/en
Publication of JPS61190959A publication Critical patent/JPS61190959A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To reduce contact resistance between a first layer wiring and a second layer wiring in a fined through-hole section, and to improve the degree of integration of multilayer interconnection structure by boring a through-hole to an inter-layer insulating film and forming the second layer wiring under the state in which the inner side surface of the through-hole is coated with an inorganic insulating film. CONSTITUTION:A through-hole 6 is bored to one part of a polyimide film to expose one part of a first layer Al wiring 3. The diameter of the through-hole 6 is brought to size such as 2mum at that time. A plasma CVD oxide film 7 is formed onto the whole surface containing the through-hole in thin size (approximately 0.4mum). The surface of the polyimide film and the plasma CVD oxide film on the base of the through-hole are dry-etched through RIE. Only a CVD oxide film 7a in the inner surface section of the through-hole is left at that time. Al is evaporated, and patterned, thus shaping a second layer Al wiring 5 connected to the first layer Al wiring 3 through the through-hole onto the polyimide film, then completing double layer interconnection structure.

Description

【発明の詳細な説明】 し技術分野〕 本発明は多層配線の微細化技術に関し、主として半導体
装置における多層配線形成方法に関する〇〔背景技術〕 ICやLSI等の半導体装置において、1チツプあたり
の素子数が増大するに伴い、素子の電極間を接続するア
ルミニウム等の配線は1層構造では無理であり、2層以
上の多層配線構造が採用されている。この2層以上の配
線間には層間絶縁層として、従来は、シリコン酸化物や
リン酸化物をふくむシリコン酸化物糸ガラス等の無機絶
縁膜が使われていたが、これで厚膜を形成した場合に、
熱処理の際の歪によってクラック等が生じやすく、又、
材質の異なるどうしの絶縁膜を多層に重ねると表面の段
差が甚疋しくなり、その上に形成される配線に断線不良
を生じるなどの問題があった。
[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology for miniaturizing multilayer wiring, and mainly relates to a method for forming multilayer wiring in semiconductor devices. [Background Art] In semiconductor devices such as ICs and LSIs, elements per chip are As the number of devices increases, it is no longer possible to use a single layer structure for interconnects made of aluminum or the like to connect between electrodes of elements, and a multilayer interconnect structure of two or more layers is being adopted. Conventionally, an inorganic insulating film such as silicon oxide thread glass containing silicon oxide or phosphorous oxide has been used as an interlayer insulating layer between two or more layers of wiring, but it is possible to form a thick film with this. In case,
Cracks are likely to occur due to distortion during heat treatment, and
When insulating films made of different materials are stacked in multiple layers, the level difference on the surface becomes severe, causing problems such as disconnections in the wiring formed thereon.

このような無機の絶縁膜に代って、比較的低温処理が可
能で、しかも表面平坦性を確保できる1機絶縁膜が使わ
れるようになった。特に本発明者によって開発された高
耐熱性のポリイミド系高分子樹脂を層間絶縁属に用いた
配線構造が採用されている(特公昭57−36759公
報参照)。
Instead of such inorganic insulating films, single-organic insulating films, which can be processed at relatively low temperatures and can ensure surface flatness, have come to be used. In particular, a wiring structure in which a highly heat-resistant polyimide polymer resin developed by the present inventor is used as an interlayer insulator has been adopted (see Japanese Patent Publication No. 57-36759).

このポリイミド系樹脂、たとえば、芳香族ジアミンと、
芳香族テトラカルボン酸二無水物とを反応して得られる
重合物からなるポリイミド系樹脂を、基板上に層間絶l
ik膜として形成する場合、ポリイミド系樹脂のプレポ
リマー溶液!液を配線の形成された基板表面にスピンナ
塗布した後、溶媒成分を蒸発させ、200〜300℃熱
処理して重合硬化させて被a’v形成する。
This polyimide resin, for example, aromatic diamine,
A polyimide resin made of a polymer obtained by reacting with an aromatic tetracarboxylic dianhydride is interlayered on a substrate.
When forming an ik film, a prepolymer solution of polyimide resin! After applying the solution to the surface of the substrate on which wiring is formed using a spinner, the solvent component is evaporated, and heat treatment is performed at 200 to 300° C. to polymerize and harden, thereby forming an a'v layer.

第7図はポリイミド系樹脂を層間絶#111g1!に使
用した2層アルミニウム配線構造の一例を示す断面図で
ある。
Figure 7 shows interlayer polyimide resin #111g1! FIG. 2 is a cross-sectional view showing an example of a two-layer aluminum wiring structure used in FIG.

1はシリコン結晶基板、2は表面酸化膜(SiQ。1 is a silicon crystal substrate, 2 is a surface oxide film (SiQ).

III)であ、る。3は第1層AJ(アルミニウム)配
線で厚さd1=1〜1.75μm程度である。4はポリ
イミド系樹脂からなる層間絶縁膜で厚さd2=2.2μ
m程度である。5は第2層1配線で層間絶縁膜4の上に
形成され、その一部に開けられたスルーホール(透孔)
6を通じて第1層Al配線3に接続する。
III). 3 is a first layer AJ (aluminum) wiring having a thickness d1 of about 1 to 1.75 μm. 4 is an interlayer insulating film made of polyimide resin, thickness d2 = 2.2μ
It is about m. 5 is a second layer 1 wiring formed on the interlayer insulating film 4, and a through hole formed in a part thereof.
6 to the first layer Al wiring 3.

このような2層配線構造において、1間絶縁膜4のスル
ーホールが微細化し、その口径りが3μm以下になると
、孔開は後にスパッタクリーニング処理を行っても、第
2層配縁5と第2層配縁5との間のコンタクト抵抗が急
増することがわかってきた。
In such a two-layer wiring structure, as the through-holes in the first-layer insulating film 4 become finer and their diameter becomes 3 μm or less, the opening of the holes becomes difficult even if sputter cleaning is performed later. It has been found that the contact resistance with the two-layer interconnect 5 increases rapidly.

し発明の目的] 本発明は上述した問題を克服するためになされたもので
ある。
OBJECT OF THE INVENTION] The present invention has been made to overcome the above-mentioned problems.

したがって本発明の一つの目的は、多層配線構造におい
て、ポリイミド系樹脂を用いた層間絶縁膜のスルーホー
ルでの上下のアルミニウム配線間の接触抵抗を減少させ
ることにある。
Therefore, one object of the present invention is to reduce the contact resistance between upper and lower aluminum wires in a through hole of an interlayer insulating film using polyimide resin in a multilayer wiring structure.

本発明の他の目的はポリイミド系樹脂を層間絶縁膜に用
いた多層配線構造をもつ半導体装置のさらに高集積化を
実現することにある。
Another object of the present invention is to realize higher integration of a semiconductor device having a multilayer wiring structure using polyimide resin as an interlayer insulating film.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。
A brief overview of typical inventions disclosed in this application is as follows.

すなわち、基板上に第2層1配線と第2層1配線とをポ
リイミド系樹脂からなる層間絶縁膜にあけたスルーホー
ル(透孔)を通して接続するにあたって、上記層間絶縁
膜にスルーホールをあげた後、少なくとも上記スルーホ
ールの内側面を無機性の絶縁膜で覆った状態で第2層配
線を形成することにより、微細化されたスルーホール部
における第1層配線と第2層配線との接触抵抗を減少さ
せ、多層配線構造の高集積化が実現できる。
That is, in order to connect the second layer 1 wiring and the second layer 1 wiring on the substrate through through holes made in the interlayer insulating film made of polyimide resin, the through holes were formed in the interlayer insulating film. After that, by forming a second layer wiring with at least the inner surface of the through hole covered with an inorganic insulating film, contact between the first layer wiring and the second layer wiring in the miniaturized through hole portion is established. It is possible to reduce resistance and achieve high integration of multilayer wiring structures.

〔実施例〕〔Example〕

第1図乃至第7図は、本発明の一実施例を示すものであ
って、半導体基板上に2層Al配線を形成するプロセス
の工程断面図である。以下、各工程に従って詳しく述べ
ろ。
FIGS. 1 to 7 show an embodiment of the present invention, and are cross-sectional views of a process for forming two-layer Al wiring on a semiconductor substrate. Please explain each step in detail below.

(1)第1図に示すように、Si(シリコン)I晶基体
(ウェハ)IY用意し、この基体の一生面に図示されな
い半導体素子を形成し、その際に生成された表面酸化膜
2の上に、AI<アルミニウム)を蒸着(又はスパッタ
)し、厚さ1.75μmの第17@Alj配線3ft形
成させる。
(1) As shown in FIG. 1, a Si (silicon) I crystal substrate (wafer) IY is prepared, a semiconductor element (not shown) is formed on the whole surface of this substrate, and the surface oxide film 2 generated at that time is On top of this, evaporation (or sputtering) is performed to form a 17th @Alj wiring having a thickness of 1.75 μm (3 feet) (AI<aluminum).

(2)この上にポリイミド系樹脂を塗布し、第2図に示
すよ5KJIkさ1,75〜2.0μm程度の層間絶縁
膜4を上記第1層AI配@3を覆うように形成する。こ
の被1g!4は、ポリイミド系樹脂のプレポリマー溶液
、又は半型合物溶液(たとえばN−メチル−2−ピロリ
ドンもしくはN−N−ジメチル−アセトアミドなどを溶
液とする)を基体表面にスピンナー塗布したのち、溶媒
成分を蒸発させ、さらに200〜300℃で熱処理して
硬化させることより形成する。
(2) A polyimide resin is applied thereon, and an interlayer insulating film 4 having a thickness of 5KJIk and about 1.75 to 2.0 μm is formed to cover the first layer AI layer 3 as shown in FIG. This cover is 1g! In step 4, a prepolymer solution of a polyimide resin or a half-form compound solution (for example, a solution of N-methyl-2-pyrrolidone or N-N-dimethyl-acetamide) is applied to the surface of the substrate using a spinner, and then a solvent is applied. It is formed by evaporating the components and further heat-treating at 200 to 300°C to harden it.

(3)次いでホトレジストマスクを通し、ヒドラジン−
ヒトラード・エチレンアミンを用いてエッチし、第3図
に示すようにポリイミド被膜の一部にスルーホール(透
孔)6をあけ、第1層1配線3の一部を露出する。この
ときスルーホール6の径はたとえば2μmとする。
(3) Next, pass through a photoresist mask to remove hydrazine.
Etching is performed using Hitlered ethylene amine to make a through hole 6 in a part of the polyimide film to expose a part of the first layer 1 wiring 3, as shown in FIG. At this time, the diameter of the through hole 6 is, for example, 2 μm.

(4)  このあとプラズマ放電装置を用い、気相中で
化学生成したSiQ、すなわちプラズマCVDW化膜7
を、第4図に示すように上記スルーホールを含む全面に
薄<(0,4μm程度)形成する。
(4) After this, using a plasma discharge device, SiQ is chemically generated in the gas phase, that is, the plasma CVDW film 7
As shown in FIG. 4, is formed to a thickness of about 0.4 μm over the entire surface including the through hole.

(5)  基体に対し電界をかけた状態で垂直方向のみ
にエッチを行う、いわゆるR I E (IJアクティ
ブ・イオンエッチ)を行なって、ポリイミド被膜表面及
びスルーホール底面のプラズマCVD#R化膜をドライ
エッチする。
(5) Perform so-called RIE (IJ active ion etching), which performs etching only in the vertical direction while applying an electric field to the substrate, to remove the plasma CVD#R film on the surface of the polyimide film and the bottom of the through hole. Have dry sex.

このとき、イオン投射方向に沿ったスルーホール内側面
部分のCVD酸化膜7aのみが、第5図に示すようにエ
ッチされないで残存する。
At this time, only the CVD oxide film 7a on the inner surface of the through hole along the ion projection direction remains without being etched, as shown in FIG.

(61Al(アルミニウム)を蒸着し、バターニングす
ることにより、第6図に示すように第」層Al配線3に
スルーホールを通して接続する第2層Al配線5をポリ
イミド被膜上に形成し、かくして2層配線構造が完成す
る。
(By vapor-depositing 61Al (aluminum) and buttering, a second layer Al wiring 5 is formed on the polyimide film to be connected to the second layer Al wiring 3 through a through hole as shown in FIG. The layer wiring structure is completed.

〔効果〕〔effect〕

以上実施例で説明した本発明によれば、下記のように効
果が得られる。
According to the present invention explained in the embodiments above, the following effects can be obtained.

ポリイミド系樹脂エリなる層間絶縁膜のスルーホールが
微細化された場合に第1層Al配線と第21iIAl配
線との間の接触抵抗が増大する理由としては、第2層配
線形成の際のA!蒸着時にスルーホール内でポリイミド
樹脂表面からの脱ガスにより、スルーホール底面のAJ
面が変質し、A!酸化物を含んだ高比抵抗のhlKi膜
が生成されることと考えられる。
The reason why the contact resistance between the first layer Al wiring and the 21st IAl wiring increases when the through holes in the interlayer insulating film made of polyimide resin are miniaturized is due to A! when forming the second layer wiring. During vapor deposition, degassing from the surface of the polyimide resin inside the through-hole causes AJ on the bottom of the through-hole.
The surface changes in quality and A! It is thought that a high resistivity hlKi film containing oxides is generated.

しかし、スルーホールの内側面を、無機物質であるプラ
ズマCVD5iO,膜で覆うことにより、ポリイミド系
樹脂からの脱WガスによるAI衣表面変質が大幅に防止
され、この状態で第1層Al配線が形成されることにエ
リ、第1層Al配線と第2層Al配線との接触抵抗が減
少する。
However, by covering the inner surface of the through hole with an inorganic plasma CVD 5iO film, the surface deterioration of the AI coating due to the detung gas from the polyimide resin is significantly prevented, and in this state, the first layer Al wiring is Due to this formation, the contact resistance between the first layer Al wiring and the second layer Al wiring is reduced.

しかし、スルーホールの内側面を無機質のプラズマCV
 D S iOt @で覆うことくより、ポリイミド樹
脂からの脱ガスによるA1表面の変質が大幅に阻止され
、このような状態で第2層Al配線が形成されることに
より、第1層Al配線と第2層Al配線との接触抵抗が
減少できる。
However, the inner surface of the through hole was coated with inorganic plasma CV.
By covering with DSiOt@, the deterioration of the A1 surface due to degassing from the polyimide resin is significantly prevented, and by forming the second layer Al wiring in this state, it is able to match the first layer Al wiring. Contact resistance with the second layer Al wiring can be reduced.

第8図は層間絶縁膜の状態によって異なるスルーホール
部の上下AI配線の抵抗とスルーホール底面(D)との
関係を曲線図により示すものである。
FIG. 8 is a curve diagram showing the relationship between the resistance of the upper and lower AI wirings in the through-hole portion and the bottom surface (D) of the through-hole, which varies depending on the state of the interlayer insulating film.

同図において、人は層間絶縁膜にS t 02や5iN
(ナイトライド)の如き無機物の膜を使用した場合、B
はポリイミド系樹脂の如き有機物の膜を使用した場合で
あり、Cはポリイミド系樹脂を使用するとともにスルー
ホール内側面を5iQ1膜で覆った場合の例を示す@ 同図において示すように、使用し得るスルーホール抵抗
Rにおいては、ポリイミド系樹脂では、スルーホールロ
径りが4μm程度が限界であるが、スルーホール内側面
をSiQ、膜等で覆うことにより、2μm程度に微細化
することも可能である。
In the same figure, a person uses S t 02 or 5iN in the interlayer insulating film.
When using an inorganic film such as (nitride), B
C shows an example where an organic film such as polyimide resin is used, and C shows an example where a polyimide resin is used and the inside surface of the through hole is covered with a 5iQ1 film. With polyimide resin, the through-hole resistance R obtained is limited to about 4 μm, but it is possible to make it as fine as about 2 μm by covering the inside surface of the through-hole with SiQ, a film, etc. It is.

このように1本発明によれば、スルーホールの微細化限
界が増すことで、ポリイミド系樹脂多層配線の高集積化
が実現できることになった。
As described above, according to the present invention, by increasing the limit of miniaturization of through-holes, it is possible to realize highly integrated polyimide-based resin multilayer wiring.

以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもなX、1゜ 例えばスルーホール内側面を覆う無機膜としてプラズマ
Si3N、を使用する場合にも同様の効果が得られる。
Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, a similar effect can be obtained when plasma Si3N is used as the inorganic film covering the inner surface of the through hole.

〔利用分野〕[Application field]

本発明は2層配線あるいは3層以上の配線′?:有し1
1層間絶lik膜にポリイミド系樹脂の如き有機膜を使
用した多層配線構造の半導体装置に全て適用できる。
Is the present invention applicable to two-layer wiring or three or more layer wiring'? :Has 1
The present invention can be applied to any semiconductor device having a multilayer wiring structure in which an organic film such as a polyimide resin is used as a single-layer insulation film.

本発明は特にリニアICなどの半導体集積回路装置Ki
用して最も有効である。
The present invention particularly applies to semiconductor integrated circuit devices such as linear ICs.
It is most effective to use

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第6図は本発明の一実施例を示す2層配線プ
ロセスの工程断面図である。 第7図は従来の2層配線構造の一例を示す断面図である
。 第8図はスルーホール抵抗とスルーホールロ径の関係曲
線図である。 1・・・Si基板、2・・・SiQ、膜、3・・・第1
層Al配線、4・・・ポリイミド層間寝、5・・・第2
k1層配線、6・・・スルーホール、7・・・無機物被
膜。 第  1  図 ♀ 第  2  図 第  3  図 第  4  図 第  5  図 第  6  図
FIGS. 1 to 6 are process cross-sectional views of a two-layer wiring process showing an embodiment of the present invention. FIG. 7 is a sectional view showing an example of a conventional two-layer wiring structure. FIG. 8 is a relationship curve diagram between through-hole resistance and through-hole diameter. 1...Si substrate, 2...SiQ, film, 3...first
Layer Al wiring, 4... Polyimide interlayer, 5... Second
k1 layer wiring, 6... through hole, 7... inorganic coating. Figure 1 ♀ Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

【特許請求の範囲】 1、基板上に形成された第1層配線と第2層配線とを層
間の有機性絶縁膜にあけた透孔を通して接続するにあた
って、上記層間の有機性絶縁膜に透孔をあげた後、少な
くとも上記透孔の内側面を無機性の絶縁膜で覆った状態
で第2層配線を形成することを特徴とする多層配線の形
成方法。 2、上記有機性の絶縁膜として、ポリイミド系樹脂を使
用する特許請求の範囲第1項記載の多層配線の形成方法
。 3、上記有機性の絶縁膜にポリイミド系樹脂を使用する
とともに、上記無機性の絶縁膜にシリコン酸化物糸ガラ
スを使用する特許請求の範囲第1項記載の多層配線の形
成方法。
[Claims] 1. When connecting the first layer wiring and the second layer wiring formed on the substrate through the through hole formed in the organic insulating film between the layers, the organic insulating film between the layers is connected. A method for forming a multilayer wiring, which comprises forming a second layer wiring with at least the inner surface of the through hole covered with an inorganic insulating film after forming the hole. 2. The method for forming a multilayer wiring according to claim 1, wherein a polyimide resin is used as the organic insulating film. 3. The method of forming a multilayer wiring according to claim 1, wherein a polyimide resin is used for the organic insulating film, and silicon oxide thread glass is used for the inorganic insulating film.
JP3039985A 1985-02-20 1985-02-20 Forming method for multilayer interconnection Pending JPS61190959A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3039985A JPS61190959A (en) 1985-02-20 1985-02-20 Forming method for multilayer interconnection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3039985A JPS61190959A (en) 1985-02-20 1985-02-20 Forming method for multilayer interconnection

Publications (1)

Publication Number Publication Date
JPS61190959A true JPS61190959A (en) 1986-08-25

Family

ID=12302853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3039985A Pending JPS61190959A (en) 1985-02-20 1985-02-20 Forming method for multilayer interconnection

Country Status (1)

Country Link
JP (1) JPS61190959A (en)

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