JPS6298659A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPS6298659A
JPS6298659A JP23736485A JP23736485A JPS6298659A JP S6298659 A JPS6298659 A JP S6298659A JP 23736485 A JP23736485 A JP 23736485A JP 23736485 A JP23736485 A JP 23736485A JP S6298659 A JPS6298659 A JP S6298659A
Authority
JP
Japan
Prior art keywords
film
layer
onto
wirings
shaped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23736485A
Other languages
Japanese (ja)
Inventor
Toru Inaba
稲葉 透
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP23736485A priority Critical patent/JPS6298659A/en
Publication of JPS6298659A publication Critical patent/JPS6298659A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce an area occupied by a capacitance on a chip by forming an Al film onto a soft polyimide resin film as a foundation. CONSTITUTION:In a semiconductor base body 1, an active element 8, a passive element, etc. such as a transistor are formed to the surface, and the surface has oxide film SiO2 9, and has an Al electrode, first layer Al wirings 10, etc. connected in low resistance to diffusion layers for the elements. An organic insulating film 2 is shaped on the first layer Al wirings as an interlayer film, and consists of a high heat-resistant polyimide group high molecular resin-for example, a prepolymer liquid composed of a polyimide group resin acquired by reacting aromatic diamine and an aromatic tetracarboxylic acid anhydride is spinner-coated onto the surface of a substrate to which wirings are shaped, solvent components are evaporated,and the prepolymer liquid is polymerized and cured through heat treatment at 200-300 deg.C. An Al film 3 is formed onto the organic insulating film as the interlayer film at the same time as a second layer Al wiring. A thin dielectric film 4 is shaped onto the surface of the Al film 3.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置、特に多層配線を有する半導体装置
における容量形成技術に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a capacitor formation technique in a semiconductor device, particularly a semiconductor device having multilayer wiring.

〔背景技術〕[Background technology]

IC,LSI等の半導体集積回路装置に内蔵する容量素
子は大別して(1)半導体基体内に不純物拡散されたp
n接合を利用する仄合容倣、(2)半導体基体の表面に
シリコン酸化膜(Sing)を介してアルミニウム等の
金属膜を重ねるMO3容量がある。MO8容量の変形と
してたとえば日経マグロウヒル社発行の[日経エレクト
ロニクスJ 11982年10月25日号によれば、酸
化膜の代りにシリコン窒化膜(5isN+ )を用いた
容量が紹介されている。
Capacitive elements built into semiconductor integrated circuit devices such as ICs and LSIs are broadly classified into (1) p
(2) MO3 capacity in which a metal film such as aluminum is layered on the surface of a semiconductor substrate via a silicon oxide film (Sing). As a modification of the MO8 capacitor, for example, according to the October 25, 11982 issue of Nikkei Electronics J published by Nikkei McGraw-Hill, a capacitor using a silicon nitride film (5isN+) instead of an oxide film is introduced.

この場合、St、N、は高い誘電率を有することにより
、かなり高効率の容量が得られるが、第1層配線に使用
されるAl膜と拡散層との間で容量を形成するため、(
1)チップ面積が太き(なる、(2)拡散層と基体との
間に寄生の接合容量が発生する、(3)片方の電極とな
る拡散層の横方向のシリーズ抵抗が大きくなる等の問題
があることが本願発明者によりあきらかとされた。
In this case, St, N, have a high dielectric constant, so a fairly highly efficient capacitance can be obtained, but since a capacitance is formed between the Al film used for the first layer wiring and the diffusion layer, (
1) The chip area becomes large, (2) parasitic junction capacitance occurs between the diffusion layer and the substrate, and (3) the lateral series resistance of the diffusion layer that becomes one of the electrodes becomes large. It has been found by the inventor of this application that there is a problem.

この他に多層配線における第1層配線のA2膜の上に薄
い誘電体膜を介して第2層配線のAA膜を重ねるMIM
(金属・絶縁物・金属)型容量が本願発明者等によって
提案されている。しかし、この場合、第1層のAA膜は
硬い下地基板ないし下地のS iO,膜の上に形成され
ているが、 AJIlt膜面にヒルロノクスと称する0
、5〜1.5μmの突起物が発生しやすい。このため第
1層A召膜上に形成される誘電体膜が薄い場合にこのヒ
ルロノクスが誘電体膜を突きぬけで上下の電接が短絡す
るということがわかった。
In addition, there is MIM in which the AA film of the second layer wiring is overlaid on the A2 film of the first layer wiring in a multilayer wiring via a thin dielectric film.
A (metal/insulator/metal) type capacitor has been proposed by the inventors of the present application. However, in this case, the first layer of AA film is formed on a hard base substrate or underlying SiO film, but there is a layer of 0 called Hiruronox on the AJIlt film surface.
, protrusions of 5 to 1.5 μm are likely to occur. For this reason, it has been found that when the dielectric film formed on the first layer A layer is thin, this hiruronox penetrates the dielectric film and short-circuits the upper and lower electrical connections.

〔発明の目的〕[Purpose of the invention]

本発明は上記した問題を克服するためになされたもので
ある。
The present invention has been made to overcome the above-mentioned problems.

本発明の一つの目的は下地構造とは無関係でチップ上に
占有面積な犬ぎくとらないMIM容量を提供することに
ある。
One object of the present invention is to provide an MIM capacitor that is independent of the underlying structure and does not take up too much space on a chip.

本発明の他の一つの目的はヒルロックの影響のtxいM
IM容量を提供することにある。
Another object of the present invention is to reduce the influence of hillock
The objective is to provide IM capacity.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本発明の記述および添付図面からあきらかになろう。
The above and other objects and novel features of the present invention include:
It will become clear from the description of the invention and the accompanying drawings.

〔発明の概要〕 本願において開示されろ発明のうち代表的なものの概要
を簡単に説明すれば下記のとおりである。
[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

すなわち、半導体基体上に配線下地膜又は配線層間膜と
してポリイミド系樹脂などの有機被膜が形成されたもの
においてこの有機被膜の上に形成した第1電極となる第
1のA2膜と、第1のA!II!膜上に形成した薄い誘
電体膜と、この誘電体膜上に形成した第2電榛となる第
2のA2膜とによって容量を形成したものであって、下
地となる軟いポリイミド樹脂膜上にA2膜を形成するこ
とで薄い誘電体膜を形成した場合でもヒルロックの発生
が防止され、層間膜上のA2膜を利用することによって
、チップ上の容量の占める面積な犬ぎくとらないですみ
、前記発明の目的を達成できる。
That is, in a device in which an organic film such as a polyimide resin is formed as a wiring base film or a wiring interlayer film on a semiconductor substrate, a first A2 film forming a first electrode formed on this organic film, and a first A2 film formed on the organic film as a first electrode. A! II! A capacitor is formed by a thin dielectric film formed on the film and a second A2 film formed on the dielectric film, which becomes a second electric field, and is formed on a soft polyimide resin film as the base. By forming the A2 film on the interlayer film, hillocks can be prevented even when a thin dielectric film is formed, and by using the A2 film on the interlayer film, the area occupied by the capacitance on the chip can be avoided. , the object of the invention can be achieved.

〔実施例1〕 第1図乃至第4図は本発明の一実施例を示すものであっ
て、半導体基体上にMIM容量を形成すルプロセスの工
程断面図である。
[Embodiment 1] FIGS. 1 to 4 show an embodiment of the present invention, and are cross-sectional views of a process for forming an MIM capacitor on a semiconductor substrate.

(1)  シリコン半導体基体の上に有機絶縁被膜を形
成し、この上に容量の一方の電極であるAノ膜3を形成
する。(第1図) 上記半導体基体1はその表面には第5因を参照し、トラ
ンジスタ等の能動素子(8)、受動素子等が形成された
ものであって1表面に酸化膜(Sin、)(9)を有し
、上記素子の拡散層に低抵抗接続するA1電極、第1層
A石配線00)等を有するものである。
(1) An organic insulating film is formed on a silicon semiconductor substrate, and the A film 3, which is one electrode of the capacitor, is formed on this film. (Fig. 1) Referring to the fifth factor, the semiconductor substrate 1 has active elements (8) such as transistors, passive elements, etc. formed on its surface, and has an oxide film (Sin, etc.) formed on its surface. (9), and includes an A1 electrode connected with low resistance to the diffusion layer of the above element, a first layer A stone wiring 00), and the like.

上記有機絶縁膜2は上記第2層A2配線の上に層間膜と
して形成されたもので、昼耐熱性のポリイミド系高分子
樹脂であって、たとえば芳香族ジアミンと芳香族テトラ
カルボン酸二無水物とを反応して得られるポリイミド系
樹脂のプレポリマー漱を配線の形成された基板表面にス
ピンナ塗布した後、溶媒成分を蒸発させ、200〜30
o℃で熱処理して重合硬化させるものである。
The organic insulating film 2 is formed as an interlayer film on the second layer A2 wiring, and is made of day heat-resistant polyimide polymer resin, for example, aromatic diamine and aromatic tetracarboxylic dianhydride. After applying a prepolymer residue of polyimide resin obtained by reacting with
It is polymerized and hardened by heat treatment at 0°C.

An膜3は層間膜である有機絶縁膜の上に第2/u A
 、6配勝と同時に形成されるものでA−e蒸着(スパ
ッタ)後にホトレジストマスクを用いて所要とする容量
の形状寸法にパターニングされる。
An An film 3 is a second /u A film on an organic insulating film which is an interlayer film.
, 6 are formed at the same time, and after A-e vapor deposition (sputtering), patterning is performed using a photoresist mask into the shape and size of the required capacitance.

(21A−g膜3の表面に薄い誘電体膜4を形成する。(A thin dielectric film 4 is formed on the surface of the 21A-g film 3.

この誘電体は、たとえばプラズマナイトライドP−3i
N (誘電率!=6.7)、ナイトライドSi、N。
This dielectric material is, for example, plasma nitride P-3i
N (permittivity!=6.7), Si nitride, N.

(誘電率と=7.0)、あるいはプラズマシリコン1l
ff化膜P−8iO,(誘電率4、O−4,3)’Y使
用シソの厚さは100〜1oooiとする。(第2図)
(3)全面にポリイミド樹脂などの第2層目の有機被膜
5を生成し、ホトエツチングによって必要とする容量の
面積形状のスルーホール6をあける。
(permittivity = 7.0) or 1 liter of plasma silicon
The thickness of the ff film P-8iO, (permittivity 4, O-4, 3)'Y used is 100 to 1 oooi. (Figure 2)
(3) A second layer organic film 5 of polyimide resin or the like is formed on the entire surface, and a through hole 6 having the area shape of the required capacity is formed by photoetching.

このスルーホールエッチにはヒドラジンの40〜80%
水溶液等を使用する。(第3図)(4)容量の他方の電
極であるA2膜7を形成する。
For this through-hole etch, 40 to 80% of hydrazine is used.
Use an aqueous solution etc. (FIG. 3) (4) Form the A2 film 7 which is the other electrode of the capacitor.

このAAllU7は第2層目の有機被膜5の上に第3層
のA2配mav形成と同時に形成されるものである。
This AAllU7 is formed on the organic film 5 of the second layer at the same time as the formation of the A2 pattern mav of the third layer.

第5図は上記プロセスによって得られた各社を有する半
導体集積回路装置の一例を示す一部断面図である。同図
において、8は能動素子拡散層、9は基板表面Sin、
膜、10+1gl)tjA−g配YJJ、11は第2層
A2配線、12は第38ik13配森である。
FIG. 5 is a partial sectional view showing an example of a semiconductor integrated circuit device obtained by the above process. In the figure, 8 is an active element diffusion layer, 9 is a substrate surface Sin,
11 is the second layer A2 wiring, 12 is the 38th ik13 wiring.

〔発明の効果〕〔Effect of the invention〕

以上実施例で述べた本発明によれば下記のように効果が
得られる。
According to the present invention described in the embodiments above, the following effects can be obtained.

(1)多層配線構造では、通常第1層配線は各素子から
の電極取出しのための配線密度が大ぎくここに容iを入
れる余地は少ない。一方、第2層以上の配線は第1層配
緋に比して配線密度はそれほど犬きくなく、第2層と第
3層で容量をつくる場合。
(1) In a multilayer wiring structure, the first layer wiring usually has a high wiring density for taking out electrodes from each element, so there is little room for adding capacity here. On the other hand, the wiring density in the second and higher layers is not as high as that in the first layer, and the capacitance is created in the second and third layers.

下地の素子構造に影響を与えることが少なく、広い面積
で高容量が得られる。
It has little effect on the underlying element structure, and high capacitance can be obtained over a wide area.

(2)容量の第111極を柔軟な有機絶縁膜の上に設け
たことによってA2を使用した場合でもストレスがかか
らないためにヒルロノクスが発生し難い。
(2) Since the 111th electrode of the capacitor is provided on a flexible organic insulating film, stress is not applied even when A2 is used, so hirronox is less likely to occur.

このためその上に薄い誘電膜を形成することができ、高
容量が可能である。
Therefore, a thin dielectric film can be formed thereon, and a high capacity can be achieved.

(3)上記(1)(2+よりチップ面積を大ぎくするこ
となく高容thtを形成することが可能である。たとえ
ばビデオ帯のフィルタ内蔵が可能となる。
(3) From (1) (2+) above, it is possible to form a high capacity tht without increasing the chip area. For example, it is possible to incorporate a video band filter.

以上本発明によってなされた発明を実施例にもとづき具
体的に説明したが、本発明は上記実施例に限定されるも
のでなく、その要旨を逸脱しない範囲で種々変更が可能
である。
Although the invention made by the present invention has been specifically explained above based on the examples, the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof.

たとえば容量の第1m極に使用するA−gにボロンを混
入させることによってヒルロノクスの発生をさらに少な
(シ、依頼性ある容tを形成することができる。
For example, by mixing boron into A-g used for the first m-electrode of the capacitor, it is possible to form a more reliable capacitor with less generation of hiruronox.

さらにil 、@21!極としてはA2合金、チタンT
i、タンタルTa、タングステンW、ポリシリコンによ
っても形成できることは言うまでもな(So 〔利用分野〕 本発明は有機絶縁膜を使用した多層配線構造を有する半
導体装置の全てに応用可能である。
More il, @21! As the pole, A2 alloy, titanium T
It goes without saying that it can also be formed using i, tantalum Ta, tungsten W, or polysilicon (So [Field of Application] The present invention is applicable to all semiconductor devices having a multilayer wiring structure using an organic insulating film.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第4図は本発明の一実施例を示す容量素子形
成プロセスの工程断面図である。 第5図は本発明の応用例を示す容量素子の内蔵の半導体
集積回路装置の一部断面図である。 ■・・半導体基板、2・・・有機絶縁膜、3・・・第1
のA、8膜(′dL極)、4・・・誘電体膜、5・・・
第2の有機絶縁膜、6・・・スルーホール、7・・・第
2のA影膜(電極)。
1 to 4 are process cross-sectional views of a capacitive element forming process showing one embodiment of the present invention. FIG. 5 is a partial sectional view of a semiconductor integrated circuit device with a built-in capacitive element, showing an application example of the present invention. ■...Semiconductor substrate, 2...Organic insulating film, 3...First
A, 8 films ('dL pole), 4... dielectric film, 5...
second organic insulating film, 6... through hole, 7... second A shadow film (electrode);

Claims (1)

【特許請求の範囲】 1、半導体基体上に配線下地膜又は層間膜を有する半導
体装置において、被膜の上に形成された第1の配線電極
膜と第1の配線電極膜表面に形成された薄い誘電体膜及
びこの誘電体膜上に形成された第2の配線電極膜とで容
量が構成されていることを特徴とする半導体装置。 2、上記下地膜又は層間膜はポリイミド系樹脂からなる
特許請求の範囲第1項に記載の半導体装置。
[Claims] 1. In a semiconductor device having a wiring base film or an interlayer film on a semiconductor substrate, a first wiring electrode film formed on the film and a thin film formed on the surface of the first wiring electrode film A semiconductor device characterized in that a capacitor is formed by a dielectric film and a second wiring electrode film formed on the dielectric film. 2. The semiconductor device according to claim 1, wherein the base film or interlayer film is made of polyimide resin.
JP23736485A 1985-10-25 1985-10-25 Semiconductor device Pending JPS6298659A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23736485A JPS6298659A (en) 1985-10-25 1985-10-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23736485A JPS6298659A (en) 1985-10-25 1985-10-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6298659A true JPS6298659A (en) 1987-05-08

Family

ID=17014292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23736485A Pending JPS6298659A (en) 1985-10-25 1985-10-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6298659A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508881A (en) * 1994-02-01 1996-04-16 Quality Microcircuits Corporation Capacitors and interconnect lines for use with integrated circuits
KR100306111B1 (en) * 1989-03-20 2001-09-24 가나이 쓰도무 Semiconductor integrated circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100306111B1 (en) * 1989-03-20 2001-09-24 가나이 쓰도무 Semiconductor integrated circuit device
US5508881A (en) * 1994-02-01 1996-04-16 Quality Microcircuits Corporation Capacitors and interconnect lines for use with integrated circuits

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