JPS61190637A - Automatic reset device at computer trouble - Google Patents

Abstract

PURPOSE:To secure the reliability of a device and to improve the operating ratio by resetting an interface (I/F) circuit to stop the output to the external if troubles exceeding a prescription are detected in a certain time. CONSTITUTION:When a trouble occurs in a CPU11, a self-diagnostic circuit 21 resets the CPU21, and contents of a counter circuit 22 are increased by +1. Though the CPU11 is reset, the output to an external device 3 is held as it is because an I/F circuit 12 is as it is, and the state of the external device 3 is held. The CPU11 is restarted after reset, the control is continued if any more trouble is not detected. When A-number of seconds elapses after the restart of the CPU11, a timer circuit 23 clears the counter circuit 22; but if a trouble is detected before the elapse of A-number of seconds, contents of the counter circuit 22 are increased by +1. At this time, it is judged that a serious trouble occurs in the CPU, and the output signal to the external is stopped to stop the external device 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an apparatus for automatically resetting a computer in the event of a computer failure.

[Technical Background of the Invention and Problems thereof] The structure and operation of a conventional automatic reset device when a computer fails will be explained with reference to FIGS. 3 and 4.

The computer 1 includes a central processing unit (hereinafter referred to as CPU) 11 and an interface circuit (hereinafter referred to as I/F circuit) 12. The automatic reset device 2 is a self-diagnosis circuit 21
The state of cput is monitored through the signal line L1.

The operation of this device is such that when the self-diagnosis circuit 21 detects a failure in the CPU II, it resets the CPU and the I/F circuit 12, initializes the computer 1, and restarts it.

This operation is shown in the flowchart in Figure 4 for failure detection (1).
00) to 'les. I/F circuit reset (
101), after CPU reset (102). cpu
Reset release (103), I/F circuit reset release (
104) to respond to the flow of returning to normal operation.

In this automatic reset device 2, once a failure is detected, the
Since the /F circuit 12 is reset, the output signal sent to the external device 3 is also initialized, and the external device is stopped. In other words, in the case of this automatic reset device 2, the CPU
II and the self-diagnosis circuit 21 due to a temporary cause such as noise, and a failure is detected.

Since the computer 1 is immediately initialized and the external device 3 is also shut down, although it is possible to improve reliability, it has the drawback of lowering the operating rate.

[Objective of the Invention] The present invention solves the problems of the prior art described above, improves the reliability of the device by the self-diagnosis circuit, avoids interruptions in the operation of external devices due to temporary failures, and improves the operating rate. The purpose of the present invention is to provide an automatic reset device that achieves this.

[Summary of the invention] In order to achieve this object, the present invention provides a timer circuit and a counter circuit in addition to a self-diagnosis circuit, resets only the minimum necessary circuits when a failure is detected, and replaces the I/F circuit with the current one. If no more failures are detected after the reset is released, processing continues as is, and if more failures than specified are detected within a certain period of time, the I/F circuit is reset and output to the outside. By stopping H1
The aim is to ensure 1m reliability and improve operating efficiency.

[Embodiment of the invention'] FIG. 1 shows a circuit diagram of an automatic reset device according to an embodiment of the invention.

A computer 1 composed of a CPU II and an I/F circuit 12 controls external devices 3 such as valves. The automatic reset device 2 includes a self-diagnosis circuit 21, a counter circuit 22, and a timer circuit 23, and a signal line L1
The status of cput is monitored through. CPUII
When a failure such as a clock stop, a parity error, or a watch dog error occurs, the self-diagnosis circuit 21 resets the CPU II once through the signal line L2 and causes it to restart. At the same time, signal line L3. L4 counts the counter circuit 22 once and clears the timer circuit 23. When the timer circuit 23 is not cleared for a certain period of time, the counter circuit is cleared by the signal line L5. The counter circuit 22 is configured to reset the I/F circuit 12 via the signal line L6 when the counter circuit 22 counts a predetermined number of times or more due to the detection of a failure in the CPU II before receiving the clear from the timer circuit 23. ing.

Next, the operation of the present invention will be explained using FIG. 1 and FIG. 2 showing an operation flowchart. To simplify the explanation, it is assumed that the number of times the counter circuit 22 is set is two, and the time that the timer circuit is set is A seconds.

When the CPU 11 is operating normally, the flowchart shown in FIG. 2 branches to NO at failure detection (200), creating a loop.

When a failure occurs in CPU 11, which was operating normally.

The self-diagnostic circuit 21 resets cputt, counts up the counter circuit 22 to 1, and clears the timer circuit 23. cpuli
is reset, but the I/F circuit 12 remains the same, so
The current output to the external device 3 is maintained, and the state of the external device 3 is maintained. After resetting, the CPU 11 restarts, and if no further failure is detected, control continues.

This operation is shown in the flowchart in Figure 2 as failure detection (
200), branch to 'les and do a cpu reset (20
1), and if a failure is detected twice within A seconds (202), the process branches to NO, and after canceling the reset of the CPU (203), the process returns to normal operation. As you can see from this, cputt or self-diagnosis circuit 2
In the event of a failure due to a temporary cause such as noise coming into the device 1, control with a high operating rate can be performed without stopping the external device 3.

Furthermore, when A seconds have passed after the CPU II is reset and restarted, the timer circuit 23 clears the counter circuit 22, but if a failure is detected again before that, the counter circuit 22 counts up further.
The count becomes 2. In this case, it is determined that a serious failure has occurred in the CPU II, and the I/F circuit 12 is reset, the output signal to the outside is stopped, and the external device 3 is stopped.

This operation is shown in the flowchart in Figure 2 as failure detection (
Branch to Yes at 200) and reset the CPU (201
), and the failure is detected twice (202) within A seconds.
This corresponds to the flow of branching to les and resetting the I/F circuit (204). As can be seen from this, the reliability of control by the self-diagnosis function can be improved.

Furthermore, when the I/F circuit 12 is reset and then the CPU II is reset and restarted, the timer circuit 23 is cleared while a failure is detected, so the I/F circuit 12 remains in the reset state. keep it.

This operation is shown in the flowchart of FIG. 2. Within A seconds from the last failure detection after the CPU reset is released (205), the failure is detected again (206) and branches to 'les, and after the CPU is reset (207), CPU reset release (2)
05).

However, after the CPU II failure was no longer detected,
When seconds have elapsed, the timer circuit 23 clears the counter circuit 22, so that the reset state of the I/F circuit 12 is also released and control is performed from the beginning.

This operation is shown in the flowchart in Figure 2. Within A seconds after the last failure is detected, the failure is detected again (206) and the process branches to NO, and after the I/F circuit reset is released (208), the process returns to normal operation. corresponds to

This eliminates the problem of restarting control even though cpu i 1 is out of control and repeatedly starting and stopping the external bag [3], and after confirming that cpult has returned to normal. , it will be possible to restart automatically.

Although the above embodiment shows an example in which the I/F circuit 12 is reset when the CPU II fails, it is also possible to maintain the current status without resetting depending on the settings within the I/F circuit 12. The system configuration can be made as follows.

[Effects of the Invention] As explained above, according to the present invention, the self-diagnosis function in the event of a computer failure is maintained, the external device is not stopped due to a temporary failure, and the device can be operated while maintaining high reliability. This has the effect of improving the operating rate.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of an automatic reset device when a computer malfunctions according to the present invention, FIG. 2 is a flowchart of its operation, and FIG. 3 is a circuit diagram of a conventional automatic reset device when a computer malfunctions. 1st! ± is a flowchart of its operation. 1... Computer, 2... Automatic reset device, 3... External device, 11... CPU, 12...
- I/F circuit, 21... self-diagnosis circuit, 22... counter circuit, 23... timer circuit. (7317) Agent: Patent Attorney Noriyuki Chika (
(and 1 other person) Figure 1, Figure 2, Figure 3]

Claims (1)

[Claims] In a computer having an interface circuit between a central processing unit and an external device, a self-diagnosis circuit detects a failure in the central processing unit, outputs a failure detection signal, and resets the central processing unit; A timer circuit that generates an output when a certain period of time elapses without being cleared, and a timer circuit that is cleared by the output of this timer circuit, but outputs when a specified number of failure detection signals are counted without being cleared. an automatic reset device in the event of a computer failure, characterized in that the device comprises: a counter circuit that generates a counter circuit that resets the interface circuit;