JPS61189745A - Junction box control system - Google Patents

Abstract

PURPOSE:To detect a step-out while an invalid frame is passing and to complete the pull-in by producing the invalid frames so that they remain in the number larger than the frame stages for the protections of synchronization which are used by each node. CONSTITUTION:The pre-announcement signal for the cut of power supply is delivered from a node 7 and detected by a supervisory equipment 2. Then plural invalid frames are produced continuously from a frame generating part 5. A junction box 3 performs a changeover processing when those invalid frames are transmitted at a time point t1. Here this changeover processing changes the length of the invalid frame. The synchronizing signal SY of the first invalid frame is detected at a node 11 connected to a junction box 4 at the downstream side. Then it is impossible to detect the next synchronizing signal after a prescribed time TO. Such actions are carried out in three times. Thus the pull-in control is performed and the frame synchronizing signal SY is detected at a time point t2. Hereafter the signals SY are detected continuously in three times after a prescribed time TO. Then the end of the pull-in is decided and the normal transfer of data is performed.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Embodiment (a) Configuration of an Embodiment (Fig. 2) ('b) Operation of the present invention (Figures 2, 3, and 4) Effects of the invention [Summary] A junction box is connected to the loop transmission line, and a node is connected to the subloop transmission line via the junction box. In this transmission system, the subloop transmission path is disconnected while invalid frames are being transmitted.

[Industrial application field]

The present invention handles synchronization loss that occurs after disconnection of a specific subloop within a dummy frame, without requiring control over synchronization protection of each node related to a bypass device such as a junction box connected to a loop-shaped transmission line. This invention relates to a junction box control method that allows processing without affecting actual communications.

As a data communication network, a system in which multiple nodes (terminal stations) are connected on a loop transmission path has been developed. Furthermore, a network configuration has also been proposed in which a subloop is connected to a loop transmission path to enable system expansion and contraction in the event of a failure.

[Conventional technology]

For example, as shown in FIG. 5, in a loop-shaped transmission line ML,
Monitoring device Sv and junction box JBX1. JB
X2... and node numbers etc. as necessary, and connect the sub loop SL1... to the junction box.
SL,... are provided, and nodes Nt are connected to these sub-loops.
, Nt, Ns, etc. are connected, and a frame signal is transmitted to these to transmit and receive data. A frame synchronization method is used.

In such a conventional frame synchronization method, as shown in Fig. 6, data is transmitted by adding a frame synchronization signal SY to the beginning of the data. For protection, protect against frame synchronization.

Normally, the frame synchronization signal SY is always monitored at every timing T when the frame synchronization signal comes, and even if this is not detected at that timing, for example, once, the frame synchronization remains in the retracted state, and a certain number of frame synchronizations are performed. It is only when the signal does not arrive that it is determined that synchronization has been lost and a new synchronization pull-in operation is performed.

In FIG. 6, since the frame synchronization signal SY is inserted at an interval of - frame period, the node approximately predicts the transmission timing of the frame synchronization signal 8Y using an internal timer such as a clock counter. The detection control of this frame synchronization signal SY is started near this point. By the way, in the case where a bit error occurs in the frame synchronization signal due to noise in the transmission path, etc.2, if the synchronization is determined to be out of synchronization based on the frame synchronization signal not being detected a short number of times, such as once or twice, the actual data Since the amount of data that cannot be received increases even though the frame synchronization signal has been transmitted, protection is provided such that an error occurs when the frame synchronization signal is not detected n times.

This number of n is determined by the system. If n
In the system with = 3, as shown in FIG. 6, since the frame synchronization signal 8Y has a bit error, processing is performed on the assumption that frame synchronization has been detected even if frame synchronization is not detected at time 2 1o. in this case.

Time 1. Since the next frame synchronization signal SY is detected at , there is no problem, but if following to, t,.

When no frame synchronization signal is detected at t2, processing is performed as an error occurrence, and continuous frame synchronization signal detection is performed without intermittent synchronization signal detection by the timer. Once this was detected, frame synchronization signal detection was performed continuously at the next scheduled timing to confirm synchronization pull-in and resume data transmission and reception.

Now in junction box JBX, node N
When the transmission line ML is disconnected from the transmission line ML due to a power outage in the junction box JBX.

When the transmission path ML is switched to the bypass side to form a bypass for the subloop SL1 within the subloop 8L, data being transmitted within the subloop 8L is damaged. Moreover, the data length becomes shorter based on this switching, so in the next frame -
Since the frame synchronization signal is transmitted at a timing shorter than that, loss of synchronization occurs, and valid data is discarded until the loss of synchronization is recovered.

In order to improve the discarding of valid data in such a large number of frames, the applicant of this patent filed Japanese Patent Application No. 59-25627.
No. 2 proposed sending out a dummy frame without valid data at the time of switching, and performing switching control using this dummy frame.

[Problem that the invention seeks to solve]

However, although this improves the problem of valid data being damaged because the dummy frame is damaged during switching, the dummy frame length changes, resulting in loss of synchronization on the downstream side and the need to re-synchronize. Valid data will be discarded.

In order to prevent valid data from being discarded due to this loss of synchronization, it is necessary to add a desynchronization signal to the dummy frame, and to have hardware that detects and operates the next frame synchronization signal after the dummy frame. Therefore, it is an object of the present invention to always update the next valid frame after a dummy frame without damaging or discarding valid data or complicating the hardware. [Means for Solving Problems] By Providing a Junction Box Control System That Enables Establishment of Synchronization [Means for Solving Problems] FIG. 1 is an explanatory diagram of the principle of the present invention. In Figure 1,
Reference numeral 1 denotes a loop-shaped transmission line, and a monitoring device (S node) 2 and junction boxes 3 and 4 are connected to this transmission line 1. A sub-loop transmission line (hereinafter referred to as sub-loop) 9 to which a plurality of nodes 7 and 8 for transmitting and receiving data are connected is connected to the junction box 3, and a switching control section 10 is also provided. Junction box 4 is configured similarly to junction box 3.

A subloop 12 to which the node 11 is also connected is connected. The monitoring device 2 is also provided with a frame generator 5 that outputs valid frames or invalid frames (dummy frames), and a frame buffer memory (FBM) 6 that temporarily holds data on the transmission line 1. Switching control section 1
0 outputs either the transmission line 1 or the subloop 9, and when the subloop 9 is connected to the transmission line 1, the data transmitted from the subloop 9 is output.

When subloop 9 and subloop 12 are connected to transmission line 1 and are operating normally, transmission line 1 and subloop 9, 1
For example, when node 7 is disconnected due to a power cut, the switching control unit 10 switches the input side from the subloop 9 to the transmission line 1. However, when the node 7 outputs a power-off notice signal, the monitoring device 2 detects this and causes the frame generation unit 5 to continuously generate a plurality of invalid frames. Junction box 3 performs switching processing when this invalid frame is transmitted at time 11, but at that time, the length of the invalid frame changes due to this switching processing, and node 11 connected to junction box 4 downstream thereof , after detecting the synchronization signal SY of this first invalid frame, the next synchronization signal cannot be detected after a predetermined period of time, and 3
This is done twice. As a result, synchronization pull-in control is performed and a frame synchronization signal SY is detected at time t2. Then, after a predetermined time To has elapsed, after detecting the frame synchronization signal 8Y three times in succession, it is determined that the synchronization pull-in is complete, and normal data transmission and reception is performed.

[Effect]

In the present invention, based on the change in invalid frame length that occurs during switching processing in the junction box 3, the nine nodes 11 connected to the downstream junction box 4 are
Since invalid frames are continuously transmitted during the synchronization loss and synchronization/synchronization processing in It can be processed without giving.

〔Example〕

An embodiment of the present invention will be described in detail with reference to FIGS. 2, 3, and 4.

FIG. 2 is a block diagram of an embodiment of the present invention, and FIGS. 3 and 4 are diagrams explaining its operation.

(a) - Good example configuration Figure 2 (a) is a configuration diagram of an embodiment of the present invention, Figure 2 (b) is an explanatory diagram of the frame at the time of advance notice of power outage or connection, Figure 2 (C) is
(d) is an explanatory diagram of an invalid frame when the power is turned off, and (d) is an explanatory diagram of an invalid frame when the power is connected.

In Fig. 2, the same reference numerals as in other figures indicate the same parts, and 2
1 is a frame determination unit, as shown in FIG. 2(b),
22 checks whether or not a power-off notice signal is written in the frame ladder FH, reads out the address of the ON frame, and reports these to the control unit 23. 22 erases the invalid frame. A transmission selector selectively outputs data transmitted from the frame generation unit 5 or frame buffer memory 6; 23 is a control unit that controls which of two inputs the output of the transmission selector 22 is to be sent to; It controls the generation of invalid frames or valid frames from the frame generation section 5, and the writing and reading of data into and from the frame buffer memory 6.

The switching control section 10 of the junction box 3 is provided with a command analysis circuit 31 and a selector 32. The command analysis circuit 31, as shown in FIG. 2(C), decodes the disconnection command and address written in the frame head FH, and controls the selector 32 in accordance with the decoding result.

The node 7 has a frame synchronization circuit 41. Power cutoff notice signal circuit 42. A data communication control circuit 43 etc. are provided,
Further, nodes 8 and 11 are also configured similarly to node 7. The frame synchronization circuit 41 detects a frame synchronization signal SY to perform frame synchronization, and has a counter (not shown) for counting a clock. If a prescribed number of frame synchronization signals 8Y cannot be detected consecutively, the counter operating as a timer is stopped.

The zero power cutoff notice signal circuit 42, which detects the next frame synchronization signal and performs the synchronization pull-in operation again, sends the frame head FH when the power cutoff occurs at the node 7, as shown in FIG. 2(b). A flag FLG serving as a power cutoff notice signal and the address of the node 7 are entered. The data communication control circuit 43 sends and receives data to and from valid frames, and recognizes that a disconnection command is set in the frame head FH for invalid frames. No access 0 (b) Operation of the present invention Next, the operation of the present invention will be explained.

(2) Normally, the selector 32 of each junction box 3.4 operates so as to accommodate its sub-loop 9, 12 in the transmission line 1. At this time, the frame is transmitted to the monitoring device 2 via the transmission line 1, and the valid frame is transmitted to the frame buffer memory 6. This frame buffer memory 6 operates so that the length of the transmission path including the sub-loops 9 and 12 is an integral multiple of the length of the effective frame. When the frame synchronization signal SY of a valid frame is located at the beginning of the frame buffer memory 6, the frame synchronization signal SY is transferred to the frame in order to correct bit errors that may exist in this frame synchronization signal SY due to line noise, etc. It may be controlled so that the generation unit 5 generates more than one. In this way, normally, the effective frame of the frame period % is: Monitoring device 2 - Transmission line 1 - Junction box 3 (subloop 9) - Junction box 4 (subloop 12) - Transmission line 1 - Monitoring device 2
is being transmitted.

■ By the way, when there is a request to turn off the stain source to the node 7 in the sub-loop 9 for some reason, the power cut-off notice signal circuit 42 of the node 7 sends the tl<, valid frame as shown in FIG. 2(b). During frame header F'H.

It sets a power-off notice signal and sets the address of its own node in its address field. A valid frame having a frame header filled with this information is transmitted to the frame determination unit 21 of the monitoring device 2 via the node 7 - node 8 - junction box 3 - junction box 4 - note 11 - junction box 4. At this time, the frame determination unit 21 detects that the power-off notice signal is turned on, reads the address part, recognizes that there is a power-off notice from the node 7, and transmits this to the control unit 23. and reset the power-off warning signal.

After this valid frame is sent to the transmission path 1 via the frame buffer memory 6, the control unit 23 instructs the frame generation unit 5 to set a disconnection command OFF to the frame in the node 7. Sends an invalid frame with the address added to the address field. As shown in FIG. 3, the number of invalid frames is assumed to be sufficiently longer than the number of stages of synchronization protection performed by the frame synchronization circuit 31 of each node. Data communication control circuit 3 for each node 7, 8, etc.
In step 3, it is recognized that the disconnection command OFF in an invalid frame is set, this is identified as an invalid frame, and this frame is not accessed. When this invalid frame reaches the junction box 3 whose subloop includes the node 7 that forewarned the power-off, the command analysis circuit 31 recognizes that the disconnection command OFF has been set, reads its address part, and automatically It is confirmed that this node 7 is included on the sub-loop 9 of the junction box 3. Based on these recognitions, the command analysis circuit 31 controls the selector 32 to bypass the sub-loop 9, and the selector 32 Operate to output the transmitted data. Thus node 7
Since the subloop 9 to which the node 7 is connected is disconnected from the transmission line 1, the power to the node 7 can be turned off.

■ When the selector 32 in the junction box 3 switches the input side from the subloop 9 to the transmission line 1 side, the invalid frame existing on the subloop 9 will disappear, and as a result, as shown in FIG. ), the first several invalid frames are in a state where the dummy data parts DM and DMt are partially connected, and the length of the first invalid frames changes from T to T. .

■ Therefore, in the node 11 downstream of the junction box 3, its frame synchronization circuit (not shown) detects the frame synchronization signal SY at time t1, and the frame length To
Even if an attempt is made to detect the next frame synchronization signal 8Y later, it cannot be detected. Since the frame synchronization signal 8Y could not be detected three times in a row, the υ synchronization protection period ended and the υ frame synchronization circuit continuously detected the frame synchronization signal 8Y. , As a result, at time t2, the next frame synchronization signal SY
Detect. When the frame synchronization signal 8Y is detected a total of three times at intervals of 10 frame lengths, the synchronization protection period ends, and resynchronization is completed at time t3, returning to the normal state. However, the data communication control circuit (not shown) of the node 11 detects that the disconnection command OFF is written in the frame head detected at time t3, and learns that this is an invalid frame. The necessary data will be transmitted and received in subsequent valid frames.

■ When such an invalid frame is transmitted to the monitoring device 2 after going around the transmission path 1, the frame determination unit 21 identifies it as an invalid frame due to the presence of the disconnection command OFF, and Since these invalid frames are not transmitted to the e-buffer memory 6, they are erased by the frame determination section 21.

(2) On the other hand, when the subloop 9 is accommodated in the transmission line 1, after the subloop is separated, the detection circuit 33 provided in the junction box monitors the signal from the subloop side. Then, when the power of the nodes in the subloop is turned on and communication becomes possible again, a normal frame synchronization signal is transmitted to the subloop side signal line of the selector in the junction box.

The detection circuit 33 detects this, and the command analysis circuit 31
to notify. The command analysis circuit 31 is.

Connection notice signal in the frame header of the passing frame (
(see FIG. 2(a)) and writes the address of the node in the subloop in the address field.

Upon receiving this, the monitoring device 2 sets a connection command in the frame header, and sends out an invalid frame (see FIG. 2(d)) with a number of synchronization protection stages equal to or greater than the address of the node set in the address field. (The operation of S■ here is the same as when cutting a subloop.) When the invalid frame reaches the junction box, the command analysis circuit analyzes the address and switches the selector. (See Figure 4) At this time, as shown in Figures 3(a) to 3(C), due to the delay on the subloop, a destroyed valid frame D2 flows on the transmission path, but this subframe The effective frame D that passed immediately before the connection of
It is the same as 2 and does not affect actual communication.

The monitoring device notices that the connection command in the frame header is set and erases invalid frames and corrupted valid frames.

By sending invalid frames that exceed the number of synchronization protection stages, υ
, without removing synchronization protection at downstream nodes.

Communication can be resumed immediately with the next valid frame.

A node within the subloop learns that communication is possible due to the passage of an invalid frame in which the address of a node within its own subloop is set.

When an invalid frame is output, since the valid frame is held in the frame buffer memory 6, valid data will not be lost.

Incidentally, in the above explanation, an example was explained based on the number of synchronization protection stages, but the number of synchronization protection stages is of course not limited to this, and can be determined as appropriate. The same applies to the case where the transmission line is a double loop as shown in FIG.

〔Effect of the invention〕

In the present invention, bypass control is performed by generating the number of invalid frames so that the number of invalid frames remains equal to or greater than the number of frame stages of synchronization protection used by each node. detection and synchronization retraction can be completed. Therefore, when the next valid frame arrives, synchronization is always established and normal communication is possible. Therefore, it is possible to use hardware on the mate side that is substantially the same as conventional hardware.

In this way, according to the present invention, without controlling the synchronization protection of each node, it is possible to deal with a power outage of a node on a subloop, etc. without affecting actual communication at all. A highly reliable system can be constructed at low cost.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is an embodiment of the present invention,
3 is an explanatory diagram of the operation of the present invention, FIG. 4 is a diagram illustrating an example of sub-loop connection, FIG. 5 is an example of a conventional loop-shaped transmission path, FIG. 6 is an explanatory diagram of the conventional operation, and FIG. 7 is another example of a loop-shaped transmission line. 1...Transmission line 2...Monitoring device 3.4...Junction box 5...
...Frame generation unit 6...Frame buffer memory 7.8...
...Node 9 ...Sub loop 10
......Switching control section 11...Node 12
・・・・・・Sub loop

Claims (1)

[Scope of Claims] A data transmission/reception system in which a monitoring device (2) and a junction box (3) are connected to a loop-shaped transmission path (1), and a node is connected to a sub-loop transmission path of the junction box, comprising the steps of: A disconnection request output means for requesting disconnection from the transmission path is provided, and the monitoring device (2) is provided with a frame generation unit (5) that continuously outputs invalid frames with a number of steps greater than the number of synchronization protection steps of the node, The junction box (3) is provided with a switching control unit (10) for identifying a node to be disconnected, so that the junction box disconnects a subloop connected to a node that has issued a disconnection request during the transmission of the invalid frame. At the same time, the lower node performs resynchronization pull-in and synchronization establishment during the passage of the invalid frame.