JPS58116835A - Node extension system - Google Patents

Node extension system

Info

Publication number
JPS58116835A
JPS58116835A JP21362181A JP21362181A JPS58116835A JP S58116835 A JPS58116835 A JP S58116835A JP 21362181 A JP21362181 A JP 21362181A JP 21362181 A JP21362181 A JP 21362181A JP S58116835 A JPS58116835 A JP S58116835A
Authority
JP
Japan
Prior art keywords
transmission line
node
data
extension
loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21362181A
Other languages
Japanese (ja)
Inventor
Takashi Tazaki
田崎 堅志
Akira Takeyama
明 竹山
Tokuhiro Aritaka
有高 徳裕
Satoshi Nojima
聡 野島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21362181A priority Critical patent/JPS58116835A/en
Publication of JPS58116835A publication Critical patent/JPS58116835A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To prevent the occurrence of a data error during node extension by inserting an extension transmission line into a main transmission line after obtaining the synchronism of data on the main transmission line with that on the extension transmission line. CONSTITUTION:An existent node 100 is equipped with a T branch circuit 10, synchronizing elastic buffer 11, and transmission line 12 and is connected to a transmission line. When an extension node 20 is added to it nearly, a signal branched from the circuit 10 is transmitted to the buffer 11 via the extension node 200. Through an extension transmission line 2, the node 200 is connected to the transmission line 1 on branch basis. Then, the nose 100 performs frame synchronization between data in the buffer 11 and data on the transmission line 1 and then changes a switch 12 from the transmission line side 1 over to the buffer side 1 once completing the synchronization. This system eliminates the occurrence of a data error due to a step out in loop-back operation, performing the extremely smooth extension.

Description

【発明の詳細な説明】 (1)  発明の技術分野 本発明は、情報処理ネットワークにおけるノードの増設
方法に係り、特に伝送路上のデータの流れを乱すことな
く伝送路を切換え、ノードの増設を行う方式に関する。
[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a method for adding nodes in an information processing network, and in particular, switching transmission paths and adding nodes without disturbing the flow of data on the transmission path. Regarding the method.

(2)技術の背景 コンビ、−夕の分散処理とオフィスオートメーシ嘗ンの
普及が進めば、ループネットワーク方式は急速に浸透す
る可能性がある。比較的狭い地斌に分散したコンビ、−
夕や端末機器を相互接続するローカル・ネットワーク方
式などは、米国を中心に商用化されはじめた。
(2) Technical background: - If distributed processing and office automation become more widespread, the loop network method may spread rapidly. A combination dispersed in a relatively narrow ground, -
Local network systems for interconnecting terminal devices have begun to be commercialized mainly in the United States.

WJI図はループネットワークのモデルで、T(08T
はホストコンビ、−タ、CCPFi回線制御装置、CN
はセンターノード、Svはループ全体の監視制御ノード
、TNはターミナルノードで、各ターミナルノードには
、ファクシミリ(FAX)、プリンタ(printer
)、ワードプロセサ(w−p)グラフィック端末などの
各種端末が接続される。
The WJI diagram is a model of a loop network, T (08T
is a host combination, -ta, CCPFi line controller, CN
is the center node, Sv is the monitoring control node for the entire loop, TN is the terminal node, and each terminal node has a facsimile (FAX) and a printer (printer).
), a word processor (WP), a graphic terminal, and other various terminals are connected.

このようなネットワークでは、各端末はホストコンピュ
ータを使用できるだけでなく、それぞれのノードを介し
てユーザ間のデータ通信を行うことができる。
In such a network, each terminal can not only use a host computer but also perform data communication between users via respective nodes.

またとのようなネットワークはオフィス内、ビル内2本
社工場と地方工場間のデータ通信などに好適であり、急
速に普及しそうな状勢にある。
Networks like Matato are suitable for data communications within offices and between two main factories in buildings and local factories, and are likely to become popular rapidly.

(3)従来技術と問題点 既設のループ型ネ、トワークに新たにノードを増設する
方法として、従来は第2図(a)、 (b)、 (e)
に示す手順で行われている。第2図はループ部分のみを
示す。
(3) Conventional technology and problems As a method of adding new nodes to an existing loop-type network, the conventional method is as shown in Figures 2 (a), (b), and (e).
This is done according to the steps shown below. FIG. 2 shows only the loop portion.

第2図(a)、 (b)、 (c)においてCN、TN
は既に説明した。TNXは増設しようとするノード、A
In Fig. 2 (a), (b), and (c), CN and TN
has already been explained. TNX is the node to be expanded, A
.

BFiループの名称で九個のループをAループ、内側の
ループt−Bループと名づける、 即ち21f系ループで、通常はAループを使用している
が障害発生時にはBループに切換えられるようになって
いる。
The nine loops are named the A loop and the inner loop t-B loop in the BFi loop name. In other words, it is a 21f system loop, and normally the A loop is used, but it can now be switched to the B loop in the event of a failure. ing.

上記の如きループネットワークに新たにノードTNXを
増設しようとする場合は、第2図(b)の如(TNI、
TNi+1のノード内でAループ、Bループ′を接続し
て新たな閉ループを構成する。このよりな方法をループ
バックと呼ぶ。次いで新ノードTNXを挿入し終ったと
ころでループパラクラ解除し、第2図(c)の如く増設
が完了する。
When trying to add a new node TNX to the above loop network, as shown in Figure 2 (b) (TNI,
A new closed loop is constructed by connecting A loop and B loop' within the node of TNi+1. This better method is called loopback. Next, when the new node TNX has been inserted, the loop paralysis is released, and the expansion is completed as shown in FIG. 2(c).

ところがこのループパ、タ方式によると、Aループ、B
ループを接続し一つのループを形成シても、フレーム同
期はずれが起き、データエラーが生ずる。Aループ、B
ループはもともと別のループで、それぞれのループ内で
同期はとっているが、Aループ、Bループ間の同期はと
っていない。
However, according to this loop pattern, A loop, B
Even if the loops are connected to form one loop, frame synchronization will occur and data errors will occur. A loop, B
The loops are originally separate loops and are synchronized within each loop, but the A and B loops are not synchronized.

従って監視制御ノードSvの働きをもってしても、同期
はずれが起ることになる。
Therefore, even with the function of the supervisory control node Sv, a loss of synchronization will occur.

(4)発明の目的 本発明は、従来方式におけるノード増設時のデータエラ
ー発生を防止し、ネットワークの運用に影響を与えない
ノード増設方式を提供することにある。
(4) Purpose of the Invention The object of the present invention is to provide a node addition method that prevents the occurrence of data errors when adding nodes in the conventional method and does not affect network operation.

(5)発明の構成および実施例 本発明の基本構成を第3図に示す。(5) Structure and embodiments of the invention The basic configuration of the present invention is shown in FIG.

ノード100はT分岐回路10、同期用エラスティック
バッファ11、伝送路スイッチ12、および処理部13
からなり、伝送路1に接続されている。これに新たにノ
ード200を増設する場合、T分岐回路10から分岐さ
れた信号をノード200経由で同期用エラスティックバ
ッファ11へ伝送する。増設伝送路2によって、ノード
200は伝送Wlr1へ分岐接続される。
The node 100 includes a T branch circuit 10, a synchronization elastic buffer 11, a transmission path switch 12, and a processing section 13.
and is connected to the transmission line 1. When a new node 200 is added to this, the signal branched from the T branch circuit 10 is transmitted to the synchronization elastic buffer 11 via the node 200. The node 200 is branch-connected to the transmission Wlr1 by the additional transmission line 2.

次いでノード】00では、同期用エラスティックバッフ
ァ11内のデータと伝送路】上のデータのフレーム同期
をと9、同期がとれたところで伝送路スイッチ12を、
伝送路1@から同期用エラスティックバッファll側に
切り換える。
Next, node ]00 performs frame synchronization between the data in the synchronization elastic buffer 11 and the data on the transmission path.
Switch from the transmission line 1@ to the synchronization elastic buffer ll side.

以上で増設動作は完了するが、第4図を用いて本発明の
細部を更に説明する。
Although the expansion operation is completed above, the details of the present invention will be further explained using FIG. 4.

第4図(a)はノード増設前の伝送路上のフレームの状
態を示す。Fはデータフレーム先頭のフラグビy)、f
l’lはn番目のフレームの、データである。
FIG. 4(a) shows the state of frames on the transmission path before adding nodes. F is the flag y at the beginning of the data frame), f
l'l is the data of the nth frame.

矢印はデータの流れを示し、21には処理部13からデ
ータが流入し、22からは他のノードヘデータが流れ、
23は分岐回路から増設ノードへのデータの流れを、2
4は増設ノードからのデータの流れを示す。
Arrows indicate the flow of data; data flows into 21 from the processing unit 13, data flows from 22 to other nodes,
23 represents the flow of data from the branch circuit to the expansion node.
4 shows the flow of data from the expansion node.

第4図(b)°は同期用エラスティックバッファ(以下
バッファと略す)11がなく、フレーム位置不一致の場
合を示す。
FIG. 4B shows a case where there is no synchronization elastic buffer (hereinafter abbreviated as buffer) 11 and the frame positions do not match.

第4図(C)はバッフ711の作用により同期がとれた
場合を示す。伝送路lと伝送路20線路長が違うので第
4図(C)のP点では各伝送路上のデータの位相が合わ
ないのであるが、バッファ11の長さを調節することに
より位相を合わせることができる。同期がとれたところ
で第4図(d)に示す如く、伝送路スイッチ12tバツ
フア11側に接続し、増設が完了する。
FIG. 4(C) shows a case where synchronization is achieved by the action of the buffer 711. Since the lengths of transmission line 1 and transmission line 20 are different, the phases of the data on each transmission line do not match at point P in FIG. 4(C), but the phases can be matched by adjusting the length of buffer 11. I can do it. When synchronization is achieved, the transmission line switch 12 is connected to the t buffer 11 side, as shown in FIG. 4(d), and the expansion is completed.

同期(フラグビットの位置)監視、および伝送路スイッ
チ12の切り換え制御などはすべて処理1lI13で行
なうことができる。この動作は例えば伝送路1とバッフ
ァ11のフラグビットを同時に検出した時にAND回路
を動作させ、AND回路の出力で、伝送路スイッチ12
を切り換えることにより容易に実現できる。
Synchronization (position of the flag bit) monitoring, switching control of the transmission path switch 12, etc. can all be performed by the processing 1113. In this operation, for example, when the flag bits of transmission line 1 and buffer 11 are detected simultaneously, an AND circuit is operated, and the output of the AND circuit is used to operate the transmission line switch 12.
This can be easily achieved by switching.

(6)  発明の詳細 な説明した如く、本方式ではループバック時の同期はず
れによるデータエラーの発生などがなく、極めてスムー
ズに増設が行なえるという大きな効果がある。高速・多
重の通信ネットワークにおいては、わずかな時間の回線
の乱れも、大きな影醤を与えることになるので、本発明
の効果は極めて大である。
(6) As described in detail, this method has the great effect of not causing data errors due to out-of-synchronization during loopback, and allowing for extremely smooth expansion. In a high-speed, multiplex communication network, even a slight disturbance in the line can have a big impact, so the effects of the present invention are extremely significant.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のループネットワークの基本構成を示す図
、第2図は従来のノード増設を説明する図、第3図は本
発明ノード増設方式を説明する図、第4図は既設伝送路
と増設ノードとの同期合わせを説明する図′t%ある。 第3図において、100は既設ノード、200は増設ノ
ード、10はT分岐回路、11は同期用エラスティ、ク
バ、ファ。 12は伝送路スイッチ、13は処理部である。 薄 1 囚 茸2図 奪 3ri!J
Figure 1 is a diagram showing the basic configuration of a conventional loop network, Figure 2 is a diagram explaining conventional node addition, Figure 3 is a diagram explaining the node addition method of the present invention, and Figure 4 is a diagram showing the existing transmission line and There is a diagram 't% explaining synchronization with an additional node. In FIG. 3, 100 is an existing node, 200 is an expansion node, 10 is a T-branch circuit, and 11 is a synchronization elasty, kuba, and fa. 12 is a transmission path switch, and 13 is a processing section. Usui 1 Prisoner mushroom 2 drawing 3ri! J

Claims (1)

【特許請求の範囲】[Claims] 主伝送路と主伝送路に接続されて機能する装置とt接続
するノードに、前記主伝送路と増設用ノードを含む増設
伝送路とにデータを分岐する分岐回路と、前記増設伝送
路の出力データと前記主伝送路を経由したデータの同期
を調整するためのエラスティックバッファと、前記主伝
送路と前記増設伝送路を切換えるだめの伝送路スイッチ
とを設け、前記画伝送路内のデータの同期がとれた場合
に前記伝送路スイッチを作動させ、増設用ノードを含む
前記増設伝送路を主伝送路に挿入することを特命とする
ノード増設方式。
A branch circuit that branches data between the main transmission path and an expansion transmission path including an expansion node, at a node connected to the main transmission path and a device that functions by being connected to the main transmission path, and an output of the expansion transmission path. An elastic buffer for adjusting the synchronization of data and data via the main transmission line, and a transmission line switch for switching between the main transmission line and the additional transmission line are provided, and the data on the image transmission line is A node expansion method in which, when synchronization is achieved, the transmission path switch is activated and the expansion transmission path including the expansion node is inserted into the main transmission path.
JP21362181A 1981-12-29 1981-12-29 Node extension system Pending JPS58116835A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21362181A JPS58116835A (en) 1981-12-29 1981-12-29 Node extension system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21362181A JPS58116835A (en) 1981-12-29 1981-12-29 Node extension system

Publications (1)

Publication Number Publication Date
JPS58116835A true JPS58116835A (en) 1983-07-12

Family

ID=16642196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21362181A Pending JPS58116835A (en) 1981-12-29 1981-12-29 Node extension system

Country Status (1)

Country Link
JP (1) JPS58116835A (en)

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