JPH05199250A - Clock changeover system - Google Patents

Abstract

PURPOSE:To automate the changeover of a clock signal by sending a switching request from a master transmitter through the delivery of occurrence of a fault from a slave transmitter whose fault occurrence is detected and switching sequentially a transmission line. CONSTITUTION:When a fault of a transmission line takes place at a point X between slave transmitters 14 and 15, a fault detection source device 14 sends a fault occurrence signal FD via a transmission line 16 and slave transmitters 13-11 send the signal FD. Upon the receipt of the signal FD, the master transmitter 10 sends a switching request signal SW via a transmission line 17. The slave transmitters 11-13 receive a signal SW to extract a clock from the transmission line 17 and transfers sequentially the signal SW. Upon the receipt of the signal SW, the device 14 replaces an internal clock with a clock extracted from the data of the transmission line 17. Thus, no manual clock changeover on the occurrence of a fault of the transmission line is required and the synchronization clock is automatically restored at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock switching system, and in particular, it is constructed by connecting a plurality of transmission devices in a ring shape and operates all of these transmission devices in synchronization with one clock. The present invention relates to a clock switching system that switches clocks in the case of a transmission line failure in a synchronous ring system.

[0002]

2. Description of the Related Art Conventionally, in this type of synchronous ring configuration system, a master device (hereinafter referred to as a master transmission device) and a transmission device (hereinafter referred to as a slave transmission device) that operates according to a clock from the master transmission device. Device) and each transmission device can bidirectionally transmit data according to this clock. Specifically, in the slave transmission device, the clock transmitted in one direction from the master transmission device is extracted and used as the clock of the slave transmission device, and the clock is transmitted in one direction to the next transmission device. Was there. After that, the clocks are sequentially transmitted in one direction by the same operation, and finally returned to the master transmission device.

In this configuration, when a failure occurs in the transmission path for transmitting the clock and the clock cannot be received, the transmission device located downstream from the failure occurrence location cannot extract the clock of the transmission path. ..

In this case, a fault is detected in the slave transmission device located immediately after the fault occurrence position, and the clock generated in this slave transmission device is transmitted to the transmission line instead of the clock from the master transmission device. ing. Thus, in a system that transmits the clock of the slave transmission device instead of the clock of the master transmission device, network synchronization cannot be achieved.

On the other hand, when a failure occurs, the slave transmission devices may be sequentially switched so that each slave transmission device extracts the clock transmitted from the master transmission device to the transmission line in the direction opposite to the conventional transmission line. Has been done. In this case, each slave transmission device needs to switch the transmission path from which the clock is extracted. Switching of the transmission paths in each of the transmission devices, that is, switching of the clock is normally performed manually in order from the master side to the transmission device that has detected the transmission path failure. Further, even when the failure of the transmission path is recovered, the transmission path, that is, the clock is switched back manually in each transmission device.

[0006]

However, in such a conventional clock switching system, it is necessary to manually control the clock switching when the transmission line fails. Therefore, there is a problem that the switching requires manpower and the system does not function as a synchronization network synchronized with the clock of the master transmission device until the switching is completed.

In view of the above-mentioned drawbacks, the technical problem of the present invention is to provide a ring-based synchronous network system,
It is to provide a method of automatically switching clock signals when switching the clock extraction direction when a transmission line failure occurs.

[0008]

According to the present invention, a master transmission device and a plurality of slave transmission devices are connected in a ring shape, and the plurality of slave transmission devices are synchronized with a clock from the master transmission device. In a clock switching system used for a ring-shaped synchronous network capable of bidirectional transmission in a clockwise direction and a counterclockwise direction, one of the slave transmission devices is provided with a clock transmitted from the master transmission device in a predetermined direction. When the stop is detected, the one slave transmission device transmits the stop of the clock in the predetermined direction to the master transmission device,
In the master transmission device, a clock switching method is characterized in that a switching request signal instructing to switch the transmission direction to a direction opposite to the predetermined direction is transmitted in the reverse direction to a slave transmission device that has detected a clock stop. can get.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

1A, 1B, 1C, 1D,
Referring to (E) and (F), the clock switching method according to the embodiment of the present invention is applied to a master transmission device 10 and first to fifth slave transmission devices 11, 12, 13, 14, and 15. A case will be described where is applied to a synchronous network in which the outer transmission line 16 and the inner transmission line 17 connect in a ring shape. Here, it is assumed that data is transmitted counterclockwise to the outer transmission line 16 and data is transmitted clockwise to the inner transmission line 17.

Further, the master transmission device 10 is provided with a master clock generator 20 for generating a master clock, and this master clock is sent from the master transmission device 10 to the outer and inner transmission lines 16 and 17. ing. In each of the slave transmission devices 11 to 15, it is assumed that in the normal state, the master clock is extracted from the outer transmission line 16 to generate the internal clock pulse. As described above, in the normal state, each slave transmission device 11 to 15 operates according to the internal clock pulse synchronized with the master clock, and transmits data in the clockwise or counterclockwise direction via the inward or outward transmission lines 16 and 17. It is assumed that data is transmitted in the clockwise direction according to the master clock. Therefore, in the normal state, as shown in FIG. 7A, all the transmission devices 10 to 15 operate in synchronization with one master clock in the counterclockwise direction. Although not shown in FIG. 1A, each slave transmission device 11 to 15 includes an internal clock generator that generates an internal clock.

Here, as shown in FIG. 1B, it is assumed that a transmission line failure has occurred at a point X between the fifth slave transmission device 15 and the fourth slave transmission device 14.
In this case, the fourth slave transmission device 14 cannot extract the master clock, and the occurrence of a transmission line fault is detected by monitoring the interruption of the master clock. Here, the fourth slave transmission device 14 is called a failure detection source device.

When the occurrence of a failure is detected, the fourth slave transmission device 14 switches to the internal clock generator and sends out the data signal by this internal clock. The data signal contains overhead, and the fourth slave transmission device 14 transmits a failure occurrence signal FD, which indicates the occurrence of a transmission path failure in this overhead, to the third counterclockwise direction via the outer transmission path 16. To the slave transmission device 13 of. The third to first slave transmission devices 13 to 11 transmit the failure occurrence signal FD one after another, and the failure occurrence signal FD is finally given to the master transmission device 10.

As shown in FIG. 1C, the master transmission device 10 has a fault occurrence signal FD indicating the occurrence of a transmission line fault.
When it receives, the clock switching request signal SW is transmitted in the clockwise direction to the first slave transmission device 11 by using the overhead. The first slave transmission device 11 receives the switching request signal SW and switches the clock extraction source. As a result, the first slave transmission device 11 extracts the clock from the transmission path 17 around the inner side.

In the first slave transmission device 11 which has switched the clock extraction source, as shown in FIG.
The switching request signal S toward the second slave transmission device 12
W is transferred using overhead, and in the device 12,
The switching request signal SW is received, the clock extraction source is switched, and the switching request signal SW is sent to the third slave transmission device 13. As a result, the second slave transmission device 12
Are switched to extract the clock from the inner transmission line.

Also in the third slave transmission device 13, FIG.
As shown in (E), after receiving the switching request signal SW, the clock extraction source is switched, and the switching request signal SW is sent to the fourth slave transmission device 14, that is, the failure detection source device.

As shown in FIG. 1 (F), when the failure detection source device 14 receives the switching request, it switches the clock from the internal clock to the clock extracted from the clockwise transmission path data, and the switching completion indicating the switching completion. The signal SC is transmitted in the counterclockwise direction to the master transmission device 10 via the third to first slave transmission devices 13 to 11 using the overhead.

2 (A), (B), (C), and (D)
The procedure of switching back the clock when the failure at the point X is recovered will be described with reference to FIG. When the fault is recovered,
As shown in FIG. 2A, the fourth slave transmission device 14
Switches back the clock extraction source to the counterclockwise transmission path data, and sends the switching back request signal RR to the third slave transmission device 13 using the overhead.

Next, as shown in FIG. 2B, after the third slave transmission device 13 also receives the switchback request, the clock extraction direction is switched from the inward transmission line 17 to the outer transmission line 16, The switchback request signal RR is sent to the second slave transmission device 12. Thereafter, similarly, the second and first slave transmission devices 12 and 11 sequentially switch the clock extraction direction back to the outer transmission line 16 (FIGS. 2C and 2D).

Switchback request RR to master transmission device 10
At the stage when the signal is transmitted, network synchronization is established in the state before the failure of the entire ring-configured synchronous network.

The configuration of the slave transmission device that performs the above operation will be described with reference to FIG. Since the first to fourth slave transmission devices 11 to 14 have the same configuration, the slave transmission device is indicated by 1n in FIG.
The illustrated slave transmission device 1n (n is a positive integer) is connected to outer and inner transmission lines 16 and 17, and transmits data signals in the counterclockwise and clockwise directions through these transmission lines 16 and 17, respectively. can do.

The illustrated slave transmission device 1n has a first
Input disconnection detection circuit 31, first overhead termination unit 3
2 and the first overhead insertion portion 33, which are both connected to the outer transmission line 16. The first input break detection circuit 31 detects a break in the clock sent from the upstream transmission device, and generates a break detection signal indicating break detection. On the other hand, the first overhead termination unit 3
2 extracts overhead from the outer transmission line 16 and generates an overhead signal. Further, the first overhead inserting unit 33 inserts the overhead into the data signal of the outer transmission line 16 and sends it to the downstream transmission device in the counterclockwise direction.

Further, the slave transmission device 1n has a second input disconnection detection circuit 36 and a second input disconnection detection circuit 36 which are connected to the inner loop transmission line 17.
Overhead termination section 37 and a second overhead insertion section 38 of the first input disconnection detection circuit 31, the first overhead termination section 32, and the first overhead termination section 32, respectively.
The same operation as that of the overhead insertion unit 33 is performed.

The interruption detection signal and the overhead signal are supplied to the first and second input interruption detection circuits 31, 36 and the first and second input interruption detection circuits 31, 36, respectively.
Is sent from the overhead termination units 32 and 37 to the overhead analysis control unit 40. The overhead analysis control unit 40 analyzes the interruption detection signal and the overhead signal and generates a control signal as indicated by a broken line.

In FIG. 3, the slave transmission device 1n is
The internal clock generator 41, the clock extraction circuit 42, the first selector 46 connected to both the internal clock generator 41 and the clock extraction circuit 42, and the second selector 47 connected to the outer and inner loop transmission lines 16 and 17. And have. Of these, the first and second selectors 46 and 4
7 is the first and second overhead insertion parts 33 and 38.
At the same time, it is controlled by the overhead analysis control unit 40.

Referring to FIG. 4, the master transmission device 10 receives data signals from the outer loop transmission line 16 and the inner loop transmission line 17, and also receives the data signals from the inner loop transmission line 17 and the outer loop transmission line 1.
6 is configured to send a data signal. The illustrated master transmission apparatus 10 is connected to a first master overhead termination unit 51 connected to the outer loop transmission line 16, a first master overhead insertion unit 52 connected to the inner loop transmission line 17, and a inner loop transmission line 17. A second master overhead terminating unit 53 and a second master overhead inserting unit 54 connected to the outer transmission line 16 are provided. The master overhead analysis control unit 55 analyzes the overhead signals detected by the first and second master overhead terminating units 51 and 52, and according to the result, the master overhead analysis control unit 55 controls the first and second master overhead inserting units 52 and 54 to perform master operation. Send a control signal.

The original clock CL from the master clock generator 28 is supplied to the master input disconnection detection circuit 57 and the clock receiving section 58. The master input disconnection detection circuit 57 monitors the original clock and, when the disconnection of the original clock is detected, generates an input disconnection detection signal. On the other hand, the clock receiving unit 58 changes the original clock CL to the intermediate clock C.
Generate Lm. The intermediate clock CLm from the clock receiving unit 58 is given to the selector 62 together with the internal clock CLi from the master clock generating circuit 61. The selector 62 sends the selected clock as a master clock to the outer loop transmission line 16 and the inner loop transmission line 17, and sends it to the inside of the master transmission device 10 as an in-device clock.

In this configuration, in the normal state, the intermediate clock CLm from the clock receiving section 58 is selected by the selector 62 and sent to the outer and inner transmission lines 16 and 17 as a master clock, while the original clock CLm is supplied.
Is detected, the internal clock CLi is set to the selector 6
It is selected in 2 and output as a master clock. The illustrated master overhead analysis control unit 55 has a function of controlling the first master overhead insertion unit 51, inserting the switching request signal SW into the overhead, and sending the switching request signal SW to the inner loop transmission line 17. ing.

The operation of the slave and master transmission devices 1n and 10 will be described with reference to FIGS. 5A and 5B together with FIGS. Slave transmission device 1n shown in FIG.
May operate as a failure detection source device and may operate as an intermediate transmission device for transferring a failure detection signal FD and the like. In this relation, in FIG. 5A and FIG. The operations of the detection source device, the intermediate transmission device, and the master transmission device will be described.

In a normal operation state, the fault detection source device monitors the master clock on the outer transmission line 16 by the first input break detection circuit 31. In this state, the second
Selector 47 selects the data signal O on the outer transmission line 16, and the first selector 46 selects the output N of the clock extraction circuit 42. As a result, the failure detection source device operates by extracting the master clock on the outer transmission line 16. When the failure detection source device detects the disconnection of the master clock on the outer loop transmission line 16, the overhead analysis control unit 40 sends a control signal to the first selector 46 and selects the output E of the internal clock generation circuit 41. So that the first selector 46 is switched. Therefore, the output E of the internal clock generating circuit 41 is transmitted as a clock on the downstream side of the outer transmission line 16. At this time, the overhead analysis control unit 40 sends a control signal to the first overhead insertion unit 33 to insert the fault detection signal FD into the overhead.

This fault detection signal FD is transmitted to the outer transmission line 16
Is sent to the intermediate transmission device, and the intermediate transmission device transfers the failure detection signal FD to the master transmission device 10.

In the master transmission device 10, when the first master overhead termination section 51 and the master overhead analysis control section 55 receive and detect the fault detection signal FD sent via the outer transmission line 16, the first The master overhead inserting unit 52 is controlled to insert the switching request signal SW into the overhead. This switching request signal S
W is sent to the intermediate transmission device via the inner transmission line 17.

The intermediate transmission device sends the switching request signal SW to the second signal.
Of the second selector 4 when detected by the overhead termination unit 27 and the overhead analysis control unit 40 (FIG. 3).
7 to the inner loop transmission line 17 side,
The signal I from is selected. As a result,
The clock extracting circuit 42 extracts a clock from the inner loop transmission line 17, sends the extracted clock to the inside as an in-apparatus clock via the first selector 46, and
It is also sent to the inner transmission line 17. At this time, the second overhead insertion unit 38 causes the overhead analysis control unit 4 to
Under the control of 0, the switching request signal SW is inserted in the overhead and transferred to the failure detection source device.

In the failure detection source device, when the second overhead termination unit 37 and the overhead analysis control unit 40 detect the switching request signal SW from the inner loop transmission line 17, the second selector 47 causes the inner loop transmission line 17 to operate. To the signal I side from the above, and the first selector 46 is switched to the output N side of the clock extraction circuit 42. Then, the first overhead insertion unit 31 transmits the switching completion signal SC to the outer loop transmission line 16 under the control of the overhead analysis control unit 40. The switching completion signal SC is sent to the intermediate transmission device via the outer transmission line 16 and transferred from the intermediate transmission device to the master transmission device.

Referring to FIG. 5 (B), in the failure detection source device, the first input disconnection detection circuit 31 and the overhead analysis control unit 40 detect reception of the master clock from the master transmission device, so that the failure is detected. Recovery is detected. Upon detection of the failure recovery, the second selector 47 is switched to select the signal O on the outer transmission line 16 side. Next, from the first overhead insertion unit 33,
The cutback request signal RR is sent out on the outer transmission line 16 and sent to the intermediate transmission device.

In the intermediate transmission device, the switchback request signal RR
When the second selector 47 receives the
After switching so that the signal O on the side is selected, the switchback request signal RR is transferred to the master transmission device 10.

The operations of the fault detection source device and the intermediate transmission device described above can be represented by the flow chart shown in FIG. 6, while the operation of the master transmission device can be represented by the flow chart shown in FIG. it can. The operation shown in the flowchart is the same as the above-mentioned operation, and therefore the description thereof is omitted here.

[0038]

According to the switching system of the present invention, the clock switching at the time of transmission line failure does not require manual labor, and the synchronous clock can be recovered automatically and at high speed, and the clock can be automatically recovered even when the failure is recovered. There is an effect that it is possible to switch back.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a procedure of clock switching control proposed by the present invention.

FIG. 2 is a diagram for explaining a switchback procedure when a failure is recovered in the present invention.

FIG. 3 is a block diagram for explaining a slave transmission device used in the switching system of the present invention.

FIG. 4 is a block diagram for explaining a master transmission device used in the switching system of the present invention.

5 is a time chart for explaining the operation of the transmission device of FIGS. 3 and 4. FIG.

6 is a flowchart for explaining an operation procedure of the slave transmission device of FIG.

7 is a flowchart for explaining an operation procedure of the master transmission device of FIG.

[Explanation of symbols]

 10 master transmission device, 11, 12, 13, 14, 15 slave transmission device 16 outer loop transmission line 17 inner loop transmission line 20 master clock generator 21 internal clock oscillator at the time of transmission line failure

Claims (3)

[Claims] 1. A master transmission device and a plurality of slave transmission devices are connected in a ring shape, and the plurality of slave transmission devices are synchronized with a clock from the master transmission device to perform both clockwise and counterclockwise directions. In the clock switching system used for the ring-shaped synchronous network capable of transmitting in the opposite direction, when one of the slave transmission devices detects a stop of the clock sent from the master transmission device in a predetermined direction, the one of the slave transmission devices is detected. While the slave transmission device transmits to the master transmission device the stop of the clock in the predetermined direction, the master transmission device transmits a switching request signal for instructing to switch the transmission direction to the opposite direction to the predetermined direction. Clock switching method characterized in that data is transmitted in the reverse direction to a slave transmission device that detects the stop of the clock. formula. 2. The clock switching system according to claim 2, wherein the transmission device that has detected the stop of the clock switches the clock to the clock extracted from the transmission path data when receiving the switching request signal, and completes the switching. A clock switching system characterized by sending a switching completion signal indicating to the master transmission device. 3. The clock switching system according to claim 1, wherein when the stop of the clock is restored, the transmission path is sequentially switched back from the slave transmission device in which the clock is stopped to the master transmission device. Characteristic clock switching system.