JPS61187047A - Logical circuit simulation system - Google Patents

Abstract

PURPOSE:To detect an improper presumption in an early stage to prevent unnecessary reverse simulation by inserting forward simulation to check the matching to the state of another output terminal in the process of reverse simulation if required. CONSTITUTION:When reverse simulation is started, input terminals of unit circuit are classified, and input terminals of unit circuits of wrong output signals are defined as F-state terminals. In case the input signal value estimated by reverse simulation is connected to the input terminal of another unit circuit different from that of forward simulation, the processing is performed as follows; in case that the value of forward simulation is correct with respect to the output of a unit circuit 10 though the output of a unit circuit 11 is not an output SBC of forward simulation but is an output SDC, the input terminal is held at a value B for forward simulation by check of the unit circuit 10 though it is estimated by reverse simulation of the unit circuit 11 that the input B is D.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is a simulation method for detecting design errors by simulating logical operations in a logic circuit in the design of a logic circuit constituting a so-called electronic device. Regarding the method.

In order to check whether the logic circuit is configured to perform the logical operation intended by the designer, the input signal value is set and the output signal value at the external output terminal of the logic circuit is determined by simulation. is compared with the expected output signal value.

If the simulation results differ from the expected values, it is necessary to search for the cause in order to modify the design.

As a method of such a search, the signal value on the input side is estimated sequentially from the output terminal where the expected output value was not obtained, and based on this estimation, it is determined whether there is a connection error in the logic circuit or the logic type of the unit circuit. So-called backward simulations are used to estimate or provide data for estimating the error of

In such backward simulation, the paths to be investigated are generally branched and expanded, which tends to result in a huge simulation.
From the viewpoint of practicality, it is desirable to eliminate wasteful simulations based on such estimates at an early stage.

[Prior art and problems to be solved by the invention] FIG. 2 is a block diagram of an example of the configuration of a logic circuit simulation system.

The processing device 1 executes a simulation program loaded into the main storage device 2 to simulate the load data from the auxiliary storage bag W3 to the main storage device 2, and the data resulting from the simulation is stored in the auxiliary storage device. 3 and is retained.

The configuration data of the logic circuit to be simulated, the input signal value data for the simulation, the scheduled output signal value data at the external output terminal, etc. are input in advance to the auxiliary storage device 3 and are held therein.

In the forward simulation, input signal value data is applied to the above logic circuit configuration data, and signal value data of intermediate signal lines is sequentially obtained to finally determine the output signal values of all external output terminals. The intermediate and final signal value data are held in the auxiliary storage device 3 or the like.

FIG. 3 is a diagram illustrating simulation data. For example, configuration data specifies that unit circuits 10 and 11 each consisting of an AND gate are connected as shown.

In the following description, reference will also be made to the process flow shown in FIG.

In the forward simulation of processing step 20, the signal values A,
When B and C are given, their output signal values are (&
AB) and (ABC) are obtained as simulation data.

If the output terminal of the illustrated circuit is connected to an external output terminal, the above (&AB) and (ABC) will be the final simulation results for this part, and will be compared with the planned signal value in the next processing step 21. The validity is determined.

As a result, for example, as an output signal of the unit circuit 11 (AB
If it is detected that the simulation output (ABC) is different from the above simulation output (ABC) due to the fact that C) is scheduled, so-called inverse simulation is executed for this portion from processing step 22 onwards.

In step 22, one of the external output terminals of the simulation output signal different from the expected signal is selected as the starting point for the backward simulation.

The inverse simulation in step 23 is performed, for example, between the planned output signal value (ABC) of the unit circuit 11 in question and the simile value.
The process proceeds by a method such as estimating that the input signal value B of one of the unit circuits 11 should be D by referring to the input signal values B and C at the time of the operation.

In this way, the desired input signal value or logic type of the unit circuit is estimated sequentially going back to the previous stage circuit, and if it reaches the stage where it matches the result of the Di direction simulation, Since the estimate can be considered quite overwhelming, step 2
4 and output the estimated value in step 25.

On the other hand, if the estimation result is under contradictory conditions, such as the estimated input signal value erroneously giving the input signal value given as a simulation manual, the estimation of this backward simulation will at least Since it cannot be adopted after a certain stage, it is checked in step 26, and if a contradictory condition is detected, in step 27,
Settings are made to start over from the previous stage of the backward simulation being processed, and the process returns to step 23.

If there is no contradiction, the process returns to step 23 to continue the simulation in the backward direction.

In this way, in conventional backward simulation, a contradiction is detected after starting from one output terminal where the expected signal value cannot be obtained and estimating the signal value sequentially in the direction of the input terminal. However, there is a problem in that wasteful backward simulations are often performed.

[Means for solving problems]

The problem described above is that when searching for errors in a logic circuit based on forward simulation results in which the signal value of the output terminal is determined based on the signal value of the input terminal of the logic circuit, all of the errors in the logic circuit are determined. Forward direction stain on the external output terminal of
Compare the error output signal value and the planned signal value,
Mark the input terminals of all unit circuits that are connected to external output terminals where both signal values do not match, and for the first unit circuit that has an external output terminal where both signals do not fail, change the input terminal from the external output terminal. , a backward simulation is performed to estimate the expected input signal value of the marked input terminal, and the estimated input signal value is different from the input signal value in the forward simulation, and the input terminal is the second input terminal. is connected to the input terminal of the unit circuit, and if the input terminal is not marked as above, the estimation is determined to be incorrect,
If the input terminal is marked above, replace the input signal of the input terminal with the planned input signal value, and replace the input signal of the input terminal with the planned input signal value.
By performing a forward simulation starting from the unit circuit of , obtaining the output signal value of the external output terminal connected to the second unit circuit, and comparing the output signal value with the planned output signal value, The problem is solved by the logic circuit simulation method of the present invention, which is configured to determine the correctness of the estimation.

[Effect]

That is, at the start of the backward simulation, the input terminals of the unit circuit are classified and the input terminal that inputs the incorrect output signal to the unit circuit is marked (hereinafter, the terminal marked in this way will be referred to as the terminal in the F state. On the other hand, terminals that are not in the F state are set as terminals in the T state.

This indicates that the signal values of the F-state terminals may be estimated by the backward simulation to a value different from the value in the forward simulation.

Input signal estimated by backward simulation (at a terminal where i is different from the value of forward simulation,
That terminal is connected to the input terminal of another unit circuit (
That is, if the same signal is input), the following processing is performed depending on the state of the other connected input terminal.

FIG. 5 is a diagram illustrating the contents of this process, and both fa) and bl in FIG. 5 are the same circuits as the circuit in FIG. 3.

In FIG. 5(a), the output of the unit circuit 11 is not the forward simulation output (ABC) but (&DC) (this is expressed as CF, (&DC)), but the output of the unit circuit 10 is is the case where the value of the forward simulation is correct (this is represented by [T)].

If it is estimated that the input of B shown in the figure is D by the backward similiation of the unit circuit 11, then since this input terminal is connected to the unit circuit 10, the state of that terminal is checked.

Since that input terminal is in the T state, the input signal of this terminal should be maintained at the value at the time of forward simulation (i.e., B), and the signal value of the input terminal connected to it should be changed to D.
Is the above estimation incorrect or the hundred unit circuit 10.11
Since it should be inferred that the fact that the input terminal of is connected is an error, it is wasteful to continue the backward simulation to the previous stage at least.

FIG. 5 (bl is a CF
, (&DC)), the unit circuit 10 is also CF, (&toD)
), and therefore the input terminal of the unit circuit 10 is also classified into the F state.

In this case, apply the signal value estimated by the backward simulation of the unit circuit 11 to the unit circuit 10, perform a forward simulation of the unit circuit 10, and compare the output signal value with the planned value (&AD). This confirms the validity of the estimated value.

In this example, the conclusion is that the estimated value is appropriate, so the backward simulation may be performed in the previous stage.

In this way, by checking the consistency with the states of other output terminals during the backward simulation process by inserting forward simulations if necessary, unreasonable estimates can be detected early. , it is possible to prevent unnecessary backward simulation.

〔Example〕

FIG. 1 is a process flowchart showing the configuration of an embodiment of the present invention.

As in the prior art, forward simulation is performed in step 20 of the process, and detection of an external output terminal with an incorrect output signal value is performed in step 21.

In the next step 30, the detected in step 20,
The input terminal of a unit circuit having an external output terminal with an incorrect output signal value and other input terminals are classified, and the former are marked as F-state terminals, and the others are marked as T-state terminals.

One of the external output terminals to be subjected to backward simulation is selected in step 22, and the signal value of the input terminal of the related F state is estimated by the backward simulation in step 32.

In step 33, it is checked whether the terminal for which the new signal value has been estimated is connected to an input terminal of another unit circuit. If there is no connection, the process proceeds to step 24 and subsequent steps, and processing is performed in the same manner as in the conventional method.

If there is a connection with another unit circuit, in step 34, the classification of the terminal of the other circuit to be connected is checked.

If the terminal is in the T state, as described above, there is no need to continue this backward simulation, and the process proceeds to step 27, which is a redo process.

If the terminal is in the F state, forward simulation is performed in step 35 to check the consistency of the estimated signal value with respect to the other unit circuit, as described above.

If the simulation result matches the expected output signal value as determined in step 36, the process proceeds to step 24 to proceed with the backward simulation.

If it does not match the planned output signal value, there is no point in proceeding with the backward simulation using this estimated value, and the process proceeds to step 27 for redoing.

〔Effect of the invention〕

As is clear from the above description, the present invention has a significant industrial effect of improving simulation efficiency in debugging logic circuit design by simulation.

[Brief explanation of drawings]

Fig. 1 is a flowchart of processing in an embodiment of the present invention, Fig. 2 is a block diagram of an example of a configuration of a simulation system, Fig. 3 is an explanatory diagram of simulation data, and Fig. 4 is a flowchart of processing in an example of a conventional configuration. , FIG. 5 is an explanatory diagram of the processing contents. In the figure, 1 is the processing device 2, the main memory, 3 is the auxiliary memory, 10.11 is the unit circuit, γ (Fig.

Claims (1)

[Claims] When searching for an error in a logic circuit based on the forward simulation result, which determines the signal value of the output terminal based on the signal value of the input terminal of the logic circuit, the order of all external output terminals of the logic circuit is determined. Compare the direction simulation output signal value and the planned signal value, mark the input terminals of all unit circuits connected to external output terminals with which both signal values do not match, and mark the input terminals of all unit circuits that have external output terminals with which both signals do not match. For the first unit circuit, a backward simulation is performed from the external output terminal to the input terminal to estimate the expected input signal value of the marked input terminal, and the estimated input signal value is Unlike the input signal value in the direction simulation, if the input terminal is connected to the input terminal of the second unit circuit and the input terminal is not marked above, the estimation is determined to be incorrect, and the input terminal is If it is marked above, replace the input signal of the input terminal with the planned input signal value, perform a forward simulation starting from the second unit circuit, and then perform a forward simulation starting from the second unit circuit. A logic circuit characterized in that the logic circuit is configured to determine the validity of the above estimation by determining an output signal value of an external output terminal connected to the above and comparing the output signal value with the above scheduled output signal value. Simulation method.