JP3092599B2 - Fault simulation method and fault simulation device for logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit fault simulation method and a fault simulation for calculating a fault coverage of a test pattern for a logic circuit.
Related to the device .

[0002]

2. Description of the Related Art Conventionally, circuit data and a test pattern of a logic circuit stored in an input file are input to a computer, and a fault is assumed from the circuit data. A test pattern is evaluated by calculating a failure detection rate of the test pattern.

FIG. 6 is a flowchart showing an example of a conventional fault simulation method for a logic circuit of this type.
First, circuit data of a logic circuit stored in an input file is input (step 201 in FIG. 6), and a failure is assumed from this circuit data (202). Further, a test pattern is input from the input file (203).

Next, a full delay fault simulation is performed (204). The full delay fault simulation is a method of calculating a response output to a test pattern of a logic circuit in which a fault is assumed (hereinafter referred to as a faulty circuit) in consideration of a delay time for each gate and wiring constituting the logic circuit. This is a simulation that can obtain a high failure detection rate.
As a result, if the assumed fault is detected, the fault is deleted (205) and the test pattern is terminated (20) until the test pattern ends.
6), the procedure after the input of the test pattern (203) is repeated. Steps 203 to 2 for all test patterns
When the processing up to 05 is completed (206), the failure detection rate of such a test pattern group is calculated (207).

[0005] It should be noted that, depending on the configuration of the logic circuit and the contents of the test pattern, there are cases in which a unit delay fault simulation can be satisfactorily performed, and cases in which a fault becomes apparent without considering delay time. It is not the subject of the invention. Here, the unit delay fault simulation is based on a full delay fault simulation in which the delay times of all gates and wirings constituting a logic circuit are uniformly estimated and a response output to a test pattern of a logic circuit in which a fault is assumed is obtained. This is a rough simulation.

[0006]

However, in the above-described conventional fault simulation method for a logic circuit, there are many cases where a full delay fault simulation is performed for a logic circuit for which a unit delay fault simulation is sufficient. The full delay fault simulation requires a much longer simulation time than the unit delay fault simulation. Therefore, in the case of a logic circuit having no problem even in the unit delay fault simulation, useless operations are performed.

Here, referring to the following table, this table shows that 9
The fault coverage F. based on full delay fault simulation for C. (1) and the fault coverage F. based on the unit delay simulation. C. (2), F.R.
C. (1) and F. C. The error of (2) and the measured value of the mismatch between the expected value and the measured value are shown in percentage.

[0008]

[Table 1]

As is clear from this table, for the circuits 1 to 4 and the circuit 9, the discrepancy between the expected value and the actually measured value is determined by F.C.
C. (1) and F. C. There is no error of (2). Although there is no mismatch between the circuits 6 to 8, C. (1) and F. C.
Although there is the error of (2), it is small. Therefore, it is understood that these eight circuits are sufficient for the unit delay simulation. As a result, only the circuit 5 in which the mismatch of 29.40% is recognized has an error of 16.50%, which indicates that the full delay fault simulation is necessary.

Accordingly, it is an object of the present invention to determine whether a logic circuit, such as a sequential circuit, requires a full delay fault simulation, or whether there is no problem in a unit fault delay simulation. by selectively using the delay fault simulation appropriately, while keeping small the decrease of the fault coverage, fault simulation method and therefore efficient logic circuits shortened simulation time
An object of the present invention is to provide a failure simulation device .

[0011]

A first method of simulating a fault in a logic circuit according to the present invention is a method of simulating a fault in a logic circuit for calculating a fault detection rate of a test pattern for the logic circuit. On the other hand, a unit delay simulation for obtaining a response output to the test pattern by uniformly estimating delay times of all gates and wirings is performed, but the unit delay for the logic circuit (hereinafter, referred to as a positive circuit) which does not assume a failure is performed. The result of the simulation (hereinafter, referred to as an actually measured value) and the result of a full delay simulation (hereinafter, referred to as an expected value) for obtaining a response output to the test pattern with respect to the positive circuit in consideration of the delay time of each gate and wiring. Based on the comparison result, the full delay simulation And wherein the switching to perform the emissions.

Further, a second method of simulating a fault in a logic circuit according to the present invention is a method of simulating a fault in a logic circuit for calculating a fault detection rate of a test pattern for the logic circuit. A procedure of storing a result (expected value) of a full delay simulation for obtaining a response output to the test pattern in consideration of a delay time of each circuit, a procedure of inputting circuit data of the logic circuit, and assuming a fault from the circuit data. And a step of inputting the test pattern, and a step of executing a unit delay simulation for uniformly estimating delay times of all gates and wirings for the circuit data and obtaining an output of the logic circuit for the test pattern. Comparing the measured value with the expected value, and based on the result, Switching the execution of the delay simulation to the full delay simulation, and detecting the assumed fault by executing the unit delay simulation or the full delay simulation, deleting the fault and performing the procedure from the test pattern input to the entire test pattern. And a procedure for repeating the above.

Further, in a preferred embodiment of the fault simulation method for a logic circuit according to the present invention, in the unit delay simulation, a specified test pattern and a simulation state are held for each execution and the switching is performed for the switching. After returning to the previously held simulation state, the full delay simulation is executed from there, and when the simulation is executed a specified number of times, the process returns to the unit delay simulation.

Further, in a preferred embodiment of the fault simulation method for a logic circuit according to the present invention, the switching is performed when the number of times the actual measurement value does not match the expected value exceeds a predetermined number. Switching or returning is performed by turning off or on the unit flag.

Further, in a preferred embodiment of the method for simulating a fault in a logic circuit according to the present invention, the unit delay simulation includes simulating the faulty circuit only when the operation of the faulty circuit is different from the operation of the positive circuit. And a simultaneous failure simulation method (concurrent method) performed simultaneously with the simulation.

Further, a fault simulation of a logic circuit according to the present invention is provided.
Deployment device, fault simulation of the logic circuit for calculating the fault coverage of the test pattern for the logic circuit
In the apparatus , a circuit data input circuit that inputs circuit data of the logic circuit, a failure assumption circuit that assumes a failure from the circuit data, a test pattern input circuit that inputs the test pattern, and all of the circuit data A unit delay simulator for uniformly estimating a delay time of a gate and a wiring and obtaining a response output to the test pattern of the logic circuit; and a test of the logic circuit for the circuit data in consideration of a delay time for each gate and wiring. A full delay simulator for obtaining an output for a pattern, and the logic circuit (positive circuit) that does not assume a fault
Of the unit delay simulator for
Measured value) and the execution result of the full delay simulator (expected
Value), and a flag indicating whether the unit delay simulator or the full delay simulator is to be operated by ON / OFF, and the flag is initially set to ON. , When the value of the counter exceeds a predetermined threshold value.

The present invention provides a response output (expected value) of a positive circuit based on a full delay simulation (full delay logic simulation) for a positive circuit and a response output (expected value) of a positive circuit based on a unit delay simulation (unit delay logic simulation) for the positive circuit. If there is no inconsistency with the measured value, the error between the fault detection rate of the full delay simulation for the faulty circuit (full delay fault simulation) and the fault detection rate of the unit delay simulation for the faulty circuit (unit delay fault simulation) is very small. The focus was on the fact that
A unit delay simulation was performed, and when the difference between the expected value and the measured value exceeded a predetermined threshold value, the process was shifted to a full delay simulation, thereby realizing an efficient logic circuit failure simulation.

The full (unit) delay logic simulation and the full (unit) delay fault simulation are collectively referred to as a full (unit) delay simulation.

[0019]

Next, an embodiment of the present invention will be described.

FIG. 2 is a fault simulation of a logic circuit according to the present invention.
FIG. 1 is a block diagram of an application device , and a circuit data input circuit 1 for inputting circuit data of a logic circuit from an input file.
And a failure assumption circuit 2 for assuming a failure from this circuit data
A test pattern input circuit 3 for inputting a test pattern from an input file, a unit delay simulator 4 for uniformly estimating delay times of all gates and wirings for circuit data and obtaining a response output to a test pattern of a logic circuit, For circuit data, a full delay simulator 5 for obtaining a response output to a test pattern of a logic circuit in consideration of a delay time for each gate and wiring, and a counter 6 for counting the number of times of mismatch between an actual measurement value and an expected value
Calculate the fault detection rate of the logic circuit from the flag 7 indicating on / off which of the unit delay simulator 4 and the full delay simulator 5 is to be operated, and the result of the simulation by the unit delay simulator 4 and the full delay simulator 5 And a control circuit 9.

The outline of the operation of the fault simulation device for a logic circuit is as follows. The input file stores the circuit data and the test pattern of the logic circuit for which the fault coverage is calculated. The circuit data input circuit 1 inputs circuit data from an input file under the control of the control circuit 9, and the failure assumption circuit 2 assumes a failure from the circuit data. Further, the test pattern input circuit 3 inputs a test pattern from an input file. These circuit data, the assumed fault and the test pattern are input to the unit delay simulator 4 or the full delay simulator 5. The distribution is performed by the control circuit 9 by observing the contents of the flag 7. At first, the flag 7 is on and the unit delay simulator 4 is started.

The unit delay simulator 4 performs a unit delay logic simulation and a unit delay fault simulation by a simultaneous fault simulation method (concurrent method). The simultaneous failure simulation method is described in, for example, "Configuration and Design of Fault-Tolerant System", co-authored by Yoshihiro Toma et al. 203-P. 206
In general, paying attention to the property that a normal circuit and a faulty circuit perform almost the same operation for the same input sequence as described in the above, only when the operation of the faulty circuit is different from the operation of the normal circuit This is a simulation method in which the simulation of the failed circuit is performed simultaneously with the simulation of the normal circuit. On the other hand, the full delay simulator 5
When the flag 7 is turned off, a full delay fault simulation is performed.

The measured value obtained by the unit delay logic simulation by the unit delay simulator 4 is compared with an expected value for each test pattern in the control circuit 9, and when there is a mismatch, the counter 6 counts the number of times. When the count value of the counter 6 exceeds a predetermined threshold, the control circuit 9 turns off the flag 7 and activates the full delay simulator 5. When the simulation for all the test patterns is completed, the failure detection rate calculation circuit 8 calculates the failure detection rate of the test pattern for the logic circuit and outputs it to the output file.

According to the present invention, a unit delay simulation is executed based on such an actual measurement result as long as the number of occurrences of mismatch between the expected value and the actual measurement value is within a predetermined threshold value. When the threshold value is exceeded, a switch is made to execute a full delay simulation.

Next, referring to the flowchart,
A fault simulation method for a logic circuit according to the present invention will be described.

FIG. 1 is a flow chart showing a first embodiment of a method for simulating a fault in a logic circuit according to the present invention. First, the circuit data input circuit 1 inputs circuit data from an input file (Step 100 in FIG. 1). The control circuit 9 turns on the flag (101), and the failure assumption circuit 2
Assumes a failure (102). Assuming that a failure occurs, for example, in the logic circuit example shown in FIG.
When the test pattern to be input to the ₁ and A ₂ are "00", but the AND of the output "1" gates A ₁ refers to such things.

Next, the test pattern input circuit 3 inputs a test pattern from an input file (103). at first,
Since the flag is ON (101, 104), the unit delay simulator 4 is started (105). In the early stages of this simulation,
In order to understand the general feeling, it is a measure to allow minor inconsistencies to be tolerated.

Unit delay simulation (105)
Performs the response output of the logic circuit to the test pattern under the assumed fault for the above-described circuit data by the above-described simultaneous fault simulation method. Then, the control circuit 9 checks whether or not the measured value simulated by the positive circuit matches the expected value, and counts up the counter 6 when a mismatch occurs (107). As a result, if the count value does not exceed the predetermined threshold value, in step 108, if a failure is detected, the failure is deleted, and the process returns to the test pattern input in step 103 until the pattern ends (109). , Steps 103 to 108 are repeated.

In step 107, the count value is
If the threshold value is exceeded, the control circuit 9 turns off the flag 7 (107), and returns to step 104 via steps 108 and 109. In step 104, since the flag is not turned on, the full delay simulator 5 is activated, and a full delay fault simulation is executed (106). In this case as well, after step 106, the process moves to steps 107 and 108.

In step 109, when the end of the simulation is detected for all the test patterns, the fault coverage calculating circuit 8 calculates the fault coverage from the results of the unit delay simulation and the full delay fault simulation (111), and outputs the result. Output to file.

FIG. 3 is a flowchart showing a second embodiment of the method for simulating a fault in a logic circuit according to the present invention. FIG. 3 is different from the first embodiment shown in FIG. And a step 120 of turning on the flag when the full delay fault simulation is repeated a specified number of times.

This focuses on the locality that there is a test pattern group in which a mismatch with an expected value exists unless the simulation is a full delay fault simulation due to the characteristics of the test pattern. ,
That is, the number is equal to the number of test patterns included in the test pattern group. That is, when the flag is turned on in step 120, the unit delay simulation is performed again (104, 105). At this time, since the test pattern group has already been passed, inconsistency with the expected value occurs. The goal is to have the unit delay simulation re-challenge.

In the first embodiment shown in FIG. 1, once the process has shifted to the full delay fault simulation, the process never returns to the unit delay simulation, whereas the second embodiment returns to the unit delay simulation. The feature is that higher-speed simulation can be expected. However, of course, the error will be larger than in the first embodiment.

After returning to the unit delay simulation, the process may shift to the full delay fault simulation again (107).

FIG. 4 is a flowchart showing a third embodiment of the method for simulating a fault in a logic circuit according to the present invention. FIG. 4 is different from the first embodiment shown in FIG. 1 after a unit delay simulation (105). , A count of mismatch with the expected value is performed, and if the count value exceeds the threshold value, the flag is turned off. In addition, the simulation state is returned to the previous simulation state (130). Is added to the step of holding the simulation state (140).

Steps 130 and 140 actually function substantially before step 140. This is because steps 130 and 140 are processes performed when the flag 7 is on. Step 140
In (2), when the unit delay simulation is executed (105), the simulation state at that time, that is, signals at key points, etc. are stored in the memory for each specified test pattern. In step 130, when the flag is turned off, a full delay fault simulation is performed from the simulation state held last time (1).
06).

This is because near the test pattern where the count value of the mismatch of the expected value exceeds the threshold value, the discrepancy is likely to occur frequently since the discrepancy is likely to occur at the entrance of the above-described test pattern group. Then, by performing the full delay fault simulation (106), the accuracy is improved with the aim of performing a more careful simulation at the expense of some simulation speed.

FIG. 5 is a flowchart of a fourth embodiment of the logic circuit fault simulation method according to the present invention to which the ideas of the second and third embodiments are applied simultaneously. That is, as in the third embodiment shown in FIG. 4, if the flag 7 is on, the simulation state is held for each designated test pattern (140), and if the measured value exceeds the expected value, the flag 7 is turned off. To return to the previous simulation state (130), the full delay fault simulation is performed (106). However, when the full delay fault simulation is performed a specified number of times, the flag is turned on (120), and the process returns to the unit delay simulation. (104, 105).

A program for causing a computer to execute the above-described method for simulating a failure of all logic circuits is recorded on a recording medium such as a magnetic disk or a semiconductor memory, and read and executed by the computer. Is also good. Such a method is a fault simulation method of a logic circuit for calculating a fault detection rate of a test pattern for the logic circuit. Storing a result (expected value) of a full delay simulation for obtaining a response output with respect to, a step of inputting circuit data of the logic circuit, a step of assuming a failure from the circuit data, and a step of inputting the test pattern And a procedure for executing a unit delay simulation for uniformly estimating delay times of all gates and wirings for the circuit data and obtaining a response output to the test pattern of the logic circuit, and comparing an actual measurement value with the expected value. And executing the unit delay simulation according to the result. Having a step of switching to Deployment, and procedures repeating the unit delay simulation or the full delay simulation the assumed fault to delete detects the failure of less than the test pattern input procedure by the execution of the entire test pattern.

[0040]

According to the present invention, if the expected value mismatch of the positive circuit does not occur in the unit delay simulation, the logic circuit is determined to be a circuit having no problem even if the unit delay fault simulation is performed. For this circuit, we performed a unit delay fault simulation faster than the full delay fault simulation,
Since the configuration is switched to the full delay fault simulation when the number of occurrences exceeds the threshold, the simulation can be speeded up without lowering the fault detection rate of the logic circuit.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a first embodiment of a logic circuit failure simulation method according to the present invention .

FIG. 2 is a block diagram showing a logic circuit failure simulation apparatus according to the present invention .

FIG. 3 is a flowchart showing a second embodiment of the logic circuit failure simulation method according to the present invention .

FIG. 4 is a flowchart showing a third embodiment of the logic circuit failure simulation method according to the present invention .

FIG. 5 is a flowchart showing a fourth embodiment of the logic circuit fault simulation method according to the present invention .

FIG. 6 is a flowchart showing an example of a conventional logic circuit failure simulation method .

[Explanation of symbols]

 1 Circuit Data Input Circuit 2 Fault Assumption Circuit 3 Test Pattern Input Circuit 4 Unit Delay Simulator 5 Full Delay Fault Simulator 6 Counter 7 Flag 8 Fault Detection Rate Calculation Circuit 9 Control Circuit

Claims (10)

(57) [Claims] 1. A fault simulation method for a logic circuit for calculating a fault detection rate of a test pattern for a logic circuit, comprising: A unit delay simulation for obtaining a response output to the test pattern by uniformly estimating the delay time is performed. The result (actually measured value) of the unit delay simulation for the logic circuit (positive circuit) that does not assume a failure and On the other hand, the full delay simulation is performed on the faulty circuit based on a result of comparison with a result (expected value) of a full delay simulation for obtaining a response output to the test pattern in consideration of a delay time for each gate and wiring. Simulation of logic circuit characterized by switching as follows Option. 2. A method for simulating a fault in a logic circuit for calculating a fault detection rate of a test pattern for the logic circuit, comprising the steps of: A procedure for storing a result (expected value) of a full delay simulation for obtaining a response output with respect to the test pattern in consideration of, a procedure for inputting circuit data of the logic circuit, a procedure for assuming a failure from the circuit data, Steps for entering a test pattern,
A procedure for uniformly estimating delay times of all gates and wirings for the circuit data and executing a unit delay simulation for obtaining an output for the test pattern of the logic circuit, and a result of the unit delay simulation for the positive circuit (actual measurement) Value) and the expected value, and switching the execution of the unit delay simulation to the full delay simulation based on the result, and detecting the assumed failure by executing the unit delay simulation or the full delay simulation. A step of deleting a fault and repeating the steps following the test pattern input for all test patterns. 3. The fault simulation method for a logic circuit according to claim 1, wherein when the full delay simulation is performed a specified number of times, the unit delay simulation is restored. 4. The fault simulation of a logic circuit according to claim 1, wherein a simulation state is held for each specified test pattern during said unit delay simulation, and said simulation state is returned to a previously held simulation state at said switching. Method. 5. In the unit delay simulation, the simulation state is held for each specified test pattern and each time the simulation is executed, and the simulation state held last time is returned at the time of the switching, and the full delay simulation is executed from there. 3. The fault simulation method for a logic circuit according to claim 1, wherein the logic circuit returns to the unit delay simulation when the logic circuit is executed and executed a specified number of times. 6. The fault simulation method for a logic circuit according to claim 1, wherein the switching is performed when the number of times the actual value does not match the expected value exceeds a predetermined number. 7. The fault simulation method for a logic circuit according to claim 1, wherein said switching or returning is performed by turning off or on a unit flag. 8. The simultaneous delay simulation method (concurrent method) in which the simulation of the faulty circuit is performed simultaneously with the simulation of the positive circuit only when the operation of the faulty circuit differs from the operation of the positive circuit. 8. The method for simulating a fault in a logic circuit according to claim 1, wherein: 9. A fault simulation method for a logic circuit for calculating a fault detection rate of a test pattern for the logic circuit, wherein a delay for each gate and wiring is provided for the logic circuit (positive circuit) which does not assume a fault. A procedure for storing a result (expected value) of a full delay simulation for obtaining a response output to the test pattern in consideration of time, a procedure for inputting circuit data of the logic circuit, and a procedure for assuming a fault from the circuit data. Inputting the test pattern,
A procedure for uniformly estimating delay times of all gates and wirings for the circuit data and executing a unit delay simulation for obtaining a response output to the test pattern of the logic circuit, and a result of the unit delay simulation for the positive circuit ( Comparing the actual measured value) with the expected value, switching the execution of the unit delay simulation to the full delay simulation based on the result, and detecting the assumed failure by executing the unit delay simulation or the full delay simulation. A computer-readable recording medium storing a program for causing a computer to execute a method including the steps of deleting the fault and repeating the steps following the input of the test pattern for all test patterns. 10. A fault simulation of a logic circuit for calculating a fault detection rate of a test pattern for the logic circuit.
In the apparatus , a circuit data input circuit that inputs circuit data of the logic circuit, a failure assumption circuit that assumes a failure from the circuit data, a test pattern input circuit that inputs the test pattern, and all of the circuit data A unit delay simulator for uniformly estimating a delay time of a gate and a wiring and obtaining a response output to the test pattern of the logic circuit; and a test of the logic circuit for the circuit data in consideration of a delay time for each gate and wiring. A full delay simulator that calculates the output for the pattern,
A counter for counting the number of times the execution result (measured value) of the unit delay simulator and the execution result (expected value) of the full delay simulator do not match the logic circuit (positive circuit) that does not assume a failure; And a flag that indicates which of the full delay simulator is to be operated by on / off, respectively.
A fault simulation device for a logic circuit, wherein the flag is turned on, and is turned off when the value of the counter exceeds a predetermined threshold value.