JPH0727834A - Method for automatically generating test vector - Google Patents

Abstract

PURPOSE:To automatically generate a test vector which can test a circuit containing an FF having no scan-path constitution by calculating such a probability that the logical value of input signals becomes '1' by regarding the FF as a one-input, one-output buffer. CONSTITUTION:Upon receiving a logical network list, processing is started. The probability that the logical value of input signals becomes '1' at which a cost function becomes the minimum is calculated and the probability is used as the weight of a random number. Then, a test vector following the weighed random number is generated. By performing fault simulation, the test vector is inputted to a virtual logic circuit on a computer and simulated fault detection is performed to calculate a fault detecting rate. When the fault detecting rate does not reach a target value, another test vector is additionally prepared to detect the faults which could not be detected by the previously prepared test vector and similar processing is repeated. After the fault detecting rate reaches the target value, the test vector preparing process is completed by eliminating the test vector which did not contribute to the improvement of the fault detecting rate from the prepared test vectors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of creating a test vector for detecting stuck-at faults of a logic circuit in an ASIC logic circuit design support device. The stuck-at fault is a fault whose logic value is fixed at 0 or 1, and accounts for the majority of ASIC faults.

[0002]

2. Description of the Related Art In the logic design of an ASIC, a logic circuit of the ASIC having a desired function is designed, a net list is output as manufacturing information of the ASIC, and a test vector is output as inspection information. Generally, the design is ASIC
This is performed with the support of a CAD system in a broad sense called a logic circuit design support device. The automatic test vector generation of the present invention is one component of the ASIC logic circuit support device. As the function of the ASIC becomes higher, the circuit becomes larger and more complicated. As a result, the test becomes complicated, and it takes a lot of time to write the test program, and the test time tends to be long. Generally, there are two types of tests: a design evaluation test that tests whether the design is as intended and a mass production test that tests whether each manufactured IC is normal. The present invention relates to the latter.
Since the manufactured ASIC cannot hit the inside of the IC with the probe pin, it is necessary to detect the internal failure of the IC from the output signal appearing at the other external terminal in response to the input signal applied to the external terminal of the IC. . That is, the measured value of the response of the output to the input signal is compared with the normal value to judge the pass / fail.
This input signal is called a test vector or test pattern. The test must efficiently detect pass / fail for all nodes in the IC. For that purpose, it is important to create test vectors with high fault coverage. In addition, with the increasing complexity, it is essential to automatically create test vectors.

The logic circuit can be classified into a combinational circuit whose output is uniquely determined with respect to an input, and a sequential circuit whose output is determined by a function of past states and inputs. A method of automatically creating a test of a combinational circuit using a D algorithm or a random number is general. On the other hand, in a sequential circuit represented by a flip-flop circuit, it is difficult to directly apply the D algorithm because the output depends on the history of past inputs. Therefore, in the related art, in order to enable the setting of the initial value of the flip-flop and the reading of the output result, the scan path configuration is designed in the design stage, and the test vector is created using the D algorithm. .
The scan path configuration is a method in which the flip-flop is configured as a single shift register in the test mode, and is directly observed and controlled from an external terminal. Since a circuit for that purpose is added, the circuit scale increases and the cost increases. For this reason, it is difficult to use the scan path configuration in a circuit or the like that frequently uses flip-flops such as a data path circuit, and a method for effectively and economically testing an ASIC that is not the scan path configuration is desired. It was

For combinational circuits, the D algorithm can theoretically produce complete test vectors, but the ASI
When the scale of C becomes large, it is difficult to follow all the logic and obtain a complete solution. Moreover, it is not impossible to apply to a circuit including a flip-flop, but it is difficult to apply to a large-scale circuit with a complicated algorithm. As a method of creating a test vector for a combinational circuit using random numbers, see Robert Lisanke, Franc Brglez, Aart J. Dgeus, D.
avid Gregory: "Testability-Driven Random Test-Pat
tern Generation ", IEEE Transactions on Computer-A
ided Design, Vol CAD-6, No 6, pp1082-1087 (Nov. 198
7) has been published. In this paper, the probability that the input signal becomes 1 is calculated so as to maximize the failure detection rate of the combinational circuit, and the test vector is created by the weighted random number corresponding to this probability. However, this paper assumes that the part of the flip-flop uses the scan path method.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, and it is an object of the present invention to automatically create a test vector that enables testing of a circuit including a flip-flop which is not a scan path configuration.

[0006]

SUMMARY OF THE INVENTION It has been impossible to test flip-flops by a conventional test vector automatic generation method using random numbers. The present invention is a test vector automatic generation method using random numbers, which is improved from the drawbacks of the prior art, and includes the following steps. The probability that the input signal of the IC that maximizes the fault coverage is the logical value 1 is calculated, a test vector in which the probability is weighted by a random number is generated, and the fault coverage of the test vector is calculated by fault simulation. Calculate,
If the fault coverage does not reach the target, recalculate weights for undetected faults and add test vectors, and test until the fault coverage reaches the target value or the number of test vectors exceeds the limit value. -It is composed of each step of repeating the process of adding a vector and thinning out the test vector that does not contribute to the improvement of the fault coverage after the fault coverage has reached the target. According to the present invention, in the step of calculating the probability that the input of the IC that maximizes the failure detection rate becomes the logical value 1, the flip-flop is regarded as a buffer having one input and one output, and the probability is calculated by the method of calculating the probability. Enables automatic test vector creation.

[0007]

1 is a diagram showing an embodiment of the present invention. The figure is a flow chart showing the process of automatic test vector creation in the ASIC logic circuit design support device. However, the flow chart is the same as the conventional test vector generation method using random numbers. The present invention is shown in step 3 of the figure.
Regarding the calculation of random weights of. 1 is an operation start step for automatically creating a test vector, 2 is a recalculation of random weight calculation, a determination step is not performed, 3 is a random weight calculation step, 4 is a test vector generation step, 5 is a failure simulation step, 6 is a step of judging whether or not the failure detection rate has reached a target value, or whether or not the number of vectors has reached a limit value, 7 is a step of deleting unnecessary vectors, 8
Is the completion step of the test vector automatic creation processing.

The automatic test vector generation receives a logical netlist as input information and starts processing. Reference numeral 2 is a step provided to save processing time, and the determination of the first processing is Yes. In step 3, the probability that the logical value of the input signal will be 1 is calculated so as to minimize the cost function described later, and this probability is used as the weight of the random number, and step 4
Pass to. In step 4, a test vector according to the weighted random number is created. For example, the probability that the input will be 1 is 70%
If the cost function is minimized when, the probability that 1 is selected as the test vector in step 4 is 70%, and the probability that it is 0 is 30%. In the fault simulation of step 5, the test vector is input to a virtual logic circuit on the computer, faults are simulated and fault detection rates are calculated. In step 6, it is determined whether the fault coverage has reached the target or the number of vectors has reached the limit value. If No, the process returns to step 2 to enter the process of newly creating a test vector for detecting a fault that was not found in the test vectors created so far. The same process as described above is performed, and the process of adding test vectors is repeated until it is determined in step 6 whether the failure detection rate satisfies the target value or the number of test vectors exceeds the target value. If Step 6 is Yes, Step 7
Then, the test vector that did not contribute to the improvement of the fault coverage is thinned out to complete the test vector, and the entire creation process is completed. Step 2 is provided to reduce the processing time. As will be described later with reference to FIG. 2, at the initial stage of test vector creation, that is, when the number of test vectors is small,
The addition of test vectors greatly improves the fault coverage. Therefore, when the number of test vectors is small, the recalculation of weights is omitted to reduce the processing time.

The present invention relates to the calculation of weights in step 3 of the process. As a method of using a random number, the method according to the paper by R. Lisanke et al. Is widely used. A conventional method will be described below, and then an embodiment of the present invention will be described. Where i
Find the probability of failure detection for the th net. First, Ci is defined as the controllability of the i-th net, and Oi is defined as the observability of the i-th net. The controllability is the probability that the net is 1, and the observability is the probability that the logical value of the net can be observed at the outermost output. Therefore, the probability of failure detection to be obtained is as follows.

[0010]

[Equation 1]

The 0 stuck-at fault and the 1 stuck-at fault are faults whose logic values are fixed at 0 and 1, respectively. The probability of failure detection gives the probability CPd _j that failure j will be detected when n independent test vectors are input.

[0012]

[Equation 2]

Next, assuming that the number of all failures is M, the average value of the probability of failure detection is

[0014]

[Equation 3]

[0015] FIG. 2 shows a curve of average values of failure detection probabilities. Intuitively, as the number of test vectors increases, the probability of failure detection increases. Further, when the number of test vectors is small, the increase in the probability of failure detection is large, and when the number of test vectors is large, the increase is small. Further, the vertical stripe portion in FIG. 2 is a portion where the failure is not detected. The cost function is defined as the integrated value of the part where this failure is not detected. Therefore, the cost function is expressed as follows.

[0016]

[Equation 4]

The controllability of the outermost input that minimizes this cost function is calculated. In other words, IC
Find the probability that maximizes the fault coverage in the probability distribution where the external input of is a logical value 1. A test vector may be created by using the probability as a weight of the random number. The minimum value of the cost function is obtained by the gradient method. That is, the gradient vector is calculated by the following formula.

[0018]

[Equation 5]

When equation (5) is calculated, it is determined that the gradient is not yet the minimum when there is a gradient, the gradient vector is moved again, the gradient vector is obtained again, the gradient vector is continued until the gradient disappears, and the gradient is determined to be the minimum. . In equation (5), dO _j / dC _i , dC
_k / dC _i and dO _i / dO _k have unique values depending on the type of each logic gate. In the prior art, this method was not applied to flip-flops. In the present invention, the flip-flop has one input by utilizing the fact that the feedback circuit is relatively small in the logic circuit of the data path system and that the clock signal can be ignored because the large scale ASIC generally uses the synchronous clock. It was regarded as a one-output buffer and enabled to be applied to a flip-flop. That is, 1
Input 1 output as dO _j / dC _i , dC _k / dC _i , dO _i
It was possible to generate the test vector by determining the value of / dO _k and substituting it in the equation (5) to find the minimum value of the cost function. The concrete numerical value is illustrated. These are all constants. dO _j / dC _i is a coefficient in the case of a gate having two or more inputs. Therefore, the flip-flop is regarded as a 1-input buffer, and is 0. dC _k / dC _i is a coefficient when the controllability of a certain input changes.
The 1-input and 1-output buffer has the same input and output, and therefore is 1.
Since dO _i / dO _k is a coefficient when the observability of a certain output changes, it is 1 in this case as well. dO _j /
By setting the values of dC _i , dC _k / dC _i , and dO _i / dO _k as described above, it is possible to automatically create a test vector even for a flip-flop that is not in the scan path configuration.

[0020]

By implementing the present invention, it is possible to automatically create a test vector using a random number for a circuit including a flip-flop, and it is possible to reduce the test vector creation time and the test time, and it is high. Achieves fault detection, and has great economic and quality effects. It should be noted that the illustrated constituent devices and display screens are not limited to their models, styles, etc., and modifications of the structures are allowed as necessary without losing the gist of the present invention.

[Brief description of drawings]

FIG. 1 is a flowchart of a test vector generation process.

FIG. 2 is a diagram of a probability of failure detection and a cost function.

[Explanation of symbols]

1: Step 1, beginning of flow chart. 2: Step 2 in the flow chart, judgment of recalculation of random weight. 3: Step 3 of the flow chart, random weight calculation. 4: Flowchart step 4, test vector generation. 5: Step 5 in the flow chart, failure simulation. 6: Step 6 of the flowchart, judgment that the target failure detection rate or the vector number limit value has been reached. 7: Step 7 in the flowchart, delete unnecessary test vectors. 8: Step 8 in the flowchart, end.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location G06F 11/25 17/50 G06F 11/26 310 7623-5L 15/60 360 D

Claims (1)

[Claims] 1. In a test for detecting a stuck-at fault of a logic circuit including a flip-flop not having a scan path configuration, an input of an IC which regards the flip-flop as a buffer having one input and one output and maximizes a fault detection rate. When the probability that a signal has a logical value of 1 is calculated, a test vector in which the probability is weighted by a random number is generated, and the fault coverage of the test vector is calculated by fault simulation, and the fault coverage does not reach the target. Recalculates weights for undetected faults, adds test vectors, and repeats the process of adding test vectors until the fault coverage reaches the target value or the number of test vectors exceeds the limit value.
An automatic test vector creating method, which comprises each step of thinning out test vectors that do not contribute to the improvement of the fault coverage after the fault coverage reaches a target.