JPS61185962A - Complementary mos integrated circuit - Google Patents
Complementary mos integrated circuitInfo
- Publication number
- JPS61185962A JPS61185962A JP60025456A JP2545685A JPS61185962A JP S61185962 A JPS61185962 A JP S61185962A JP 60025456 A JP60025456 A JP 60025456A JP 2545685 A JP2545685 A JP 2545685A JP S61185962 A JPS61185962 A JP S61185962A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- layer
- diode
- diffusion layer
- latch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は相補型ＭＯＳ集積回路に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to complementary MOS integrated circuits.
相補型ＭＯＳ集積回路（以下、０ＭＯＳＩＣという、）
は、消費電力が小さい、動作温度範囲が広い、雑音余裕
度が大きいなどの利点を有する為、近年ＭＯＳＩＣに積
極的に採用されている。ところが、電子機器の小型、軽
量化が要求される現在、０ＭＯＳＩＣの高集積化に伴う
ラッチアップ現象が、０ＭＯＳＩＣを構成する際の解決
すべき重要な問題となっている。Complementary MOS integrated circuit (hereinafter referred to as 0MOSIC)
has been actively adopted in MOSICs in recent years because it has advantages such as low power consumption, wide operating temperature range, and large noise margin. However, now that electronic devices are required to be smaller and lighter, the latch-up phenomenon that accompanies the high integration of 0MOSCs has become an important problem to be solved when configuring 0MOSCs.
第５図は、０ＭＯＳＩＣのラッチアップ現象の説明図で
、０ＭＯＳ構造と寄生トランジスタ及び配線関係の一例
を示した模式的断面図である。同図において、電源線２
の電位が上昇し、出力信号ｌ１１３との電位差がＰ 拡
散層６で形成されるソース−ドレイン間を降伏せしめる
に至ると、発生した降伏電流のＮ−基板９へのリーク電
流がラッチアップを引き起こすトリガとなる。すなわち
Ｐ＋拡散層６からのリーク電流が寄生））Ｎ、ｆ））ラ
ンジスタ１０をオン状態にし、トランジスタ１０のコレ
クタ電流の一部が寄生’？’ＬＰ％トランジスタ１１の
ベース電流となシ、トランジスタ１１がオン状態となる
。ここで、トランジスタｔｏ、ｔｔは正帰還がかかる様
に接続しているので、両トランジスタはオン状態を保ち
、この結果、電源線２〜Ｐ＋拡散層６〜Ｎ−基板９〜Ｐ
−ウェル８〜Ｎ 拡散層７〜接地線ｌの経路に大電流が
流れ続け、この経路間にある配線、接合部が熱破壊する
などの現象が起こる。なお同図において、４．５はゲー
ト電極、８はＰ−ウェルである。FIG. 5 is an explanatory diagram of the latch-up phenomenon of the 0MOSIC, and is a schematic cross-sectional view showing an example of the relationship between the 0MOS structure, parasitic transistors, and wiring. In the same figure, power line 2
When the potential of P increases and the potential difference with the output signal l113 causes breakdown between the source and drain formed by the P diffusion layer 6, the leak current of the generated breakdown current to the N substrate 9 causes latch-up. It becomes a trigger. In other words, the leakage current from the P+ diffusion layer 6 turns on the transistor 10 (parasitic))N, f)), and part of the collector current of the transistor 10 becomes parasitic'? 'LP% When the base current of the transistor 11 decreases, the transistor 11 is turned on. Here, since the transistors to and tt are connected so that positive feedback is applied, both transistors remain on, and as a result, the power supply line 2 to P+ the diffusion layer 6 to N- the substrate 9 to P
-Wells 8 to N A large current continues to flow in the path from the diffusion layer 7 to the ground line l, and phenomena such as thermal destruction of the wiring and junctions between these paths occur. In the figure, 4.5 is a gate electrode, and 8 is a P-well.
以上の様に、従来の０ＭＯＳＩＣでは電源電圧の上昇に
よって、ラッチアップ現象が生じ、魁動作や破損を招き
やすいという欠点があった。As described above, the conventional 0MOSC has the disadvantage that a latch-up phenomenon occurs due to an increase in the power supply voltage, which tends to cause undesirable operation and damage.
従って、本発明の目的は、電源電圧の制御により上記欠
点を除去し、ラッチアップ耐性の高い０ＭＯＳＩＣを提
供する事にある。Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks by controlling the power supply voltage and to provide a 0MOSIC with high latch-up resistance.
本発明の相補型ＭＯＳ集積回路は、半導体基板上に相補
型ＭＯＳ）ランジスメによって構成された集積回路と該
集積回路の電源電圧制御回路を有する相補型ＭＯＳ集積
回路であって、前記集積回路と該集積回路の電源端子の
間に、前記半導体基板と絶縁された領域に設けられた前
記電源電圧制御回路を有している。A complementary MOS integrated circuit of the present invention is a complementary MOS integrated circuit having an integrated circuit formed by a complementary MOS transistor on a semiconductor substrate and a power supply voltage control circuit for the integrated circuit, The power supply voltage control circuit is provided between power supply terminals of the integrated circuit in a region insulated from the semiconductor substrate.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例の要部を示す断面図、第２図
はその回路を示すブロック図である。FIG. 1 is a sectional view showing a main part of an embodiment of the present invention, and FIG. 2 is a block diagram showing its circuit.
本実施例は、第１図、第２図に示すように１・Ｎ−基板
１５上［０ＭＯＳ）ランジスタから構成されたＩＣ１４
と、このＩＣ１４の電源電圧制御回路としての電圧制御
用ダイオード１３を有す０ＭＯＳＩＣであって、電圧制
御用ダイオード１３が、工ＣＬ４と電源バット部１２の
間に、Ｎ″″基板１５とは酸化膜１８によって絶縁され
たダイオード部２１に設けられていることからなってい
る。ここで電圧制御ダイオード１３の制御電圧は、後で
詳しく説明するよう４Ｃ１ＩＣ１４のラッチアップに対
する電源耐圧未満に設定される。又、ＩＣ１４は第１図
において、Ｎ−基板１５の一主面上に、Ｐ−ウェル１６
に形成された、ソース・ドレイン領域としてのＮ＋拡散
層２４．酸化膜１８． ゲートを極２５とよりなるＮ
チャネルＭＯＳ）ランジスタと、Ｎ−基板１５に形成さ
れた、ソース・ドレイン領域としてのＰ＋拡散層２８．
酸化膜１８゜ゲート電極２９とよりなるＰチャネルＭＯ
Ｓ）ランジスタとからなっている。さらに電圧制御用ダ
イオード１３は、ダイオード部２１に設けられた８層２
３と２層２７とからなっている。そしてダイオードの８
層２３はアルミニウム層３３によって、ＰチャネルＭ０
８ト９ンジスタの一方の戸拡散層２８及び電源バット部
１２に接続され、一方ダイオードのＰ層は接地線として
の多結晶シリコン層３１に接続されている。In this embodiment, as shown in FIG. 1 and FIG.
This IC 14 is a 0MOSIC having a voltage control diode 13 as a power supply voltage control circuit, and the voltage control diode 13 is located between the circuit CL4 and the power supply bat part 12, and the N'''' substrate 15 is not oxidized. The diode section 21 is insulated by a film 18. Here, the control voltage of the voltage control diode 13 is set to be lower than the power supply breakdown voltage against latch-up of the 4C1 IC 14, as will be explained in detail later. Further, in FIG. 1, the IC 14 has a P-well 16 on one main surface of the N-substrate 15.
The N+ diffusion layer 24. is formed as a source/drain region. Oxide film 18. The gate consists of pole 25 and N
channel MOS) transistor and a P+ diffusion layer 28 as a source/drain region formed on the N- substrate 15.
P-channel MO consisting of oxide film 18° and gate electrode 29
S) consists of a transistor. Furthermore, the voltage control diode 13 has eight layers 2 provided in the diode section 21.
3 and two layers 27. and diode 8
Layer 23 is formed by aluminum layer 33 to provide P-channel M0
The diode is connected to the diffusion layer 28 and the power supply batt part 12 of one of the 8 transistors, and the P layer of the diode is connected to the polycrystalline silicon layer 31 as a ground line.
次に、本実施例の製造方法について説明する。Next, the manufacturing method of this example will be explained.
第３図（ａ）〜（ｄ）は、本発明の一実施例の製造工程
における断面図である。FIGS. 3(a) to 3(d) are cross-sectional views in the manufacturing process of an embodiment of the present invention.
第３図（ａ）はａｔの多結晶シリコン層１９までを従来
の積層方法と同様に形成したものである。すなわち、１
０Ω・ＣｍのＮ−基板１５上に１００ＫｅＶで８ＸＩＱ
ｃｍ のポロンを注入し、１２００℃、Ｎｚ０ｚ
雰囲気１０時間の熱処理によ、９Ｐ−ウェル１６を形成
し、１０００℃、 Ｈ，Ｏ，雰囲気で膜厚９５００人の
素子分離用の酸化膜１７を形成し、更にｔｏｏｏ℃、Ｈ
２Ｏ２雰囲気で膜厚５００人のゲート部酸化膜１８を形
成した上で、層厚ｓｏｏ。In FIG. 3(a), layers up to the at polycrystalline silicon layer 19 are formed in the same manner as in the conventional lamination method. That is, 1
8XIQ at 100KeV on N-substrate 15 of 0Ω・Cm
Poron of cm was injected, 1200℃, Nz0z
A 9P-well 16 is formed by heat treatment in an atmosphere for 10 hours, and an oxide film 17 for element isolation with a thickness of 9500 mm is formed in an H, O atmosphere at 1000°C, and further heated at too much°C and H
After forming the gate oxide film 18 with a thickness of 500 mm in a 2O2 atmosphere, a layer thickness of soo.
人の第１の多結晶シリコン層１９を形成する。A first polycrystalline silicon layer 19 is formed.
第３図の）は酸化膜上のダイオード部２１の多結晶シリ
コン層を再結晶化し単結晶シリコン層を形成した状態の
断面図である。再結晶化の方法は、まず第３図（ａ）の
チップ上に膜厚１０００人のプラズマＣＶＤ酸化膜２ｏ
を形成し、次に１ダイオ一ド部２１に対して、３０ Ｋ
ｅＶ、直径９０ μｍの連続発振電子ビームを１２ｃｍ
／秒の速度で７０チの照射重複をとシ走査する。3) is a cross-sectional view of the state in which the polycrystalline silicon layer of the diode portion 21 on the oxide film is recrystallized to form a single crystal silicon layer. The method of recrystallization is to first deposit a plasma CVD oxide film 200 nm thick on the chip shown in Figure 3(a).
Then, for one diode part 21, 30K
eV, continuous wave electron beam with a diameter of 90 μm at 12 cm
The irradiation overlap of 70 inches is scanned at a speed of 1/sec.
第３図（Ｃ）はダイオード部２１ＯＮ層２３、及び１拡
散層２４を形成した状態の断面図である。第３図Φ）の
酸化膜２０をエツチング除去した後、Ｐチャネルのトラ
ンジスタ部をレジスト２２でマスクして、９ＱＫｅＶで
５ｘｌＱｃｍ のヒ素を注入する。FIG. 3(C) is a cross-sectional view of the diode section 21 with the ON layer 23 and one diffusion layer 24 formed. After removing the oxide film 20 shown in FIG. 3 Φ) by etching, the P-channel transistor section is masked with a resist 22, and arsenic of 5xlQcm 2 is implanted at 9QKeV.
第３図（ｄ）Ｈ、タイオード部２１ＣＪＰ層２７、及び
Ｐ 拡散層２８を形成した状態の断面図である。FIG. 3(d)H is a sectional view of the diode portion 21CJP layer 27 and P diffusion layer 28 formed.
纂３図（Ｃ）のレジスト２２を除去した後、ｙｒたにレ
ジスト２６でダイオード部２１の８層２３及びＮチャネ
ルのトランジスタ部をマスクして、５０ＫｅＶで６ Ｘ
１０１５ｃｍ ”のボロンを注入する。After removing the resist 22 shown in Figure 3 (C), mask the 8 layers 23 of the diode section 21 and the N-channel transistor section with a yr resist 26, and conduct 6X at 50 KeV.
Inject 1015 cm of boron.
次に、８ｇ３図（ｄ）のレジスト２６を除去した後、ま
ず膜厚５０００人の酸化膜３ｏを形成し、ダイオード部
２１の２層２７、及びＮ＋拡散層２４と、接地線となる
第２の多結晶シリコン層３１間のコンタクト穴を設ける
。次に、層厚３０００ Ａの第２の多結晶シリコン層３
１ｉ形成し、１ｏＯＫｅＶで６ＸｌＯｃｍ のリン
を注入した後ダイオード部２１の８層２３．Ｎ＋拡散層
２４．及びＰ＋拡散層２８とアルミニウム層３３間のコ
ンタクト穴を設ける。更Ｋ、層厚１．０μｍのアルミニ
ウム層３３を形成することＫより、第１図に示す実施例
が得られる。Next, after removing the resist 26 shown in FIG. 8G3(d), an oxide film 3o with a thickness of 5000 is formed, and the second layer 27 of the diode part 21 and the N+ diffusion layer 24 and the second A contact hole is provided between the polycrystalline silicon layers 31. Next, a second polycrystalline silicon layer 3 with a layer thickness of 3000 A is formed.
After forming 8 layers 23.1i of the diode part 21 and implanting phosphorus of 6XlOcm2 at 1oOKeV. N+ diffusion layer 24. And a contact hole is provided between the P+ diffusion layer 28 and the aluminum layer 33. Further, by forming an aluminum layer 33 with a layer thickness of 1.0 μm, the embodiment shown in FIG. 1 is obtained.
第４図はＰ−Ｎ型ダイオードの電圧、電流特性図である
。ダイオードの降伏特性は、自身の不純物濃度が増すに
従ってＢからＡの方向に変化する。FIG. 4 is a voltage and current characteristic diagram of a PN type diode. The breakdown characteristics of the diode change from B to A as its impurity concentration increases.
ここでダイオード部２１の８層２３．２層２７の不純物
密度忙関しては、ラッチアップに対する電源耐圧３５、
最大定格における電源電圧最大値３８Ｖ一対し、逆方向
の動抵抗による電圧降下分３６．３９の余裕をとった値
３７．４０の間で逆電圧降伏する様にヒ素、及びボロン
の注入量が設定されているものとする。Regarding the impurity density of the 8 layers 23 and 2 layers 27 of the diode section 21, the power supply withstand voltage 35 against latch-up,
The amount of arsenic and boron implanted is set so that the reverse voltage breakdown occurs between the maximum power supply voltage of 38 V at the maximum rating and a value of 37.40, which is a margin of 36.39 for the voltage drop due to dynamic resistance in the reverse direction. It is assumed that
以上の様に形成された本実施例のチップにおいては、外
来の過大電圧が電源パッド部１２に印加された場合、電
源線としてのアルミニウム層３３は高電位となるが、か
かる電源線と接地線としての第２の多結晶シリコン層３
１間に接続されている単結晶シリコン層からなる８層２
３，２層２７によって構成されるダイオードが０ＭＯＳ
ＩＣの戸拡散層２８に対して電源線−接地線間の電気的
なバイパス回路をなしていて、電源線−接地線間に印加
される降伏電圧以上の電圧分をリミットする為、Ｐ 拡
散層２８にはラッチアップ電源耐圧以上の電圧が印加さ
れない。又、このリミット効果の際、電流がアルミニウ
ム層３３からダイオード部２１の８層２３，２層２７を
通って第２の多結晶シリコン層３１に流れる事によシ、
Ｐ＋拡散層２８に印加される電圧が下降して％ＣＭＯＳ
ＩＣの動作に支障をきたす事がないのは、第４図のダイ
オードの降伏特性より明らかである。更忙、かかるダイ
オード部２１は、酸化膜１７．１８によ）Ｎ−基板１５
と絶縁されているので、降伏電流、及び降伏電流のリー
クがラッチアップのトリガ要因となる事はない。In the chip of this embodiment formed as described above, when an external excessive voltage is applied to the power supply pad section 12, the aluminum layer 33 serving as the power supply line becomes at a high potential; second polycrystalline silicon layer 3 as
8 layers consisting of single crystal silicon layers connected between 1 and 2
The diode composed of the 3 and 2 layers 27 is 0MOS
The P diffusion layer forms an electrical bypass circuit between the power supply line and the ground line for the IC diffusion layer 28, and limits the voltage applied between the power supply line and the ground line that exceeds the breakdown voltage. A voltage higher than the latch-up power supply breakdown voltage is not applied to 28. Also, during this limit effect, current flows from the aluminum layer 33 to the second polycrystalline silicon layer 31 through the 8th layer 23 and 2nd layer 27 of the diode section 21.
The voltage applied to the P+ diffusion layer 28 decreases and the %CMOS
It is clear from the breakdown characteristics of the diode shown in FIG. 4 that there is no problem with the operation of the IC. Furthermore, such a diode section 21 is formed by an oxide film 17, 18) on an N-substrate 15.
Therefore, breakdown current and leakage of breakdown current will not trigger latch-up.
以上、詳細説明したとおり、本発明によれば半導体基板
上の集積回路にラッチアップ耐圧以上の外来の過大電圧
を加えない様に電源電圧の制御が出来、又、電圧制御回
路が、半導体基板と絶縁された領域に設けられているの
で、電圧制御回路からのリーク電流がラッチアップのト
リガとなる事もない。従って、ラッチアップ耐性が著し
く向上し、今日の高集積化の要求に応じた信頼性の高い
相補型ＭＯＳ集積回路を得る事ができる。As described in detail above, according to the present invention, the power supply voltage can be controlled so as not to apply external excessive voltage exceeding the latch-up withstand voltage to the integrated circuit on the semiconductor substrate, and the voltage control circuit can be connected to the integrated circuit on the semiconductor substrate. Since it is provided in an insulated area, leakage current from the voltage control circuit will not trigger latch-up. Therefore, latch-up resistance is significantly improved, and a highly reliable complementary MOS integrated circuit that meets today's demands for high integration can be obtained.
Ｍ１図は本発明の一実施例を示す断面図、第２図はその
回路を示すブロック図、第３図（ａ）〜（ｄ）はその製
造方法を示す主要工程忙おける断面図、第４図はダイオ
ードの電圧、電流特性図、第５図は相補型ＭＯＳ集積回
路のラッチアップ現象の説明図である。
１２・・・・・・電源バット部、１３・・・・・・電圧
制御用ダイオード、１４・・・・・・集積回路、１５・
・・・・・Ｎ−基板、１６・・・・・・Ｐ−ウェル、１
７．１８・・団・酸化膜、１９・・・・・・多結晶シリ
コン層、２０・旧・・酸化膜、２１・・・・・・ダイオ
ード部、２２・山・・レジスト％ ２３・・・・・・Ｎ
層、２４・・・・・・Ｎ 拡散層、２５・・・・・・ゲ
ート電極、２６・・・・・・レジスト、２７・・・・・
・Ｐ／ｉｔ、２８・・・・・°Ｐ 拡散層、２９・・・
・・・ゲート電極、３０・・・・・・酸化膜、３１・・
・・・・多結晶シリコン層、３２・・・・・・酸化膜、
３３・・・・・・アルミニウム層。
“噸２′卿バ・ツ上゛嵌Ｐ
予２ＴｉＪFigure M1 is a cross-sectional view showing one embodiment of the present invention, Figure 2 is a block diagram showing its circuit, Figures 3 (a) to (d) are cross-sectional views showing the main steps of the manufacturing method, and Figure 4 is a cross-sectional view showing an embodiment of the present invention. The figure is a voltage and current characteristic diagram of a diode, and FIG. 5 is an explanatory diagram of a latch-up phenomenon in a complementary MOS integrated circuit. 12...Power supply bat part, 13...Voltage control diode, 14...Integrated circuit, 15.
...N-substrate, 16...P-well, 1
7.18... group oxide film, 19... polycrystalline silicon layer, 20... old oxide film, 21... diode part, 22... mountain... resist% 23... ...N
Layer, 24...N Diffusion layer, 25...Gate electrode, 26...Resist, 27...
・P/it, 28...°P Diffusion layer, 29...
...Gate electrode, 30...Oxide film, 31...
... Polycrystalline silicon layer, 32 ... Oxide film,
33...Aluminum layer. ``噸2'Kyoba Tsuge゛InsertP YO2TiJ
Claims (1)
成された集積回路と該集積回路の電源電圧制御回路を有
する相補型ＭＯＳ集積回路であって、前記電源電圧制御
回路を、前記集積回路と該集積回路の電源端子の間に、
前記半導体基板と絶縁された領域に設けたことを特徴と
する相補型ＭＯＳ集積回路。A complementary MOS integrated circuit comprising an integrated circuit formed of complementary MOS transistors on a semiconductor substrate and a power supply voltage control circuit for the integrated circuit, the power supply voltage control circuit being connected to the integrated circuit and the power supply for the integrated circuit. between the terminals,
A complementary MOS integrated circuit, characterized in that it is provided in a region insulated from the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60025456A JPS61185962A (en) | 1985-02-13 | 1985-02-13 | Complementary mos integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60025456A JPS61185962A (en) | 1985-02-13 | 1985-02-13 | Complementary mos integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61185962A true JPS61185962A (en) | 1986-08-19 |
Family
ID=12166528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60025456A Pending JPS61185962A (en) | 1985-02-13 | 1985-02-13 | Complementary mos integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61185962A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007294670A (en) * | 2006-04-25 | 2007-11-08 | Toyota Motor Corp | Semiconductor device and method for manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5376677A (en) * | 1976-12-17 | 1978-07-07 | Nec Corp | Semiconductor device |
| JPS53105985A (en) * | 1977-02-28 | 1978-09-14 | Nec Corp | Conmplementary-type insulating gate field effect transistor |
| JPS5429984A (en) * | 1977-08-10 | 1979-03-06 | Hitachi Ltd | Protector for semiconductor device |
-
1985
- 1985-02-13 JP JP60025456A patent/JPS61185962A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5376677A (en) * | 1976-12-17 | 1978-07-07 | Nec Corp | Semiconductor device |
| JPS53105985A (en) * | 1977-02-28 | 1978-09-14 | Nec Corp | Conmplementary-type insulating gate field effect transistor |
| JPS5429984A (en) * | 1977-08-10 | 1979-03-06 | Hitachi Ltd | Protector for semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007294670A (en) * | 2006-04-25 | 2007-11-08 | Toyota Motor Corp | Semiconductor device and method for manufacturing the same |
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