JPS61185958A - Structure and method for mounting three-dimensional lsi - Google Patents

Structure and method for mounting three-dimensional lsi

Info

Publication number
JPS61185958A
JPS61185958A JP2518085A JP2518085A JPS61185958A JP S61185958 A JPS61185958 A JP S61185958A JP 2518085 A JP2518085 A JP 2518085A JP 2518085 A JP2518085 A JP 2518085A JP S61185958 A JPS61185958 A JP S61185958A
Authority
JP
Japan
Prior art keywords
chip
lsi
chip mounting
leads
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2518085A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Sato
佐藤　芳之
Kazuhide Kiuchi
木内　一秀
Masanobu Ohata
大畑　正信
Katsuhiko Aoki
青木　克彦
Junji Watanabe
純二 渡辺
Kunio Koyabu
小薮　国夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP2518085A priority Critical patent/JPS61185958A/en
Priority to PCT/JP1986/000065 priority patent/WO1993013557A1/en
Priority to US06/919,001 priority patent/US4894706A/en
Publication of JPS61185958A publication Critical patent/JPS61185958A/en
Pending legal-status Critical Current

Links

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
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    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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    • H01L2225/06503—Stacked arrangements of devices
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06551—Conductive connections on the side of the device
    • H—ELECTRICITY
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06579—TAB carriers; beam leads
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
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    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1029—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being a lead frame
    • H—ELECTRICITY
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers

Abstract

PURPOSE:To enable to manufacture a three-dimensional LSI mounted structure by a method wherein the chip mounting materials are superposedly fixed through the holes for positioning or cutout grooves thereof and the terminals of the leads of each LSI chip, where are led out on the side surfaces of each chip mounting material, are respectively connected to each bump of the wiring board, which is disposed vertically to each chip circuit. CONSTITUTION:Each chip mounting material 10 is brought its surface, wherein lead-matching grooves 12 are formed, and its side surfaces, whereon the wiring board is disposed, into an insulated state in order to prevent the short-circuit between the LSI leads. When a metal or a semiconductor is used as the chip mounting material, an insulating film such as an SiO2 film is coated on the surface thereof by a method of sputtering and so forth or a surface oxidation is performed on the surface. A chip mounting frame 11 is made in such a depth that the upper surface of the chip becomes slightly lower than the upper surface of the chip mounting material when the chip is mounted on the chip mounting material, the lead-matching grooves 12 are grooves, which guide the leads from the LSI chip along the grooves and are used for making the leads lead out on the side surfaces of the chip mounting material, and holes 13 for positioning are penetrating holes for the bolts for fixation to be used when plural pieces of the chip mounting materials 10 are superposed in the height direction. By superposing and fixing the chip mounting materials, whereon the LSI chip is mounted one by one, in such a way, the three0dimensional LSI mounted structure is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、平面回路構造に形成された大規模集積回路〔
以下ＬＳＩ（エル・ニス・アイ）と記す〕チップの複数
個を高さ方向に重ね合せて一つのケースに高密度に実装
する三次元ＬＳＩ実装構造及び実装法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a large-scale integrated circuit formed in a planar circuit structure [
The present invention relates to a three-dimensional LSI mounting structure and mounting method in which a plurality of chips (hereinafter referred to as LSI) are stacked in the height direction and mounted in a single case with high density.

〔従来の技術とその問題点〕[Conventional technology and its problems]

従来、この種のＬＳＩの三次元実装構造では。 Conventionally, this type of LSI has a three-dimensional mounting structure.

ＬＳＩチップの端子部を配線ボード上のソケットに挿入
する構造（特願昭５４−５４０４５）　、あるいはＬＳ
Ｉチップの端子部を配線ボード上に熱圧着等の方法で接
続する構造（特願昭５５−２７４６１）にみられるよう
に、ＬＳＩチップを一つずつ位置合せを行ないながら実
装して作製してゆく構造であったので、（１）ＬＳＩチ
ップ間隔が詰められない。A structure in which the terminal part of an LSI chip is inserted into a socket on a wiring board (Japanese Patent Application No. 54-54045), or an LS
As seen in the structure (Japanese Patent Application No. 55-27461) in which the terminal part of the I chip is connected to the wiring board by a method such as thermocompression bonding, the LSI chip is manufactured by mounting the LSI chips one by one while aligning them one by one. (1) The spacing between LSI chips cannot be reduced.

（２）製作工程が非効率的である。（３）ＬＳＩチップ
を傷つけないように取り扱うことが難しい。(2) The manufacturing process is inefficient. (3) It is difficult to handle the LSI chip without damaging it.

等の問題点があった。There were problems such as.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明は、従来技術での上記した諸問題点を解決し、チ
ップからのリード（電極接続線）の配線ボード等への一
括接続を可能とし、チップ間の間隔を小とし、１１作工
程を効率化することのできる三次元ＬＳＩ実装構造及び
実装法を提供しようとするものである。The present invention solves the above-mentioned problems in the prior art, enables the leads (electrode connection lines) from the chips to be connected all at once to a wiring board, etc., reduces the spacing between chips, and requires 11 manufacturing steps. The present invention aims to provide a three-dimensional LSI mounting structure and mounting method that can improve efficiency.

〔問題点を解決するための手段〕[Means for solving problems]

本発明では、上記の諸問題点を解決するために。 The present invention aims to solve the above problems.

平面回路構造に形成されたＬＳＩチップの複数個を高さ
方向に重ね合せて一つのケースに高密度に実装する構造
において、各ＬＳＩチップは夫々薄板状のチップ搭載体
の搭載枠内に上面がチップ搭載体上面より僅かに低くな
るように搭載され、各ＬＳＩチップのリードは、各チッ
プ搭載体の表面に電気絶縁して設けられたリード合せ溝
に沿ってチップ搭載体の側面に導き出され、これらのチ
ップ搭載体が夫々に設けた位置合せ用の孔あるいは切欠
溝を介して高さ方向に重ねられ固定されており、各チッ
プ搭載体の側面に導き出されている各ＬＳＩチップのリ
ードの端末がチップ回路に対して垂直に配置された配線
ボードのバンプに夫々接続されている構造を採用する。In a structure in which multiple LSI chips formed in a planar circuit structure are stacked vertically and mounted in a single case with high density, each LSI chip has its top surface placed within the mounting frame of a thin plate-like chip mounting body. The LSI chips are mounted slightly lower than the top surface of the chip mounting body, and the leads of each LSI chip are led out to the side surface of the chip mounting body along lead matching grooves that are electrically insulated on the surface of each chip mounting body. These chip mounting bodies are stacked and fixed in the height direction through alignment holes or notched grooves provided respectively, and the terminals of the leads of each LSI chip are led out to the side of each chip mounting body. A structure is adopted in which the chips are respectively connected to bumps on a wiring board arranged perpendicularly to the chip circuit.

〔発明の実施例〕[Embodiments of the invention]

以下２本発明の実施例について述べる。 Two embodiments of the present invention will be described below.

第１図（ａ）、（ｂ）は夫々９本発明の一実施例に用い
る。ＬＳＩチップを搭載するためのチップ搭載体の平面
図、側面図である。図中のＩＯはチップ搭載体、１１は
チップ搭載枠、　１２はリード合せ溝。FIGS. 1(a) and 1(b) are each used in one embodiment of the present invention. FIG. 2 is a plan view and a side view of a chip mounting body for mounting an LSI chip. In the figure, IO is the chip mounting body, 11 is the chip mounting frame, and 12 is the lead matching groove.

１３は位置合せ用孔である。チップ搭載体１０は、アル
ミナ等のセラミックあるいはＭｏ（モリブデン）等の金
属あるいはＳｉ（シリコン）等の半導体のいずれをも採
用できるが、ＬＳＩリード間の短絡防止のため、リード
合せ溝１２の表面と、後述する配線ボードが配置される
面、即ち第１図（ａ）の側面図で正面に描かれている面
、が絶縁化されている必要がある。チップ搭載体として
金属あるいは半導体を用いる場合、スパッタリング等の
方法により表面にＳｉｎ、（二酸化シリコン）等の絶縁
膜をコーティングするか、あるいは表面酸化を行なうこ
とで、チップ搭載体の表面の絶縁化は可能である。チッ
プ搭載体１０に予め加工されるチップ搭載枠１１は、後
述するＬＳＩチップをその内側に搭載するためのもので
、チップを搭載したときにチップ上面がチップ搭載体の
上面より僅かに低くなるような深さにチップ搭載体上面
に作られるものであり、リード合せ溝１２は、ＬＳＩチ
ップからのリードを、それに沿って案内して側面に導き
出すために上面に作られる溝であり２位置合せ用孔１３
は、チップ搭載体１０の複数個を高さ方向に重ね合せる
際のボルトの通し孔となるものである。13 is an alignment hole. The chip mounting body 10 can be made of ceramic such as alumina, metal such as Mo (molybdenum), or semiconductor such as Si (silicon). It is necessary that the surface on which the later-described wiring board is arranged, that is, the surface depicted in the front in the side view of FIG. 1(a), is insulated. When using metal or semiconductor as the chip mounting body, the surface of the chip mounting body can be insulated by coating the surface with an insulating film such as Sin or (silicon dioxide) by sputtering or by performing surface oxidation. It is possible. The chip mounting frame 11, which is pre-processed into the chip mounting body 10, is for mounting an LSI chip (to be described later) inside thereof, and is designed so that the top surface of the chip is slightly lower than the top surface of the chip mounting body when the chip is mounted. The lead alignment groove 12 is a groove formed on the top surface to guide the leads from the LSI chip along the lead to the side surface, and is used for two-position alignment. Hole 13
These holes serve as holes for bolts when a plurality of chip mounting bodies 10 are stacked one on top of the other in the height direction.

なお、チップ搭載体としては第１図（ｂ）に１００とし
て示すように、チップ搭載枠１１の代りとしてチップ搭
載溝１１１を用い２位置合せ用孔１３の代りとして位置
合せ用切欠溝１３３を用いることもできる。なお、以下
の説用は、第１図（ａ）のチップ搭載体にて行なう。In addition, as a chip mounting body, as shown as 100 in FIG. 1(b), a chip mounting groove 111 is used instead of the chip mounting frame 11, and a positioning notch groove 133 is used instead of the second positioning hole 13. You can also do that. The following explanation will be made using the chip mounting body shown in FIG. 1(a).

第２図は、ＬＳＩチップを搭載したチップ搭載体の実施
例平面図と側面図である。２１はＬＳＩチップ、２２は
リードであり、その他は第１図（ａ）と同じである。Ｌ
ＳＩチップ２１には、配線接続用のリード２２が、リー
ド長が等しくなるように取付けられている。このＬＳＩ
チップ２１は、リード２２がリード合せ溝１２に入り込
み、かつ、チップ搭載体側面からリード先端までの距離
が一定になるように、チップ搭載体１０に接着される。FIG. 2 is a plan view and a side view of an embodiment of a chip mounting body on which an LSI chip is mounted. 21 is an LSI chip, 22 is a lead, and the other parts are the same as in FIG. 1(a). L
Leads 22 for wiring connection are attached to the SI chip 21 so that the lead lengths are equal. This LSI
The chip 21 is bonded to the chip mounting body 10 such that the leads 22 enter the lead matching grooves 12 and the distance from the side surface of the chip mounting body to the lead tip is constant.

第３図は、ＬＳＩチップを搭載したチップ搭載体を重ね
合せて固定し、形成した三次元ＬＳＩ実装構造を示す図
であり、３１は端部固定板、３２は固定用ボルト、３３
はナツトである。第３図に示す構造は、チップ搭載体１
０に予め加工された４つの位置合せ用孔１３に固定用ボ
ルト３２を通して次々にチップ搭載体ＩＯを重ね合せて
、固定用ボルト３２をナツト３３で締結することで実現
できる。なお９両端には、チップ搭載体１０と同じ大き
さで、かつ１等しい位置合せ用孔を有する端部固定板３
１を配置させる。このようにして、リードのピッチが、
縦方向、横方向にそれぞれに揃い、かつ、リード先端位
置が同一平面上にある構造体が得られる。FIG. 3 is a diagram showing a three-dimensional LSI mounting structure formed by stacking and fixing chip mounting bodies on which LSI chips are mounted, in which 31 is an end fixing plate, 32 is a fixing bolt, and 33
is Natsuto. The structure shown in FIG.
This can be achieved by passing the fixing bolts 32 through four alignment holes 13 that have been pre-processed to zero, stacking the chip mounting bodies IO one after another, and fastening the fixing bolts 32 with nuts 33. In addition, at both ends of 9, end fixing plates 3 having the same size as the chip mounting body 10 and having one alignment hole are provided.
Place 1. In this way, the pitch of the reed is
A structure can be obtained in which the lead tips are aligned in both the vertical and horizontal directions and are located on the same plane.

第４図は、第３図構造体における各リードの配線ボード
への接続の一例である。４０は第３図に示した構造体、
４１は配線ボード、４２は配線ボード上のバンプである
。接続に際しては、従来のＣＣＢ（ｃｏｎｔｒｏｌｌｅ
ｄ　ｃｏｌｌａｐｓｅ　ｂｏｎｄｉｎｇ）接続時に行な
われるように１例えば、バンプ４２としてハンダバンプ
を用いて、配線ボード４１上のバンプ４２と構造体４０
からのリード２２の位置を合せ、加熱しながら、バンプ
４２の中にリード２２が垂直に埋め込まれるように、配
線ボード４１と構造体４０とを近づけることにより、接
続することができる。FIG. 4 is an example of how each lead in the structure shown in FIG. 3 is connected to the wiring board. 40 is the structure shown in FIG. 3;
41 is a wiring board, and 42 is a bump on the wiring board. For connection, conventional CCB (controller)
(collapse bonding) 1 For example, using a solder bump as the bump 42, the bump 42 on the wiring board 41 and the structure 40 are connected.
The wiring board 41 and the structure 40 can be connected by aligning the positions of the leads 22 and heating them so that the leads 22 are vertically embedded in the bumps 42.

第５図は、第３図構造体における各リードの配線ボード
への接続の他の一例である。第４図との違いは、構造体
４０からのり−ド２２の先端部を直角に折り曲げた状態
で配線ボード４１上のバンプ４２に接続する点である。FIG. 5 shows another example of the connection of each lead to the wiring board in the structure shown in FIG. The difference from FIG. 4 is that the tip of the glue 22 from the structure 40 is bent at a right angle and connected to the bump 42 on the wiring board 41.

この、リード２２を折り曲げる構造は、第４図で示した
バンプ４２にリード２２を垂直に埋め込むことが難しい
ような細いリードの際に有効である。This structure of bending the lead 22 is effective when the lead 22 is so thin that it is difficult to vertically embed the lead 22 in the bump 42 shown in FIG.

第６図に、リード２２の先端部を、チップ搭載体１０の
側面に沿って直角に折り曲げる方法を示す。FIG. 6 shows a method of bending the tips of the leads 22 at right angles along the sides of the chip mounting body 10.

６１は折り曲げ用のローラであり、このローラ６１を。61 is a roller for folding;

構造体４０の側面に沿って、ころがしながら移動させる
ことで、折り曲げ面を揃えて、リード２２の先端部を直
角に折り曲げることが可能である。By rolling and moving along the side surface of the structure 40, it is possible to align the bending surfaces and bend the tips of the leads 22 at right angles.

第７図は、第３図構造体における各リードの配線ボード
への接続の、さらに他の一例であり、７１は中間板、７
２はハンダボールである６接続は次の順序で行なう。ま
ず、構造体４０のリード２２の位置と等しいピッチの孔
をもつ中間板７１を構造体４０の上にのせることにより
、番孔の中にリード２２が夫々入るようにする。中間板
７１は少なくとも孔の内面を含めた表面層が電気絶縁化
された材料のものであればよい。例えば、中間板７１と
して、　（１００）面の単結晶Ｓｉを用い、ホト工程と
異方性エツチング法を併用すれば、４角錐体の孔を精度
よく形成することができる。表面層の絶縁化は酸化で可
能である。次に、中間板７１の孔の位置にリードに埋め
込まれたハンダボール７２を形成する。このためには孔
にハンダボールを配置し、加熱してもよいし、中間板７
１の孔の位置にハンダを中間板の裏面からマスク蒸着し
、続いて加熱してもよい。このようにして作ったハンダ
ボール７２と中間板７１とが取付けられた構造体の、配
線ボード４１上のバンプ４２への接続は、従来多用され
ているＣＣＢ法にて行なうことが可能である。中間板７
１を用いるこの第７図構造は、第５図に示した。リード
２２を折り曲げる構造と同様に、第４図のバンプ４２に
り−ド２２を垂直に埋め込むことが難しいような細いリ
ードの際に適用して有効である。FIG. 7 is still another example of the connection of each lead to the wiring board in the structure shown in FIG. 3, where 71 is an intermediate plate;
2 is a solder ball. 6 Connections are made in the following order. First, an intermediate plate 71 having holes having the same pitch as the positions of the leads 22 of the structure 40 is placed on the structure 40 so that the leads 22 are inserted into the respective holes. The intermediate plate 71 may be made of a material whose surface layer including at least the inner surface of the hole is electrically insulated. For example, if a (100) plane single crystal Si is used as the intermediate plate 71 and a photo process and anisotropic etching are used in combination, the square pyramidal holes can be formed with high precision. Insulation of the surface layer is possible by oxidation. Next, solder balls 72 embedded in the leads are formed at the positions of the holes in the intermediate plate 71. For this purpose, a solder ball may be placed in the hole and heated, or the intermediate plate 7 may be heated.
Solder may be vapor-deposited using a mask at the position of the hole No. 1 from the back side of the intermediate plate, followed by heating. The structure in which the solder balls 72 and the intermediate plate 71 thus produced are attached can be connected to the bumps 42 on the wiring board 41 by the CCB method which has been widely used in the past. Intermediate plate 7
This FIG. 7 structure using 1 is shown in FIG. Similar to the structure in which the leads 22 are bent, this structure is effective when applied to thin leads where it is difficult to vertically embed the leads 22 in the bumps 42 shown in FIG.

第８図は、チップ搭載体をフィルムキャリアとする場合
に用いる。ＬＳＩチップ搭載用のフィルムキャリアの一
実施例の平面図と側面図で、（ａ）は位置合せ用孔１３
を用いる場合、（ｂ）は位置合せ用切欠溝１３３を用い
る場合である。第８図において、８０及び８００はフィ
ルムキャリア、８１はチップ搭載穴、８２はダミーリー
ドである。チップ２１のフィルムキャリア８０への搭載
は通常のインナーリードボンディング法を用いリード２
２及びダミーリード８２をチップ２１に接続することに
より行なう。FIG. 8 is used when the chip mounting body is used as a film carrier. A plan view and a side view of an embodiment of a film carrier for mounting an LSI chip, in which (a) shows alignment holes 13;
(b) is the case where the positioning notch groove 133 is used. In FIG. 8, 80 and 800 are film carriers, 81 is a chip mounting hole, and 82 is a dummy lead. The chip 21 is mounted on the film carrier 80 using the normal inner lead bonding method.
This is done by connecting 2 and dummy leads 82 to the chip 21.

チップ搭載穴８１及び位置合せ用孔１３はフィルムキャ
リアロールテープ（図示省略）に予め加工されている。The chip mounting hole 81 and the alignment hole 13 are pre-processed in the film carrier roll tape (not shown).

フィルムキャリアロールテープは、チップ２１を搭載し
た後２図示したフィルムキャリア８０の大きさに切断す
る。切断に際しては、ダミーリード８２の端部は、フィ
ルムキャリア８０の切断面に一致するようにし、リード
２２の端部は、配線ボード４１上のバンプ４２への接続
に必要な長さ分だけ。After mounting the chip 21 on the film carrier roll tape, it is cut into the size of the film carrier 80 shown in FIG. When cutting, the ends of the dummy leads 82 should match the cut surface of the film carrier 80, and the ends of the leads 22 should have a length necessary for connection to the bumps 42 on the wiring board 41.

フィルムキャリア８０の切断面からとび出すようにする
。It is made to protrude from the cut surface of the film carrier 80.

第９図は、ＬＳＩチップを搭載したフィルムキャリアと
９弾性体のスペーサとを交互に重ね合せて固定し、形成
した三次元ＬＳＩ実装構造体の実施例図で、　９１はス
ペーサである。この実施例構造体の実現のためには、第
３図において説明したと同様に、固定用ボルト３２にフ
ィルムキャリア８０に作られた位置合せ用孔１３あるい
は位置合せ用切欠溝１３３を通し５重ね合せ、端部固定
板３１とナツト３３を用いて固定する。第３図のチップ
搭載体１０の重ね合せとの相違点は、フィルムキャリア
８０とスペーサ９１を交互に重ね合わせてゆく点である
。スペーサ９１は、フィルムキャリア８０と等しい大き
さを持ち、又、フィルムキャリア８０と同様９位置合せ
用孔１３あるいは位置合せ用切欠溝１３３があけられて
おり、固定用ボルト３２が通せるようにしである。スペ
ーサ９１は９弾性体を用い、フィルムキャリア８０上の
ＬＳＩチップ２１．リード２２及びダミーリード８２の
厚み調整と固定を可能にする。第９図実施例構造は、第
３図構造と同様に２．第４図〜第７図に示す方法での配
線ボード４１上のバンプ４２への接続が可能である。FIG. 9 is an embodiment of a three-dimensional LSI mounting structure formed by alternately overlapping and fixing a film carrier on which an LSI chip is mounted and spacers made of nine elastic bodies, where 91 is a spacer. In order to realize the structure of this embodiment, as explained in FIG. Then, fix them using the end fixing plate 31 and nuts 33. The difference from the stacking of the chip mounting bodies 10 in FIG. 3 is that the film carriers 80 and spacers 91 are stacked alternately. The spacer 91 has the same size as the film carrier 80, and, like the film carrier 80, has nine alignment holes 13 or alignment notches 133, so that the fixing bolts 32 can be passed through. be. The spacer 91 is made of an elastic body, and the LSI chip 21 on the film carrier 80. It is possible to adjust and fix the thickness of the lead 22 and the dummy lead 82. The structure of the embodiment shown in FIG. 9 is similar to the structure shown in FIG. It is possible to connect to the bumps 42 on the wiring board 41 by the methods shown in FIGS. 4 to 7.

〔発明の効果〕〔Effect of the invention〕

以上説明したように１本発明によれば、ＬＳＩチップを
搭載したチップ搭載体を積み重ねて固定することにより
三次元ＬＳＩ実装構造体を得る方式であるので、電極（
リード）位置出しが簡単に行なえるようになり、配線ボ
ード等への一括電気接続が容易に可能であり、又２本構
造では。As explained above, according to the present invention, a three-dimensional LSI mounting structure is obtained by stacking and fixing chip mounting bodies on which LSI chips are mounted.
(Lead) positioning can be easily performed, bulk electrical connection to wiring boards, etc. is easily possible, and the two-piece structure allows for easy positioning.

ＬＳＩチップの一枚分の実質的な厚みは、チップ搭載体
の厚みを薄くすることで、一枚のＬＳＩチップの真の厚
みの２倍以下程度にすることが可能であるため、従来の
一チップずつ位置合せを行なって配線ボードへ接続して
ゆく方法に比べ、（１）ＬＳＩチップの間隔が詰められ
る。（２）製作工程が効率的である。という利点を有す
る。さらに。The actual thickness of one LSI chip can be reduced to less than twice the true thickness of one LSI chip by reducing the thickness of the chip mounting body. Compared to a method in which each chip is aligned and connected to a wiring board, (1) the spacing between LSI chips can be reduced; (2) The manufacturing process is efficient. It has the advantage of moreover.

ＬＳＩチップとして、フィルムキャリア等のチップ搭載
にマウントしたものを用いることができ。As an LSI chip, one mounted on a chip mounting device such as a film carrier can be used.

ＬＳＩチップを裸のままで取り扱う必要がないため、（
３’）ＬＳＩチップを傷つけることなく、容易にハンド
リングできる。という利点も有する。Since there is no need to handle the LSI chip bare, (
3') Easy handling without damaging the LSI chip. It also has the advantage of

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）、（ｂ）は夫々本発明の一実施例チップ搭
載体の平面図と側面図、第２図はＬＳＩチップを搭載し
たチップ搭載体の実施例の平面図と側面図、第３図はチ
ップ搭載体を重ね合せた三次元実装構造を示す図、第４
図及び第５図は夫々第３図構造体の配線ボードへの接続
の一実施例図。 第６図はリードをチップ搭載体の側面に沿って直角に折
り曲げる方法の説明図、第７図は第３図構造体の配線ボ
ードへの接続の他の実施例図、第８図（ａ）、（ｂ）は
夫々ＬＳＩチップを搭載したフィルムキャリアの平面図
と側面図、第９図は第８図のフィルムキャリアを重ね合
せた三次元実装構造を示す図である。 く符号の説明〉1(a) and (b) are respectively a plan view and a side view of a chip mounting body according to an embodiment of the present invention, FIG. 2 is a plan view and a side view of an embodiment of a chip mounting body on which an LSI chip is mounted, Figure 3 is a diagram showing a three-dimensional mounting structure in which chip mounting bodies are stacked one on top of the other.
5 and 5 are respectively diagrams of an embodiment of the connection of the structure shown in FIG. 3 to a wiring board. Fig. 6 is an explanatory diagram of a method of bending the leads at right angles along the side surface of the chip mounting body, Fig. 7 is an illustration of another embodiment of the connection of the structure shown in Fig. 3 to the wiring board, and Fig. 8 (a) , (b) are a plan view and a side view of a film carrier on which an LSI chip is mounted, respectively, and FIG. 9 is a diagram showing a three-dimensional mounting structure in which the film carriers of FIG. 8 are superimposed. Explanation of symbols>

Claims (6)

【特許請求の範囲】[Claims] （１）平面回路構造に形成されたＬＳＩチップの複数個
を高さ方向に重ね合せて一つのケースに高密度に実装す
る構造において、各ＬＳＩチップは夫々薄板状のチップ
搭載体の搭載枠内に上面がチップ搭載体上面より僅かに
低くなるように搭載され、各ＬＳＩチップのリードは、
各チップ搭載体の表面に電気絶縁して設けられたリード
合せ溝に沿ってチップ搭載体の側面に導き出され、これ
らのチップ搭載体が夫々に設けた位置合せ用の孔あるい
は切欠溝を介して高さ方向に重ねられ固定されており、
各チップ搭載体の側面に導き出されている各ＬＳＩチッ
プのリードの端末がチップ回路に対して垂直に配置され
た配線ボードのバンプに夫々接続されていることを特徴
とする三次元ＬＳＩ実装構造。(1) In a structure in which multiple LSI chips formed in a planar circuit structure are stacked vertically and mounted in a single case with high density, each LSI chip is mounted within the mounting frame of a thin plate-shaped chip mounting body. The top surface of the LSI chip is mounted slightly lower than the top surface of the chip mounting body, and the leads of each LSI chip are
Leads are guided to the side of the chip mounting body along the lead alignment grooves provided electrically insulated on the surface of each chip mounting body, and the leads are guided through the alignment holes or notch grooves provided in each of the chip mounting bodies. They are stacked and fixed in the height direction,
A three-dimensional LSI mounting structure characterized in that terminals of leads of each LSI chip led out to the side surface of each chip mounting body are respectively connected to bumps of a wiring board arranged perpendicularly to the chip circuit. （２）前記チップ搭載体として夫々等しい長さに切断さ
れたフィルムキャリア切断片を用い、前記各ＬＳＩチッ
プは夫々上記フィルムキャリア切断片に設けられたチッ
プ搭載穴内に上面がフィルムキャリア切断片上面とほぼ
一致するように搭載され、上記各ＬＳＩチップのリード
は上記各フィルムキャリア切断片の表面に沿ってフィル
ムキャリア切断片の側面に導き出され、これらのフィル
ムキャリア切断片と弾性薄板状のスペーサとが交互に夫
々に設けられた位置合せ用の孔あるいは切欠溝を介して
高さ方向に重ねられ固定され、各フィルムキャリア切断
片の側面に導き出された各チップのリード端末がチップ
回路に対して垂直に配置された配線ボードのバンプに夫
々接続されていることを特徴とする特許請求の範囲第１
項記載の三次元ＬＳＩ実装構造。(2) Film carrier cut pieces cut into equal lengths are used as the chip mounting body, and each LSI chip is placed in a chip mounting hole provided in the film carrier cut piece so that the upper surface thereof is the upper surface of the film carrier cut piece. The leads of each LSI chip are guided to the side of the film carrier cut piece along the surface of each of the film carrier cut pieces, and the film carrier cut pieces and the elastic thin plate-like spacer are mounted so that they almost coincide with each other. The leads of each chip are stacked and fixed in the height direction through alternately provided alignment holes or notched grooves, and the lead terminals of each chip led out to the side of each film carrier cutout are perpendicular to the chip circuit. Claim 1, characterized in that the bumps are respectively connected to the bumps of a wiring board arranged in the
Three-dimensional LSI mounting structure described in section. （３）前記ＬＳＩチップのリード端末の前記配線ボード
への接続が、各ＬＳＩチップから出たリード位置に対応
した孔を持つ中間板を介して、かつ、各ＬＳＩチップか
ら出たリードが配線ボード上のバンプに垂直に埋め込ま
れ、接続されていることを特徴とする特許請求の範囲第
１項あるいは第２項記載の三次元ＬＳＩ実装構造。(3) The lead terminals of the LSI chips are connected to the wiring board through an intermediate plate having holes corresponding to the positions of the leads coming out of each LSI chip, and the leads coming out of each LSI chip are connected to the wiring board. The three-dimensional LSI mounting structure according to claim 1 or 2, wherein the three-dimensional LSI mounting structure is vertically embedded and connected to the upper bump. （４）前記各ＬＳＩチップのリード端末の前記配線ボー
ドへの接続が、各ＬＳＩチップから出たリードの先端部
が面を揃えて折り曲げられて配線ボード上のバンプに接
続されていることを特徴とする特許請求の範囲第１項あ
るいは第２項記載の三次元ＬＳＩ実装構造。(4) The connection of the lead terminals of each LSI chip to the wiring board is characterized in that the tips of the leads coming out of each LSI chip are bent so that their surfaces are aligned and connected to bumps on the wiring board. A three-dimensional LSI mounting structure according to claim 1 or 2. （５）平面回路構造に形成されたＬＳＩチップの複数個
を高さ方向に重ね合せて一つのケースに高密度に実装す
る方法において、各チップを搭載するチップ搭載体の夫
々にチップ搭載前にまず、（イ）チップを搭載したとき
チップ上面がチップ搭載体上面より僅かに低くなる深さ
をもつチップ搭載枠と、（ロ）チップのリードをチップ
搭載体の側面に導き出すための電気絶縁表面をもつリー
ド合せ溝と、（ハ）重ね合せ時の位置合せの案内となる
位置合せ用の孔もしくは切欠溝とを加工する過程と、上
記加工後のチップ搭載体の夫々にチップを接着、搭載し
てチップのリードを上記リード合せ溝に沿ってチップ搭
載体の側面に導き出す過程と、上記チップ搭載後のチッ
プ搭載体の複数個を高さ方向に重ね上記位置合せ用孔を
介して固定する過程と、その後、各チップのリード端末
をチップ回路に対して垂直に配置した配線ボードのバン
プに夫々接続する過程とから成る三次元ＬＳＩ実装法。(5) In a method of densely mounting multiple LSI chips formed in a planar circuit structure in a single case by overlapping them in the height direction, each chip is mounted on each chip mounting body before chip mounting. First, (a) a chip mounting frame with a depth such that the top surface of the chip is slightly lower than the top surface of the chip mounting body when the chip is mounted, and (b) an electrically insulating surface for leading the chip leads to the side of the chip mounting body. A process of machining a lead alignment groove with a diameter, and (c) a positioning hole or notch groove that serves as a guide for positioning during overlapping, and bonding and mounting the chip on each of the chip mounting bodies after the above processing. and guiding the chip leads to the side surface of the chip mounting body along the lead alignment groove, and stacking the plurality of chip mounting bodies after mounting the chips in the height direction and fixing them through the alignment hole. A three-dimensional LSI mounting method comprising the following steps: a. （６）前記各チップのリード端末を前記配線ボードに夫
々接続する際に、チップ搭載体の側面に沿ってローラを
ころがすことにより、上記側面に導き出した各リードを
、折り曲げ面が配線ボード上のバンプ面と一致するよう
に揃えて折り曲げてから、各リード端末を配線ボードの
バンプに接続することを特徴とする特許請求の範囲第５
項記載の三次元ＬＳＩ実装法。(6) When connecting the lead terminals of each chip to the wiring board, roll a roller along the side surface of the chip mounting body so that each lead led out to the side surface is connected so that the folded surface is on the wiring board. Claim 5, characterized in that each lead terminal is connected to the bump of the wiring board after being aligned and bent to match the bump surface.
Three-dimensional LSI mounting method described in section.
JP2518085A 1985-02-14 1985-02-14 Structure and method for mounting three-dimensional lsi Pending JPS61185958A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2518085A JPS61185958A (en) 1985-02-14 1985-02-14 Structure and method for mounting three-dimensional lsi
PCT/JP1986/000065 WO1993013557A1 (en) 1985-02-14 1986-02-14 Structure for mounting the semiconductor chips in a three-dimensional manner
US06/919,001 US4894706A (en) 1985-02-14 1986-02-14 Three-dimensional packaging of semiconductor device chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2518085A JPS61185958A (en) 1985-02-14 1985-02-14 Structure and method for mounting three-dimensional lsi

Publications (1)

Publication Number Publication Date
JPS61185958A true JPS61185958A (en) 1986-08-19

Family

ID=12158801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2518085A Pending JPS61185958A (en) 1985-02-14 1985-02-14 Structure and method for mounting three-dimensional lsi

Country Status (1)

Country Link
JP (1) JPS61185958A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01173742A (en) * 1987-12-28 1989-07-10 Hitachi Ltd Semiconductor device
JPH01309362A (en) * 1988-06-08 1989-12-13 Hitachi Ltd Multichip semiconductor device
JPH08143701A (en) * 1994-11-23 1996-06-04 Interchem Environment Inc Method of decomposing foamed plastic material
RU2584180C2 (en) * 2014-07-17 2016-05-20 Открытое акционерное общество "Научно-исследовательский институт электронной техники" Method of assembling three-dimensional integrated 3d bis circuits

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01173742A (en) * 1987-12-28 1989-07-10 Hitachi Ltd Semiconductor device
JPH01309362A (en) * 1988-06-08 1989-12-13 Hitachi Ltd Multichip semiconductor device
JPH08143701A (en) * 1994-11-23 1996-06-04 Interchem Environment Inc Method of decomposing foamed plastic material
RU2584180C2 (en) * 2014-07-17 2016-05-20 Открытое акционерное общество "Научно-исследовательский институт электронной техники" Method of assembling three-dimensional integrated 3d bis circuits

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