JPS61184981A - Oscillator for clock of controller ic - Google Patents

Abstract

PURPOSE:To generate a stable high-frequency clock and, at the same time, to constitute a voltage controlling oscillator circuit and frequency multiplying circuit including a duty correcting circuit in one piece, by changing charging and discharging by means of the input voltage to the voltage controlling oscillator circuit and multiplying frequencies by means of the frequency multiplying circuit including the duty correcting circuit by inputting the output of the oscillator circuit in the duty correcting circuit. CONSTITUTION:When the output of a NOR circuit G1 is 'low', the potential at the 1st switching element 6 of a capacitor C approximates to potential VSS=0 and the potential at the other end 7 rises since the drain current of a P-MOS transistor P2 charges the capacitor C. When the potential rises to a level at which inverters I5-I7 are switched, a flip-flop (FF) circuit is inverted and the terminal 7 is switched to the potential VSS by an N-MOS transistor N3. Therefore, the voltage at a terminal 6 becomes lower than the VSS. A duty correcting circuit 30 is a phase shifting circuit which sets the duty of the waveform of a VCO output at 50% when the duty is not 50% and two pulses whose phases are different by 90 deg. from each other but whose duties are 50% enter in the input of an EX-OR circuit 39. At this moment, the frequency can be doubled against the original one.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a clock oscillator for a controller IC of a liquid crystal television.

BACKGROUND OF THE INVENTION In recent years, in order to save power in liquid crystal televisions, there is a tendency to use a clock oscillator as a 0-MO8 circuit on the same chip, like other digital circuits. Conventionally, VaO is a two-chip device consisting of an oscillator made of bipolar transistors with stable performance and other circuits of (J-MOS).

Problems to be Solved by the Invention However, the frequency of the clock oscillator of the TV controller air a is 1' OMH2, synchronized with the TV signal, and the temperature drift and voltage drift are small.
The problem with the circuit oscillator was that it had no precedent, partly because LCD televisions were so young.

Means for Solving the Problems The present invention consists of a voltage controlled oscillation circuit, a duty correction circuit, and a frequency multiplication circuit that receive the output of a phase comparator as input, and each of the circuits are connected in series in order to generate the voltage controlled oscillation. The circuit consists of a voltage-current conversion circuit, a current mirror circuit, a switch circuit consisting of two sets of switch elements and a 7-lip-flop circuit (hereinafter referred to as 1!1! circuit), a capacitor, and two columns including an AND circuit in one column. It consists of an inverter circuit, and the duty near correction circuit is set to 50% duty.
The frequency multiplier circuit is configured as a phase shift circuit of a correction circuit, and the frequency multiplier circuit is connected to the phase shift circuit, a phase shift circuit with a 90° phase difference, and an ICX.
.

The voltage-current conversion circuit is configured with an OR circuit, and the voltage-current conversion circuit is an OP/AM
The first and second switch elements are connected to P-MO3SN-MO respectively through the Karen mirror circuit.
It is connected to a switch circuit consisting of an S transistor and a capacitor connected between the connected drains of the first and second switch elements, and the capacitor is charged and discharged by the first and second switch elements via the inverter circuit. At the same time, the PIF circuit is inverted, the charging and discharging is changed by the input voltage to the voltage controlled oscillation circuit, and the output of the voltage controlled oscillation circuit is inputted to the duty correction circuit, so that the frequency multiplication circuit including the duty correction circuit It is configured to multiply the number of decorative waves.

Operation The present invention has the above-mentioned configuration, which causes little drift due to temperature and voltage, and generates stable locking at high frequencies.Since it is constructed from 0-M03Tr, it can be constructed in one piece.

Embodiment FIG. 1 shows a block diagram of an embodiment of the clock oscillator of the present invention, FIG. 2 shows a 700 circuit, and FIG. 3 shows a frequency multiplication circuit.

In FIG. 1, QD is a phase comparator (hereinafter referred to as P and O), α is a voltage controlled oscillator (hereinafter referred to as VaO),
al is a correction circuit that sets the duty of the VAO output waveform to 50%, I is a frequency multiplier circuit, QD is a voltage-current conversion circuit, (2) is a current mirror circuit, C is a charging/discharging capacitor, ) is the inverter circuit for charging, and (c) is F? circuit, (c) is a switch circuit, (to) is a duty correction circuit, (to) is a 90° phase shift circuit, (to) is a frequency multiplication I[f
In the R circuit, 0D1 (to) is a resistor, (to) and (b) are capacitors, and (to) is an inverter. FIG. 4 shows the waveforms of the 34 points and 42 points of FIG. 3 and the output.

A clock oscillator for the controller air a of the present invention (hereinafter referred to as
It is called an oscillator. ) is explained below.

Oscillator of the invention P, O(II)% V OOH1Du
It consists of a series circuit of a ty corrector aj and a frequency multiplier circuit.

vaoaa will be explained based on FIG.

The voltage-current conversion circuit Qυ consists of an OP/AMP OA and a source floor Tr J, and the current mirror circuit (2) consists of two PM OS Tr PI Pz.
The gate of the current mirror circuit (2) is connected to the drain of '1'rN1 for source 7 and the gate of P-MOS Try, P of the current mirror circuit (2). The switch circuit (to) is P-MO3TrP, and N
-MO3TrN2 and P-MO3TrP5 and N-M
Two sets of first and second switch elements of O3TrN51 and 2
A flip-flop circuit (hereinafter referred to as IF7 circuit) (c) consisting of NOR circuits G1 and G2 (hereinafter referred to as IF7 circuit) consists of a first switch element and a second switch element each having a drain, a gate, and a P-MOS Tr P, P. ,
and the connected first switch element (M
OS Tr P4 N, gate '1! ? circuit(
c) A second switch element MO8'I connected to the output terminal of the NOR circuit G2 and one input terminal of the NOR circuit circuit.
'r P, N,) is connected to the output terminal of the NOR circuit circuit of F]11 circuit (c) and one input terminal of the NOR circuit G2, forming a switch circuit, and
A capacitor C is connected between the connected drains of the switch element and the second switch element. Inverters 1, 2, 2, and 2 are connected in series to form an inverter series circuit, and the output terminal of the inverter is connected to the input terminal that is not connected to the gate of the first switch element of the NOR circuit. 3. Engineering. Connect the output end of the series circuit to one of the input ends of AND circuit A, and connect the output end to the input end of the inverter circuit to form a second inverter series circuit, and connect the output end to one of the input ends of AND circuit A.
Connected to the input terminal not connected to the gate of the second switch element of R circuit G2, connected to one of the input terminals of AND circuit A and the output terminal of the inverter, and connected to the gate of the second switch element and the HOR circuit false. Connect the inverter to the connection end of the inverter.

Duty correction circuit (7) is resistor 0υ and inverter (to)
It is a phase shift circuit, consisting of a series circuit of 0υ, a capacitor (to) connected directly between the inverter (to), and a capacitor (to) between the ground terminals, and the phase circuit (to) is the same as the duty correction circuit (7). It consists of a resistor (to), an inverter (to), a capacitor (b), and connections. Connect the output end point (b) of the inverter (to) of the duty correction circuit (to) to one of the input ends of FiX/OR circuit C31, and connect the output end point (b) to one of the input ends of the FiX/OR circuit C31.
The resistance (to) of the phase circuit (to) wo, °still the inverter (to)
Connect the output end of wx-on@path C(l) to the other input end of wx-on@path C(l).

The oscillator of the present invention connects the output terminals of p and oαυ to v c o (
1'3 voltage-current conversion circuit 021)
The output terminal of the OQ3 inverter is connected to the duty correction circuit (
) is connected to the resistor C311.

The operation of the oscillator of the present invention will be explained.

The voltage-current conversion circuit et+ converts the input voltage (VXN) to O
Convert to current using P・AMP and TR (N,) for source follower. From the drain current of this current, D is
It is represented by Rsa-. Current mirror circuit @ is TRN for source follower.

The drain current of is passed to the source of P in P-MO3TrPIP. This current is therefore controlled by the input voltage (VIN) to vCO.

The first switch element P, N and the second switch element P, N are two sets of switches.

When the output of the HOR circuit is LOW, the output of the NOR circuit GL is HIGH, and the P-M OS Tr P5
and N-M OS Tr N2 is ON, ar MO8Trp
4 and N-MO8'r'rN3 are OFF. At this time, the first switch element (6) of the capacitor C is Ye
It approximates the potential of s (=O), and the potential of the other end (7) is P-
The drain current of MO3TrP charges 1 capacitor C, so it rises. When the inverter series circuit reaches a switching level, the FF circuit is inverted and now P-
M OS Tr P, , N-M OS Tr N
When l is ON, P-M OS Tr Bl, N-M
OS Tr N.

becomes opp. Since the terminal (7) is switched to Vsa ("=;O) by N-MO8TrN, the terminal (6)
becomes a voltage lower than Vss. However, 11-M
Since the diode between the second gate and drain of 08TrN2 becomes forward biased, the potential of the terminal (6) immediately becomes V'ss (!#O). and P-MO3TrP
, the capacitor C is charged and the same operation is repeated.

Since the charging current of capacitor a can be controlled by the VaO input, the frequency can be varied.

In Fig. 3, the duty correction circuit (to) is a phase shift circuit that changes the duty of the VaO output waveform to 50% when it is not 50%, and the waveform at the output point (b) is @D in Fig. 4. . (to) is a 90' phase shift circuit with a duty of 50%, and the waveform at the output point (to) is as shown in FIG. EX, OR
The input of the circuit (2) has a duty of 900 different phases.
Two 50% pulses come in. At this time, FiX, OR
The circuit (to) can double the original frequency of (40) as shown in (43) in FIG. 4. When the frequency is four times the original frequency, this circuit can be added.

Effects of the Invention The present invention has the above-mentioned configuration for use in liquid crystal televisions without temperature drift and voltage drift, provides stability and locking of the controller E, and can be constructed in one piece.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of the oscillator of the present invention, FIG. 2 is a detailed diagram of the VOO circuit of FIG. 1, FIG. 3 is a frequency multiplication circuit diagram, and FIG. 4 is a waveform diagram of the output point of FIG. 3. shows. 1]: Phase comparator (P, O) 12: Voltage controlled oscillator (vao) 13: Duty correction circuit 14: Frequency multiplier circuit 15: Oscillation circuit 21
:Voltage-current conversion circuit 22:Current mirror circuit
23: Switch circuit 24: Inverter circuit 25
: IF IF circuit OA : OP/AMP
N, ~N,:N-MO3Tr P, ~P5:
P-MOS Tr O: Capacitor A, :A
ND circuit G, , G, :NOR circuit engineering, ~
Inverter 30: Duty 50% correction circuit 35: Phase circuit 39: KX, OR circuit Patent applicant Matsushita Electric Industrial Co., Ltd. Agent Patent attorney
Isao Abe J); I;/+”-7 Figure 4

Claims (1)

[Claims] Voltage controlled oscillation circuit, Du
It consists of a ty correction circuit and a frequency multiplication circuit, and each of the circuits are connected in series in order, and the voltage controlled oscillation circuit is composed of a voltage-current conversion circuit, a current mirror circuit, two sets of switch elements, and a flip-flop circuit (hereinafter referred to as an FF circuit). ), a switch circuit consisting of a capacitor, and A in one column.
It consists of two rows of inverter circuits including ND circuits, the duty correction circuit is configured as a phase shift circuit of a duty 50% correction circuit, and the frequency multiplier circuit is configured as a phase shift circuit of a 90° duty correction circuit.
Consists of phase shift circuits with different phases, EX and OR circuits,
The voltage-current conversion circuit is configured with an OP/AMP and a source follower transistor N_1 to convert the voltage into a current, and the first and second switching elements are connected to P-MOS) and N-MOS via the current mirror circuit. The device is connected to a switch circuit composed of a transistor and has a capacitor connected between the connected drains of the first and second switch elements, and the capacitor is charged and discharged by the first and second switch elements via the inverter circuit. At the same time, the FF circuit is inverted, the charging and discharging is changed by the input voltage to the voltage controlled oscillation circuit, and the output of the voltage controlled oscillation circuit is inputted to the duty correction circuit, and the frequency multiplication circuit including the duty correction circuit is A clock oscillator for the controller IC that multiplies the frequency.