JPS61184879A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form an effective checking element of a part wherein the relative accuracy of each process poses problems, by changing the width of an ion implanting region to the channel region of a transistor along the longitudinal direction of the channel. CONSTITUTION:In a checking element, which is simultaneously formed together with a memory element, an area, where a gate electrode 1 of the checking element and ion implanting regions 2a and 2b are overlapped, is changed. This is caused by relative position relationship, which is a problem of poor ion implantation region in the capacitor part of a capacitor-part counter electrode 11 of the memory element. Therefore the effective channel width is changed. By measuring a channel current, correlation with respect to the relative position relationship is obtained. Thus defects due to relative errors in a plurality of processes including alignining and etching accuracy, whose clarification has been difficult, can be checked simply. Feedback to the manufacturing processes can be quickly performed, and extensive contribution to the stability of yield rates can be accomplished.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to the structure of an element for checking the manufacturing process of a semiconductor integrated circuit.

[Conventional technology]

Conventionally, simple single transistors have been used as elements for checking the manufacturing process of semiconductor integrated circuits, and the measurement principle of calipers (using a vernier scale divided into 9 scales of the main scale by 10 equal parts, 1/10 of 1 scale of the main scale is used) A pattern for detecting misalignment of about 7 otolithographic layers based on K (which can be measured by ') has been used.

[Problem that the invention seeks to solve]

However, with the recent increase in the degree of integration and miniaturization of elements, the physical quantities that must be detected by individual check elements have also become minute. In cell parts, etc., the relative precision of the ion implantation process of the capacitive part, the alignment of the capacitive part counter electrode formation process, and the relative accuracy of the etching of the capacitive part counter electrode affect the characteristics, but all of these have submicron-order precision. However, there is a drawback that it is very difficult to detect these with individual check elements in each process.

The present invention aims to provide a check element for a semiconductor integrated circuit which eliminates the above-mentioned drawbacks, and particularly an effective check element for parts where the relative accuracy of each process is a problem, such as the capacitive part of a memory cell of a dynamic memory. purpose.

[Means for solving problems]

In the semiconductor integrated circuit of the present invention, in a field effect transistor for checking the manufacturing process formed simultaneously with internal elements, the width of the ion implantation region into the channel region of the transistor is varied along the length direction of the channel. It is composed of

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Figures 1 (al, (bl) to Figure 4 are explanatory diagrams of one embodiment of the present invention, Figure 3 (1al and lbl) are a plan view and a cross-sectional view of the check element of the present invention when it is normal, and Figure 2 is a diagram illustrating an embodiment of the present invention. A cross-sectional view of a normal memory cell, and FIG. 3 (al, (b)
) is a plan view and a cross-sectional view of the check element when misalignment occurs, and FIG. 4 is a cross-sectional view of the memory cell when misalignment occurs.

In FIGS. 2 and 4, reference numeral 11 is the capacitive part counter electrode of the memory cell, whereas in FIGS. 1 and 3, 1 is a check element formed at the same time as the capacitive part counter electrode of the memory cell. This is the gate electrode.

Further, 12a and 12b in FIGS. 2 and 4 are the ion-implanted regions of the capacitive part of the memory cell.
2a and 2b in the figure are capacitive part ion implantation regions 12a and 12b.
and the ion implantation regions of the check elements formed at the same time. Similarly, 3, 4° and 14 are the check element and the source and drain regions of the memory cell formed at the same time.

FIG. 2 is a cross-sectional view of a normally formed memory element as described above, and the channel region indicated by 16 in the figure is determined by the alignment and etching accuracy of the capacitive part counter electrode 11 and the capacitive part ion-implanted region 12a. The length changes depending on the alignment accuracy of the gate electrode, which changes the electrical characteristics, but in extreme cases, as shown in FIG. As a result, a channel cannot be formed, which may result in poor electrical characteristics.

On the other hand, in the check element formed at the same time as the memory element according to the present invention, the relative positional relationship between the gate electrode 1 of the check element and the capacitor ion-implanted region of the capacitor counter electrode 11 of the memory element, which is problematic due to the defect described above, is Since the overlapping region of the ion implantation regions 2a and 2b changes, the effective channel width changes, and when the channel current is measured, a correlation with the above-mentioned relative positional relationship can be obtained.

FIG. 5 is a plan view of another embodiment of the check element of the present invention, in which the rate of change of the width of the ion-implanted region of the check element in the length direction of the channel is increased. Measurement sensitivity can be easily increased.

〔Effect of the invention〕

As explained above, according to the present invention, defects caused by relative errors in multiple processes, including alignment accuracy and etching accuracy, which were difficult to identify in the past, can be easily checked, and feedback to the manufacturing process can be quickly provided, resulting in improved yield. This makes it possible to make a significant contribution to the stability of

[Brief explanation of drawings]

Figures 1 and 4 are explanatory diagrams of one embodiment of the present invention, in which Figures 1 and 4 are a plan view and a sectional view of the check element when it is in normal condition, and Figure 2 is its sectional view when it is in normal condition. A cross-sectional view of a memory cell, and FIG.
FIG. 4 is a cross-sectional view of the memory cell in the case where misalignment occurs, and FIG. 5 is a plan view of another embodiment of the check element of the present invention. 1... Gate electrode of check element, 2a, 2b
.... Ion implantation region, 3 .... Source region, 4 .... Drain region, 11 ... Capacitive part counter electrode, 12a. 12b... Capacitive part ion implantation region, 14...
...Drain region, 15...Gate electrode, 1
6... Channel region, 17... Separation region, 22... Ion implantation region. Agent: Susumu Uchihara, patent attorney...',::,
j) “Tei) ¥1 @! Sir) Kasumi Juei 3 = 1 Hana Yuhyo, 22

Claims (1)

[Claims] A field effect transistor for manufacturing process checking that is formed simultaneously with internal elements, characterized in that the width of an ion implantation region into a channel region of the transistor changes along the length direction of the channel. integrated circuit.