JPS61184328U - - Google Patents

Info

Publication number
JPS61184328U
JPS61184328U JP6765985U JP6765985U JPS61184328U JP S61184328 U JPS61184328 U JP S61184328U JP 6765985 U JP6765985 U JP 6765985U JP 6765985 U JP6765985 U JP 6765985U JP S61184328 U JPS61184328 U JP S61184328U
Authority
JP
Japan
Prior art keywords
phase
circuit
clock
locked loop
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6765985U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6765985U priority Critical patent/JPS61184328U/ja
Publication of JPS61184328U publication Critical patent/JPS61184328U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP6765985U 1985-05-08 1985-05-08 Pending JPS61184328U (enrdf_load_stackoverflow)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6765985U JPS61184328U (enrdf_load_stackoverflow) 1985-05-08 1985-05-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6765985U JPS61184328U (enrdf_load_stackoverflow) 1985-05-08 1985-05-08

Publications (1)

Publication Number Publication Date
JPS61184328U true JPS61184328U (enrdf_load_stackoverflow) 1986-11-17

Family

ID=30601682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6765985U Pending JPS61184328U (enrdf_load_stackoverflow) 1985-05-08 1985-05-08

Country Status (1)

Country Link
JP (1) JPS61184328U (enrdf_load_stackoverflow)

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