JPS61183742A - Program execution control device of floating operation processor - Google Patents

Abstract

PURPOSE:To reduce an overhead of execution of a program, and to improve its throughput by omitting as much as possible saving recovery processing of FPR in case when an execution right of the program moves. CONSTITUTION:A program 103 which is started by an OS101 being on a main memory 100 and the course of execution uses a floating operation register (FPR). When the program 103 is intermitted by the OS101, and the execution move to a program 102, a value of a flag 210 is referred to before the OS101 starts the program 102. In case of on, the OS101 saves the contents of an FPR121 to a saving area 107 on the main memory, and in case of off, processing 230 for executing no saving is executed. After the processing 230 has been executed, the OS101 starts the program 102, and executes it. The program 102 returns to the OS101 after the execution has been ended, therefore, the OS executes processing 231 based on particulars of the processing 230.

Description

[Detailed Description of the Invention] C Field of Application of the Invention] The present invention relates to O8 processing when transferring the execution right of a program in an electronic computer system having floating arithmetic registers, and in particular, to an effective method for saving and recovering processing of arithmetic registers. The present invention relates to a program execution control device.

[Background of the invention]

Usually, a floating arithmetic processor (hereinafter referred to as PPP) has a floating arithmetic register (hereinafter referred to as FPR), and the PPP uses the FPR to perform floating operations and outputs the result after completion. microprocessor (
The CPU (hereinafter referred to as CPU) executes a floating operation by moving the output result of PPP into memory.

However, if the program that requested execution of the floating operation is interrupted by O8 while the operation result is not output, and the execution moves to another program, the FP in the middle of calculation
The question is how to guarantee the contents of R.

The second WI shows the conventional FPR guarantee procedure.

5101 on the main memory 100 is controlled by CPUll0, and executes control of user programs 102 and 103 by tables 105 and 106 for managing programs. Program 102 has a higher execution priority than program 103, and program 102 has higher execution priority than program 103.
2 can be excluded and executed.

FPP120 has FPRI21, and flag is 1 during execution.
I'm putting up 22. The contents of FPRI21 are CPUI 1
0 can be sent to memory 100 via bus 130.

Conventionally, while the low-level program 103 is being executed, ○5
101 and execution moves to the program 102, if the FPP 120 is in use at that time, the FPR 121 is unconditionally moved to the save area 107 on the memory 100.
After that, the program 102 is started and executed. After the execution of the program 102 is finished, the oS 101 transfers the FPRI from the evacuation area 107.
21, a process 141 for restoring the contents was performed, and a procedure was performed for executing the program 103 again. In this case, the program 102
If the program never accesses , processes 140 and 141 are unnecessary.
This will greatly affect the system throughput.

In addition, in the literature describing the processing procedure of the conventional method, SK
“SKY COMPUTE” by Y Coputers
RS FAST FLOATING-POINT PRO
CESSOR FORMULTIBUS SYSTEMS
SYSTEM INTEGRATION MANUAL
”There is.

(Object of the invention) The object of the invention is to
The objective is to reduce the overhead of program execution by omitting PR save and recovery processing as much as possible.

[Summary of the invention]

The key point of the present invention is that a flag is provided in each program or in a table in main memory that controls the execution of the program to indicate whether the program uses PPP, and the O8 uses this flag to start the program. The point is to judge before doing.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

100-107, 110, 120-122 and 130
are the conventional components explained in FIG. Flags 210 and 220 indicate whether each program uses PPP. Each flag is shown in table 105 or
Each table 106 or program 102. or each included in the program 103.

230 and 231 are FPR save processing and recovery processing, respectively, which can be omitted according to the present invention.

FIG. 1 is a flowchart of the O8 FPR saving and recovery processing procedure using the flag 105 or 106.

First, program 1 started and running by ○5101
03 uses PPP. When this program 103 is interrupted by 081o1 and execution moves to program 102, O8101 refers to the value of flag 210 before starting program 102, and if flag 210 is ON, oSlol saves the contents of FPRI 21 to the main memory. After executing process 230, which saves the data to the upper save area 107 and does not save if the flag 210 is OFF, oSlol starts and executes the program 102. Since the program 102 returns to oS101 after execution ends, O8 performs process 231, based on the process 230, to recover if the FPR has been saved, but not to recover if it has not been saved.

Thereafter, the 08IOL returns control to the interrupted program 103 and causes it to execute.

According to this embodiment, it is possible to omit the process of saving and restoring the FPR without fail when PPP is in use, by just a few steps of determining the flag, and thereby the program throughput is improved. Furthermore, since it is not necessary to save and recover each time, there is no need to necessarily prepare an area for save and recover, and the area on the main memory can be used effectively.

〔Effect of the invention〕

According to the present invention, even if the right to execute a program is transferred during execution of a floating arithmetic processor, it is not necessary to save and recover the contents of the floating arithmetic register every time, so that the throughput of the program can be improved.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing the steps of the save and restore process of the present invention, FIG. 2 is an explanatory diagram of the conventional save and restore process for floating arithmetic registers, and FIG. 3 is an explanatory diagram of the save and restore process for floating arithmetic registers according to the present invention. It is. 100... Main memory, 105, 106... Program management table, 120... Floating arithmetic processor, 121... Floating arithmetic register. 210.220... Program flag indicating whether to use a floating arithmetic processor. 230.231... Floating arithmetic register failure 2 figure 1% 0 Procedural amendment (method) Indication of the case of Manabu Shiga, Commissioner of the Patent Office 1985 Patent Application No. 21716 Name of the invention Floating arithmetic processor Relationship between the person who corrects the program execution control device hli and the 4G matter Patent applicant and; M, +5101 Made by Hitachi, Ltd.
Osamu Oriyo Hitoi Hat Address: 5-1 Marunouchi-chome, Chiyoda-ku, Tokyo 1001
Number type company Hitachi, Ltd. ・i story East *212-111
1+Oshirono<) Lines 7 to 10 of page 4 of the specification in the Detailed Description of the Invention section of the specification are deleted and corrected as follows. A document that describes the processing procedure of SKY Compute is “SKY Compute Fast Floating-Point Processor for Multibus Systems System Inhibition Manual” by NIS
rs company “SKY Co+aputers Fast F”
floating-point Processor F
or Multibus Systems
There is a "Integration Manual").

Claims (1)

[Claims] 1. In an electronic computer system having a floating arithmetic processor, a flag indicating whether or not a program uses the floating arithmetic processor is provided in an area on the main memory that controls the program. When the execution of the program being executed using the floating arithmetic processor is interrupted, the process of saving the contents of the calculation register in the floating arithmetic processor to the area on the main memory and restarting the program The process of restoring the saved contents of time to the calculation register,
A program execution control device for a floating arithmetic processor, characterized in that the program execution control device stops based on the value of the flag.