JP3122371B2 - Computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system having a checkpoint restart function. By providing a process dedicated to checkpoint processing, lock runout processing at the time of restart is not required and construction cost is greatly reduced. To a computer system that causes Further, the present invention relates to a computer system in which, even if a failure occurs in some of the processors in a multiprocessor system having a checkpoint restart function, the remaining processors continue processing.

[0002]

2. Description of the Related Art For example, a conventional computer that recovers from a failure by performing processing while acquiring checkpoints during normal times and re-executing the system from the last acquired checkpoint when a failure occurs. The system will be described.

In this computer system, during normal operation, processing proceeds while acquiring a checkpoint of the system. When a failure or the like occurs, the system is re-executed from the last acquired checkpoint, thereby recovering from the failure.

[0004] This checkpoint is obtained in the following cases. (1) When the acquisition of a checkpoint is explicitly instructed in the code. (2) When a certain time has elapsed since the last checkpoint was obtained. (3) When an event (interruption) prompting acquisition of a checkpoint occurs.

[0005] These conditions can occur at any point during program execution. Conventionally, a checkpoint is obtained immediately when this condition occurs, that is, at an arbitrary time during the execution of a program.

FIG. 15 shows a state where a checkpoint process is being performed while the processor is performing a normal process. At time t1, in the occurrence of an event, such as prompting the acquisition of checkpoint accompanied interrupt processing (FIG. 15 (1)) of the check point processing (Fig.
15 (2)) is performed.

[0007] At time t2, in the end processing of the timer interrupt occurs when the checkpoint predetermined time has elapsed since the acquisition (Fig. 15 (3)), the checkpoint processing (FIG. 15 ( 4)).
That is, the checkpoint was obtained during execution of an arbitrary process.

FIG. 16 shows a situation in which a failure occurs during the processing while acquiring checkpoints, and the processing is re-executed from the last checkpoint.
When a failure occurs after the checkpoint is acquired at times t1 and t2 ((1) in FIG. 16 ), the process is executed again from the last acquired checkpoint (t2) (FIG. 16 ).
16 (2)).

However, in general, in consideration of re-execution in the event of a failure, there is usually a "process that must be handled in a certain unit" in the process. One of such processing parts is called a lock runout area.

In the lock run-out area, a checkpoint may be acquired during this time. However, when the system is re-executed from the checkpoint acquired during this time, a failure recovery process is performed before returning to a normal state. Indicates the section that needs to be "run off". This is the section where the spin lock is acquired.

[0011] A spin lock is a lock that cannot sleep when the lock is acquired and must continue to spin on the processor until the lock can be acquired.

When acquiring this spin lock, care must be taken so that deadlock does not occur. Normally, when a lock class with a level is added to each spin lock and another spin lock is acquired while the spin lock has already been acquired, for example, the lock class of the currently acquired spin lock is It is designed so that only spin locks of a lock class of a lower level than the lowest one of the levels can be acquired. By managing the acquisition of spin locks in this way, the order of lock acquisition by each processor is guaranteed.

For example, as shown in FIG. 17, the level of the lock class is set, and "Processing A" accompanying the lock operation is performed.
When the processor and the "process D" are executed simultaneously and both locks must be acquired at the same time, each processor always acquires the lock of the "process D" (level L5). And then lock the "process A" (level L
3) must be followed.

Here, the reason why the lock needs to be run out will be described with reference to FIGS.
FIG. 18 shows an example in which deadlock occurs because lock runout is not performed.

Now, in the processor (0), the process T0
However, in the processor (1), the process T1 is being executed, and the process T0 has the spin locks L5 and L3.
It is assumed that the process T1 has acquired the checkpoint while acquiring the spin lock L4.

Then, consider a case where a fixed fault occurs in the processor (0). In this case, only the processor (1) operates normally, so that the processor (1) processes the process T0 and the process T1.
Must be performed. Although the spin locks currently acquired by the process T0 and the process T1 can be recognized, it is necessary to predict what behavior the process T0 and the process T1 will exhibit, that is, what spin lock will be acquired. Can not.

Therefore, it is assumed that after the recovery is executed, the process T0 which has acquired the lower level spin lock is dispatched to the processor (1). Further, it is assumed that the process T0 releases the spin lock L3 that has already been acquired, and then newly acquires the spin lock L4. However, this spin lock L4
Since the process T1 executed by the processor (1) before the occurrence of the failure has acquired the process, the process T0 cannot acquire the spin lock forever. That is, a deadlock occurs. This problem is caused by the fact that although two processors guarantee the order of spin lock acquisition before the failure, one processor has failed, and the spin lock acquisition guaranteed by each processor has failed. Is lost.

As a method for solving this problem, a lock run-out function is known. This function releases all spinlocks acquired at the time of the checkpoint before re-executing from the checkpoint,
This is to make all processes independent of a specific processor, and takes the following steps.

(1) Select the process that has acquired the lowest level of spin lock from the spin locks that had been acquired when the checkpoint was acquired. (2) Make the processor appear to the processor that was executing the selected process and execute that process until the spinlock is released.

(3) During the release processing of the spin lock, it is checked whether or not a process that has acquired the spin lock still exists. (4) If present, repeat from the processing of (1). If it does not exist, the lock runout processing ends.

That is, for example, when the spin lock has been acquired as shown in FIG.
Is selected (L3 is the lowest level), and this process T0 is executed until the spin lock L3 is released.

Next, the process T1 acquiring the lowest level L4 is selected (FIG. 19B), and the process T0 acquiring L5 after its release is selected (FIG. 19C), and the lock run-out is performed. Is completed. After the lock run-out is completed, the system performs a restart.

In order to realize the lock run-out process executed in such a procedure, it is necessary that the spin lock release process calls a special dispatch mechanism during the lock run-out.

[0024]

As described above, according to the conventional checkpoint acquisition method, software (OS:
In the operating system), a special dispatch mechanism as described above had to be implemented in order to extract a processing portion such as a lock runout area and protect those "units".

For this reason, if the cost of the computer system must be increased, there is a problem that the software implementation is restricted. Accordingly, the present invention has been made in view of the above circumstances, and provides a computer system that does not require a lock runout process at the time of restart by providing a process dedicated to checkpoint processing, thereby greatly reducing the construction cost. The purpose is to do.

Another object of the present invention is to provide, in a multiprocessor system having a checkpoint restart function, a computer system which can continue processing on the remaining processors even if some of the processors fail. I do.

[0027]

[0028]

In order to achieve the above object, the present invention provides at least one processor and a checkpoint for restarting a process provided corresponding to the processor and interrupted due to a failure or the like. and checkpoints dedicated to processing the process of obtaining, during execution
Interrupt means for interrupting the process of step (a) , and changing the process dedicated to checkpoint processing from a standby state to an executable state, dispatching means for dispatching the process dedicated to checkpoint processing made executable by the interrupt means, and dispatching by the dispatching means And a standby state unit for resuming the checkpoint process only after the obtained checkpoint process obtains the checkpoint.

Therefore, according to such a configuration, the interrupting means interrupts the running process ,
Change the process dedicated to checkpoint processing from the standby state to the executable state. Next, the dispatching unit dispatches the checkpoint processing dedicated process which has been made executable by the interrupting unit, and acquires a checkpoint. As a result, at the time of checkpoint acquisition, no other processes are in the running state, so there is no possibility that a deadlock will occur.

Then, after the checkpoint processing dedicated process dispatched by the dispatching means acquires the checkpoint, the standby state shifting means sets the checkpoint processing dedicated process again to the standby state.

Further, in order to achieve the above object, the present invention provides at least one processor and, when a checkpoint acquisition condition is satisfied, acquisition of a checkpoint for restarting a process interrupted due to a failure or the like. and checkpointing execution instruction means for instructing, provided to the dispatcher operating system, the from the check point processing execution instruction means disperser
Is instructed to take a checkpoint,
Called by the dispatcher and sent to the processor
Checkpoint to get each corresponding checkpoint
A preparative process unit, the check after the checkpoint
In the computer system, characterized by comprising a standby state means that the standby state again the Kkupointo processing means.

Therefore, according to such a configuration, when acquisition of a checkpoint is instructed by the checkpoint acquisition instructing means, the executable means makes the checkpoint acquiring means executable. Next, the dispatch unit dispatches the checkpoint acquisition unit that has been made executable by the executable unit. As a result, at the time of checkpoint acquisition, no other processes are in the running state, so there is no possibility that a deadlock will occur.

Then, after the checkpoint obtaining means dispatched by the dispatching means obtains the checkpoint, the standby state shifting means sets the checkpoint obtaining means to the standby state again.

Further, according to the present invention, the process in the running state at the time of acquiring the checkpoint is only the process dedicated to the checkpoint processing. Since all other normal processes are not dependent on the processor, even if a fixed failure occurs in a specific processor of the multiprocessor system, the process dedicated to the checkpoint processing for that processor is executed. Otherwise, the system can be easily reconfigured (processor degeneration).

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a diagram showing a schematic configuration of a computer system according to one embodiment of the present invention.

A processor 10 is connected to the internal bus 11. The internal bus 11 has a memory 1
2. B for storing the image data before updating of the memory 12
IB (Before Image Buffer) 13
Is connected.

The memory 12 stores software including an operating system (OS) executed by the processor. FIG. 14 is a diagram for explaining the checkpoint / rollback function of the computer.

As shown in FIG. 5, at time t0, the contents of addresses 0, 1, 2, and 3 in the memory are a, b, c, and d, and it is assumed that no data is stored in the BIB. This state is referred to as CKP.

Thereafter, at time t1, the processor issues an instruction to store x at address 1. As a result, the content of the address 1 in the memory changes to x. At this time, the BIB stores the pre-update information of the memory, that is, the fact that “address 1 is b”.

Next, at time t2, the processor
When the instruction to store Y at the address is issued, BIB is the update information of the memory , that is, "address 2 is C" before the contents of address 2 of the memory are rewritten to Y. Is stored. Thereafter, it is assumed that a failure has occurred at time t3.

In this case, if the update information of the memory stored in the BIB is reflected in the memory in a procedure reverse to that when the information is stored, the state of the memory is changed to the state before the update, that is, the CKP at the time t0. You can roll back to the state.

If the process proceeds without a failure at time t3, the information stored in the BIB is cleared at an appropriate time and the state of the memory at that time is changed to C3.
In the case of KP, the generation of CKP will advance.

FIG. 2 is a functional block diagram for explaining functions of software stored in the memory 12. 2
1 is a process dedicated to checkpoint processing.
2 is in the standby state.

When the checkpoint acquisition condition is satisfied, the checkpoint processing dedicated process 21 in the standby state is made executable by using the wake-up unit 23.

The checkpoint acquisition condition is BIB13
Is stored when a predetermined amount of data is stored in the. Note that the checkpoint acquisition condition may be satisfied in the following cases.

(1) An AIB (After Image Buf) for storing the updated image data in the memory 12
fer) when a predetermined amount of data is stored. (2) When a checkpoint is explicitly specified in the code.

(3) When a certain time has elapsed since the last checkpoint was obtained. The checkpoint process-dedicated process 21 in the executable state is selected by the dispatcher 24. As a result, the checkpoint processing dedicated process 21 enters an execution state, and acquires a checkpoint.

If the checkpoint acquisition condition is satisfied, the priority (execution priority) of the checkpoint processing dedicated process 21 is increased in order to acquire the checkpoint as soon as possible. We do not accept.

Next, the operation will be described with reference to FIGS. FIG. 3 shows a process 21 dedicated to checkpoint processing.
3 is a flowchart showing the flow of the processing of FIG.

Check Point Processing Dedicated Process 21
Is normally in a standby state (step A1), but when the checkpoint acquisition condition is satisfied, the wake-up unit 23
Wakes up and becomes executable. Then, a checkpoint process is dispatched by the dispatcher 24 to acquire a checkpoint (step A2). When it is over, it returns to the standby state again.

FIG. 4 is a flowchart showing the flow of processing for notifying the establishment of the checkpoint acquisition condition and waking up the checkpoint processing dedicated process 21 in the standby state.

As shown in FIG. 4, when the checkpoint acquisition condition is satisfied, a process for notifying the establishment of the checkpoint acquisition condition is executed by interruption processing or a subroutine call (step B1). Here, the checkpoint processing dedicated process 21 in the standby state is set in the executable state.

The transition of the checkpoint processing dedicated process 21 to the standby state or the executable state is performed only for a specific process. For example, in UNIX, for the purpose of specifying the process to be woken up, a specific process is performed. (In this case, S) is used.

FIG. 5 is a flowchart showing the flow of processing when re-executing from a checkpoint acquired by the checkpoint processing dedicated process 21. In this case, the state of the checkpoint acquired last is first restored (step C1), and then the process 21 dedicated to checkpoint processing is set as the current process.
The process is executed from the top (step C2). Alternatively, the context of the process dedicated to checkpoint processing saved during the checkpoint may be restored.

Next, the operation of the computer system according to the present embodiment will be described with reference to FIGS. FIG.
Is a diagram for explaining the operation of the computer system of the present embodiment.

While the processor is executing an arbitrary process x, if the data amount of the image data before updating of the memory 12 stored in the BIB 13 reaches a predetermined data amount, the BIB 13 checks with the processor 10. Issue a point collection request interrupt.

Here, it is assumed that the BIB 13 interrupts the processor (1). When an interrupt is issued from the BIB 13 to the processor (1), the processor (1) temporarily interrupts the process of the process x being executed and performs an interrupt process ((1) in FIG. 6).

In this interrupt processing, the wake-up section 23 makes all the checkpoint processing dedicated processes 21 in the standby state executable (ready) (FIG. 6 (2)).

FIG. 7 is a diagram for explaining a case where a checkpoint processing dedicated process in the sleep state is set to the ready state. At this time, the priority (execution priority) of the checkpoint process dedicated process 21 in the ready state is set to be high so that it can accept only a special interrupt such as a failure notification.

When the interrupt processing is completed, the processor (1) resumes the execution of the process x which has been suspended, and when one execution unit of the process x is completed, the dispatcher 24 is subsequently called (FIG. 6). (3)).
The call of the dispatcher 24 is performed by control such as time sharing processing.

The dispatcher 24 finds a high-priority process and causes the processor to execute the process in a running state. Here, since the checkpoint processing dedicated process 21 having a high priority has been woken up, the dispatcher 24 selects the checkpoint dedicated process 21 and causes the processor to execute the process to acquire the checkpoint (FIG. 6). (4)).

In the conventional computer system, the acquisition of the checkpoint is performed in an arbitrary interrupt process of an arbitrary process. Therefore, the process has a spin lock or accesses a processor-dependent resource. Could have been. Therefore, this may cause a deadlock.

On the other hand, in the computer system according to the present embodiment, since the checkpoint is acquired by the checkpoint processing dedicated process 21 dispatched by the dispatcher 24 , no other processes are in the running state. For this reason, deadlock does not occur at the time of restart as in the conventional computer system.

When the acquisition of the checkpoint is completed, the checkpoint processing dedicated process 21 enters the sleep state again ((5) in FIG. 6), the dispatcher is called, and an arbitrary normal process starts again. Is selected ((6) in FIG. 6).

As described above, when the checkpoint processing dedicated process 21 is used, the checkpoint is always acquired only in the checkpoint processing dedicated process 21.

As a result, the lock run-out process at the time of restart is not required, and the operating system including the checkpoint acquisition function can be greatly simplified.
The construction cost can be significantly reduced.

Also, by adopting such a configuration,
The following effects can also be obtained. FIG. 8A is a diagram illustrating a multiprocessor system. In this example,
It is assumed that the multiprocessor system has four processors of processor (0) to processor (3). When acquiring a checkpoint, each processor 10 dispatches a checkpoint processing dedicated process 21 corresponding to the processor. I do.

Specifically, in a multiprocessor system, the checkpoint acquisition method includes (1)
There are two methods: a method in which processors having a data dependency are synchronized to collect checkpoints simultaneously, and a method (2) in which all processors synchronously collect checkpoints simultaneously.

However, since it is generally difficult to manage the data dependence between processors and the overhead is large, the method (2), ie, all the processors collect checkpoints simultaneously and synchronously Often do.

In the multiprocessor system according to the present embodiment, it is assumed that all processors simultaneously take checkpoints in synchronization. This indicates that only the process 21 dedicated to the checkpoint process is being executed at the time of obtaining the checkpoint, and that no other process is in the execution state.

[0071] In this case, for example, to a specific processor 10
Consider a case where an intermittent failure occurs. In this case, in the failure recovery processing, the state of the system is rolled back to the last acquired checkpoint, and then the checkpoint processing dedicated process 21 executed by each processor at the time of acquiring the checkpoint may be resumed.

Next, with reference to FIG. 8B, for example, consider the case where permanent fault in a particular processor 10 occurs.
In this case, in the failure processing, the state of the system is rolled back to the last acquired checkpoint, and thereafter, the checkpoint processing dedicated process 21 executed by each processor at the time of acquiring the checkpoint is resumed.

However, the processor 1 in which the fixed failure has occurred
0 (the processor (1) in FIG. 8B) cannot execute the process. As a result, the checkpoint processing dedicated process 21 executed by the processor in which the fixed failure has occurred.
Since (i) is not executed by any processor and no other normal process is dispatched to the failed processor, the detachment of the processor that caused the fixed failure (processor degeneration, reconfiguration ) Can be easily realized.

(Second Embodiment) FIG. 9 is a diagram showing a schematic configuration of a computer system according to a second embodiment of the present invention.

A processor 10 executes software including the operating system 20. Reference numeral 24 denotes a dispatcher having a checkpoint processing unit 25. The dispatcher 24 does not always call the checkpoint processing unit 25, but calls it only when the checkpoint processing execution instructing unit 26 instructs execution of the checkpoint processing. And if the checkpoint acquisition condition is satisfied, execution of the check point processing is instructed by the check point processing execution instruction portion 26.

When the execution of the checkpoint processing is instructed by the checkpoint processing execution instructing section 26, the dispatcher 24 calls the checkpoint processing section 25.

The checkpoint processing execution instruction is
For example, when a variable in software is used as a flag and execution of checkpoint processing is instructed, the flag is set (1). Therefore, dispatcher 2
4 only needs to call the checkpoint processing unit 25 only when this flag is set (1).

Next, an operation procedure of the computer system according to the present embodiment will be described with reference to FIGS. FIG.
5 is a flowchart showing a flow of processing of the dispatcher 24 including the checkpoint processing unit 25.

The dispatcher 24 having the checkpoint processing unit 25 is the checkpoint processing execution instructing unit 2
6 is monitored (step D1). If execution of the checkpoint processing unit 25 is instructed, the execution instruction of the checkpoint processing unit 25 is cleared (step D2). Then, checkpoints are collected (step D3).

When the collection of the checkpoint is completed, a normal dispatcher process is executed (step D4). That is, a process with a higher priority is selected, and the processor executes the process.

FIG. 11 is a flowchart showing the flow of processing for notifying the establishment of the checkpoint acquisition condition and instructing the dispatcher 24 to execute the checkpoint processing section 25 .

As shown in FIG. 11, when the checkpoint acquisition condition is satisfied, a process for notifying the establishment of the checkpoint acquisition condition is executed by interruption processing or a subroutine call (step E1). Here, execution of the checkpoint processing unit 25 is instructed.

As described above, the execution instruction of the checkpoint processing unit 25 uses, for example, a variable in software as a flag, and
Is set (1) when the execution of the instruction is instructed. Therefore, the dispatcher 24 may call the checkpoint processing unit 25 only when this flag is set (1).

FIG. 12 is a flowchart showing the flow of processing when re-execution is performed from a check point acquired by the check point processing unit 25. In this case, the state of the checkpoint acquired last is restored first (step F1), and then the dispatcher 24 is called from the top (step F2).

Here, the operation of the computer system according to the present embodiment will be described with reference to FIG. While the processor is executing an arbitrary process, if an interrupt is generated to the effect that the checkpoint acquisition condition is satisfied ((1) in FIG. 13), the checkpoint processing unit 26 is instructed via the checkpoint processing execution instruction unit 26. 25 (see FIG. 1).
3 (2)).

Thereafter, control returns to the original process, and when one execution unit of this process ends, the dispatcher 24 is subsequently called. However, since execution of the checkpoint processing unit 25 has already been instructed, the dispatcher 24 Instructs execution of the checkpoint processing unit 25,
A checkpoint is obtained ((3) in FIG. 13).

When the acquisition of the checkpoint is completed, the dispatcher 24 returns to the normal dispatcher processing of selecting a process with a high priority and causing the processor 10 to execute the process ((4) in FIG. 13). .

As described above, the checkpoint processing unit 25
In the case where the dispatcher 24 provided with is used, the acquisition of the checkpoint is always executed only in the dispatcher, so that the lock runout at the time of restart is not required. Therefore, the operating system including the checkpoint acquisition function can be greatly simplified, and the construction cost can be significantly reduced.

Therefore, according to the computer system of the above embodiment, a checkpoint is always acquired only in the checkpoint acquisition process or in the dispatcher. This eliminates any other process being executed at the time of checkpoint acquisition, eliminating the need to consider the "units" described above, which had to be considered in the conventional checkpoint acquisition method. Operating system can be greatly simplified. As a result, the cost of construction or improvement can be significantly reduced.

In a multiprocessor system, even if a fixed failure occurs in one of the processors,
By suppressing the execution of the process dedicated to the checkpoint process for the processor in which the failure has occurred, it is possible to easily realize the reconfiguration of the system (degeneration and separation of the processor).

[0091]

As described above, according to the present invention, by providing a process dedicated to checkpoint processing,
The lock runout process at the time of restart is not required, and the construction cost can be significantly reduced. Further, in a multiprocessor system having a checkpoint restart function, even when a failure occurs in some of the processors, processing can be continued in the remaining processors. Further, in a multiprocessor system having a checkpoint restart function, even when a failure occurs in some of the processors, there is an excellent effect that processing can be continued in the remaining processors.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a hardware configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is an exemplary functional block diagram for explaining functions of software stored in a memory of the computer system according to the embodiment;

FIG. 3 is an exemplary flowchart showing the flow of the process of a checkpoint process dedicated process according to the embodiment;

FIG. 4 is an exemplary flowchart showing the flow of a process for waking up a process dedicated to checkpoint processing according to the embodiment.

FIG. 5 is an exemplary flowchart showing the flow of processing when re-execution is performed from a checkpoint acquired by a checkpoint processing dedicated process according to the embodiment;

FIG. 6 is an exemplary view for explaining the operation of the computer system according to the embodiment;

FIG. 7 is an exemplary view for explaining a case where a checkpoint processing dedicated process in a sleep state according to the embodiment is set to a ready state;

FIG. 8 is a block diagram (8A) showing the configuration of the multiprocessor system according to the embodiment, and a diagram (8B) for explaining the operation of the multiprocessor system when a fixed failure occurs in the system; ).

FIG. 9 is a block diagram showing a configuration of a computer system according to a second embodiment.

FIG. 10 is a flowchart showing a processing flow of a dispatcher having a checkpoint processing unit according to the embodiment;

FIG. 11 is a flowchart showing a flow of a process for instructing a dispatcher to execute a checkpoint processing unit according to the embodiment;

FIG. 12 is a flowchart showing a flow of processing when re-executing from a checkpoint acquired by a checkpoint processing unit according to the embodiment;

FIG. 13 is an exemplary view for explaining the operation of the computer system according to the embodiment;

FIG. 14 is an exemplary view for explaining a checkpoint / rollback function of the computer according to the embodiment;

FIG. 15 is a diagram showing a state where a conventional computer system is executing a checkpoint process while performing a normal process.

FIG. 16 is a diagram showing a state in which a failure has occurred while a conventional computer system is proceeding with processing while acquiring checkpoints, and the computer system is re-executing from the last check.

FIG. 17 is a diagram showing a conventional example of setting a lock class level.

FIG. 18 is a diagram for explaining occurrence of a deadlock.

FIG. 19 is a diagram for explaining a lock run-out process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Processor, 12 ... Memory, 13 ... BIB, 21 ... Checkpoint processing dedicated process, 22 ... Sleep part, 23 ... Wakeup part, 24 ... Dispatcher, 25 ... Checkpoint processing part.

Claims (12)

(57) [Claims] At least one processor, a process dedicated to a checkpoint process provided for the processor and acquiring a checkpoint for restarting a process interrupted due to a failure, and a process being executed Interrupting means for interrupting the checkpoint processing process from a standby state to an executable state; dispatching means for dispatching the checkpoint processing process enabled by the interrupting means; and A computer system comprising: a standby state transition unit that, after the dispatched process dedicated to checkpoint processing acquires a checkpoint, sets the process dedicated to checkpoint processing to a standby state again. 2. The computer system according to claim 1, wherein the interruption processing by said interruption means is performed after a checkpoint acquisition condition is satisfied. 3. The computer system according to claim 2, wherein the checkpoint acquisition condition is satisfied when a checkpoint acquisition is instructed in the code of the processor. 4. The computer system according to claim 2, wherein the checkpoint acquisition condition is satisfied after a predetermined time has elapsed after the checkpoint is acquired by the checkpoint processing dedicated process. 5. The computer system according to claim 2, wherein the checkpoint acquisition condition is determined by a data amount of image data stored in a before image buffer for acquiring image data before updating the memory. . 6. The computer system according to claim 2, wherein the checkpoint acquisition condition is determined by a data amount of image data stored in an after-image buffer for collecting image data after updating the memory. . 7. The computer system according to claim 1, wherein the dispatching of the process dedicated to the checkpoint process by the dispatching unit is performed by a time sharing process. 8. The apparatus according to claim 1, further comprising a restoring means for restoring the state of the processor at the time of the last checkpoint acquired by the process dedicated to checkpoint processing when a temporary failure occurs in any of the processors. The computer system according to claim 1, wherein 9. The computer system according to claim 8, wherein, after the state of the processor is restored by the restoring unit, the process of the processor is executed with the checkpoint processing dedicated process as a current process. 10. When a fixed failure occurs in any of the processors, the state of the processor other than the processor in which the fixed failure has occurred is changed by the checkpoint processing processor which was last acquired by the checkpoint processing dedicated process. 2. The computer system according to claim 1, further comprising restoring means for restoring the state. 11. The processor according to claim 7, wherein after the restoration of the state of the processor by the restoration unit, the process other than the processor in which the fixed failure has occurred is executed by using the checkpoint processing dedicated process as a current process. 10. The computer system according to 10. 12. At least one processor and, when a checkpoint acquisition condition is satisfied, execution of a checkpoint process for instructing acquisition of a checkpoint for restarting a process interrupted due to a failure or the like.
Instruction means , provided in a dispatcher of the operating system, and transmitted from the checkpoint processing execution instruction means to the
When a dispatcher is instructed to acquire a checkpoint
Is called by the dispatcher and
Check to get each checkpoint corresponding to the checker
And point processing unit, the checkpoint processing after the checkpoint
And a standby state transition unit for setting the management unit to a standby state again.