JPS58217056A - Task control system of multiprocessor system - Google Patents

Abstract

PURPOSE:To allow synchronism collation even when two microprocessors differ in processing time greatly to cause deviation in timing, by synchronizing both microprocessors with each other on the basis of the judgement of a main system once data from an external device is concatenated to a task. CONSTITUTION:A main microprocessor 11 and a conventional microprocessor 12 are connected to the external device 8, and synchronous data transmitter and receivers 13 and 14 are coupled with those microprocessors 11 and 12 and coupled mutually through a synchronism data transfer line 15 to constitute a synchronous port. Input data from the external device 8 is fetched in the microprocessors 11 and 12 at the same time and stored in input buffers. Once the task requests the input data, synchronism data is generated and the received data of both systems are collated with each other and then used for the task.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention allows two microprocessors to simultaneously execute the same process in parallel, checks the execution results of both microprocessors for consistency, and detects whether one of the microprocessors has failed. The present invention relates to a task control method for a multi-microprocessor system in which the microprocessor of another thread automatically operates independently and continues processing when the microprocessor of the other thread is automatically operated independently.

The operating system (hereinafter abbreviated as O8) in a multi-microprocessor system has a task control function that performs priority processing and parallel processing of tasks, but conventional task control methods use a single computer system as the A symbol. A general task control method based on a dual system has not been proposed.

In order to realize a dual system using a conventional OS, for example, as shown in FIG. 1, the main microprocessor 1. A system in which a common computer clock is supplied to both slave microprocessors 2 by a clock generator 7, synchronized at the clock level, and a synchronization monitoring device 6 monitors the synchronized operation when data is transferred with an external input/output device 5. There is no need for synchronization processing by software, but it is the main system.

This has the disadvantage that synchronized processing cannot be performed if a timing difference occurs between the slave microprocessors 1 and 2.

The present invention has been made in view of the above-mentioned problems. Two independent microprocessors are each provided with a synchronous board, and the surface synchronous boards 1- are connected by a synchronous data transfer line.
Normally, both microprocessors operate independently, and at the point when data from an external device is connected to the task and transferred to the task, or taken out of the task and transferred to the external device,
The objective is to provide a task control method that allows synchronization to be performed even if the processing time of each microprocessor is significantly different and there is a timing lag between the two, by synchronizing based on the judgment of the main system. It is.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a block diagram showing an embodiment of the present invention, in which a main microprocessor 11° and a slave microprocessor 12 are connected to an external device 8, and each microprocessor 1'1. Data transmitting/receiving device 13.1
4 are coupled, and these are coupled by a synchronous data transfer line 15 to form a synchronous port.

Input data from the external device 8 is simultaneously transferred to the main and slave microprocessors 11 and 12 and stored in the input novel sofa. Synchronous data is generated when a task requests input data, and is used by the task after the received data is verified between both threads via a synchronization port.

The output data to the external device 8 is outputted to the external device 8 only from the main microprocessor 1 after collation is performed on both threads as in the case of input.

FIG. 3 is a diagram showing the flow of the task control method of the present invention, and the details of the operation of the inventive method will be explained below.

When performing data transfer processing with an external device, a synchronization code for the transfer data is generated in both the main and slave macro processors 11 and 12. The synchronization code is generally a sum code that sums the transferred data byte by byte.

Next, the conventional microprocessor 12 transfers the synchronization code ' to the main macroprocessor 5 base 11 via the synchronization board 1-, and receives an ACK from the main microprocessor 11.
Wait until the response code is input before proceeding to the next process.

At this time, if no response code is input from the main microprocessor 11 after waiting a certain period of time, or if an ACK1 code indicating an independent operation instruction is input, the main microprocessor 11 is assumed to be at fault, and the slave microprocessor 11 12 continues processing alone. If a NAK code indicating that the slave microprocessor 12 is at fault is input, the slave microprocessor 12 is prohibited from continuing the process.

The main microprocessor 11 compares the synchronization code from the slave microprocessor 12 with its own synchronization code, and if they match, transfers the human CK code to the slave microprocessor 12 via the synchronization port. , processing continues.If the result of comparison and verification shows that there is a mismatch, the main microprocessor 11 checks its own function, and if the self function is correct, it sends the NAK code to the slave microprocessor 1.
2, and the subsequent processing is carried out by the main macrocro processor 11.
6 l:, -: If there is an error in the function, it sends the AlK1 code to the slave microprocessor 12, considers itself to be a failure, and prohibits further processing. If the synchronization code is not received from the slave microprocessor 12 even after waiting for a certain period of time, the slave microprocessor 12 is regarded as a failure and the master microprocessor 11 continues processing independently.

As explained above, according to the present invention, two microprocessors each having a synchronization port are normally operated independently, and when data is transferred to an external device, synchronization is achieved based on the judgment of one of the microprocessors. Since one microprocessor has an asynchronous task in which it performs its own processing, it enables synchronized processing even in a dual system system where the synchronization timing of both systems is significantly different, and its industrial value is great.

Although a dual system system has been described in the embodiment, the present invention can also be applied to other types of microprocessor systems.

[Brief explanation of the drawing]

Fig. 3 is a block diagram showing the configuration of a conventional dual-system multiprocessor system, Fig. 2 is a block diagram showing the Tanuk control method of the multiprocessor system according to an embodiment of the present invention, and Fig. 3 is a block diagram showing the configuration of a conventional dual-system multiprocessor system. This is a flowchart 1- showing the procedure. 1...Main processor, 2...Slave processor, 3.4...External input/output interface, 5...External input/output device, 6... ...Synchronization monitoring device, completed... Chronokun Enerator, 8.
...External input/output device, 9.10...External input/output interface, 11...Main processor, 12...Slave processor, 13.14...
- Synchronous data transmitting/receiving device, 15... Synchronous data transfer line. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 5

Claims (1)

[Claims] A first and a second microprocessor, each comprising a synchronization port connected to the two microprocessors, and a synchronization data transfer line connecting the two synchronization ports, each of which functions to carry out arithmetic processing of the two microprocessors. dividing the unit into tasks, and when the task requests data transfer with an external device, synchronous data is transferred from the first microprocessor to the second microprocessor via the synchronous port; A task control method for a multiprocessor system characterized by synchronization based on the judgment of a second microprocessor.