JPS6118168A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a chip size through decreasing the number of elements and improving an integration degree by unifying on an element forming region a clamp diode and a collector resistance of a differential transistor in an ECL circuit. CONSTITUTION:A bipolar transistor constructing a differential transistor in an ECL circuit is formed in element forming regions 5b and 5c, an element unified by a collector resistance and a clamp diode is formed in an element forming region 5a. As the number of elements constructing a circuit decreases, an occupied area of an isolation region isolating elements each other can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor technology, and relates to a technology that is effective for use in, for example, an element that clamps an output voltage in an ECL circuit (emitter-coupled logic circuit).

[Background Art] Conventionally, in a logic LSI (large scale integrated circuit) whose basic circuit is an ECL circuit, a circuit as shown in Fig. 1 has been proposed in order to clamp the low level of the output voltage of the ECL circuit (IEEE JOURNAL OF
5OLID-8TATBCIRCUITS, VOL, 5
C-14, No. 5゜0CTOBER1979, No. 81
(See pages 8-819).

That is, this ECL circuit has a resistor R on the collector side of the transistor T1 to which the reference voltage Vref is applied to the base.
ci is connected, and input transistors T2 to T4 whose emitters are commonly connected in parallel with this transistor T1
A resistor Reo is connected to the collector side of the resistor Reo. Clamp diodes Di and Do are connected in parallel with these collector resistors Rci and Rco, respectively, between the power supply voltage Vcc and the output node n 1 + n'2.

This clamps the low level of the output of the ECL circuit.

For example, consider a case where the output nodes ni and n2 of the ECL circuit are connected to the output nodes of another ECL circuit so as to form a wired AND.

Then, the two transistors commonly connected to the output nodes nl and n2 may both be turned on, and a low-level output voltage may be output. In such a case, a large current may flow through the collector resistor Rci or Rco, causing the output node n1 or n2 to drop below the desired output voltage low level. At this time, the diode Di.

By allowing current to flow through DO, the output voltage can be clamped to a voltage lower than the power supply voltage Vcc by the threshold voltage of the diode. This makes it possible to prevent the low level of the output voltage from dropping below a desired voltage (ECL level).

By the way, when forming an ECL circuit as described above on one semiconductor substrate, clamp diodes Di and D are generally used.
o is constructed by short-circuiting the pace and collector of bipolar transistors formed in the same manner as the transistors T1 to T4, and using a PN junction between the base and emitter.

In addition, the collector resistors Rci and Rco are usually constituted by a diffusion layer formed on a semiconductor substrate.

However, transistors T, ~T4. Clamp diodes Di, Do and collector resistance Rci.

When the elements constituting Rco are formed separately using transistors and diffusion layers as described above, it is necessary to separate each element with an isolation oxide film such as LOGO5, which occupies a relatively large area. As a result, there is a risk that the degree of integration of the elements will decrease and the chip size will increase.

[Object of the Invention] An object of the present invention is to provide a semiconductor element (resistance) that can exhibit a voltage clamping effect without increasing the chip size.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, for example, in an ECL circuit, a diffusion layer that constitutes the collector resistance of a differential transistor constituting the circuit is formed in a diagonal shape on an element formation region surrounded by an isolation region. By keeping both ends of the diffusion layer facing each other with a predetermined distance apart, when the voltage applied to both ends of the diffusion layer exceeds a certain level, a breakdown occurs and a short circuit occurs. The above objectives of reducing the number of elements by integrally forming a resistor and a clamp diode on one element formation region, improving the degree of integration, and reducing the chip size are achieved.

[Example] FIG. 2 shows an example of the present invention in which a collector resistor Rci (or Rco) and a clamp diode Di (or Do) constituting an ECL circuit as shown in FIG. 1 are integrally formed as one element. FIG. 3 is a plan view showing one embodiment of the semiconductor device, and FIG. 3 is a cross-sectional view thereof.

In this embodiment, although not particularly limited, N+ buried layers 2a and 2b are partially formed on a semiconductor substrate 1 made of, for example, P-type crystalline silicon in a portion where a semiconductor element is to be formed; An N-type epitaxial layer 3 is formed over the entire surface by vapor phase growth. Then, the surface of the portion of the N-type epitaxial layer 3 that will become the element isolation region is etched until the thickness of the layer is reduced to about half, and then thermal oxidation is performed to form a relatively thick isolation oxide film 4. is formed. Thereby, element forming regions 5a, 5b, and 5c are formed, which are surrounded by the isolation oxide film 4 and are made of epitaxial layers separated from each other.

In the element formation regions 5b and 5c, bibolar transistors constituting the differential transistors T1 to T4 of the ECL circuit are formed, and in the element formation region 5a, a collector resistor Rci (Rco) and a clamp diode Di (Do
) are integrated into an element.

That is, on the main surface of the substrate in the element formation region 5a, a collector resistance is formed by ion implantation and diffusion of P-type impurities, which is performed simultaneously with the formation of the base region 6 of the bipolar transistor formed in the element formation region 5b. A P-type diffusion layer 7 is formed.

Although not particularly limited, this P-type diffusion layer 7 is formed to have an approximately U-shape as a whole, as shown in FIG.
, 7b are formed.

Then, at both ends of this diffusion layer 7, an ECL shown in FIG.
A power supply line supplying the power supply voltage VCC of the circuit and an aluminum wiring layer constituting a signal line connected to the collector of the transistor T1 or (T2 to Ta) are respectively contacted.

In FIG. 3, reference numerals 8 and 9 indicate the N-type emitter region and collector pull-up port of the bipolar transistor, respectively.

According to the embodiment described above, when the voltage applied between both ends of the P-type diffusion layer 7 exceeds a certain level, the P-type between the N-type epitaxial layer 3 and the diffusion layer 7 constituting the element formation region 5a
The N-junction breaks down and both ends are shorted,
Current flows. In other words, until the voltage applied between both terminals reaches the breakdown voltage, the element made of the P-type diffusion layer 7 acts as a resistance element through which a current proportional to the voltage flows, as shown in FIG. . When the voltage between both terminals exceeds the breakdown voltage, a large current suddenly begins to flow, acting as a clamp diode that keeps the voltage between both terminals approximately constant.

Furthermore, in the above case, by setting the distance between the bulges 7a and 7b provided at both ends of the diffusion layer 7 to an appropriate distance, the voltage that causes breakdown can be controlled.

Therefore, should the above embodiment be applied? = E In the CL circuit,
When configuring a circuit that has a function of clamping the low level of the output voltage, there is no need to form the collector resistor and the clamp diode in separate regions, and they can be formed as one element. As a result, the number of elements constituting the circuit can be reduced, and the area occupied by isolation regions separating each element can be reduced. By this, E CL
Logic LS consisting of ECL circuit with improved circuit integration
It becomes possible to reduce the chip size of I.

In the above embodiment, the bulges 7a are provided at both ends of the diffusion layer 7.
, 7b are formed, charges are more likely to be concentrated in this portion than in the case where no bulging portion is formed, and breakdown is more likely to occur.

However, it is also possible to omit these bulging portions 7a and 7b. Further, in order to further facilitate breakdown, the bulging portions 7a and 7b may be formed to have a sharper shape.

Further, in the above embodiment, the planar shape of the diffusion layer 7 is U-shaped, but the planar shape is not limited to this, and it may be formed in a C-shape or a partially cut ring shape. You may. Moreover, in the above embodiment, the inner part of the diffusion layer 7 (the region indicated by the symbol F in FIG. 2) is left as the N-type epitaxial layer 3, but an isolation oxide film is formed on this part. can also be formed. Alternatively, if a very large resistance value is required and the total length of the diffusion layer 7 becomes long, it is also possible to configure other elements in the region surrounded by the diffusion layer 7.

Furthermore, in the above embodiment, a desired breakdown voltage is obtained by mainly adjusting the distance between both ends of the diffusion layer 7, that is, the interval between the bulges 7a and 7b, but the diffusion layer 7 is not formed. The breakdown voltage may be controlled by adjusting the concentration of the epitaxial layer 3 in advance.

[Effect] In an LSI having an ECL circuit, the collector resistance of the differential transistor that constitutes the ECL circuit is constructed by forming a diffusion layer in a substantially U-shape on an element formation region surrounded by an isolation region. However, since the both ends of the diffusion layer are kept facing each other with a predetermined distance apart, when the voltage at both ends of the diffusion layer exceeds a certain level, breakdown occurs between the diffusion layer and the substrate, and the diffusion layer The collector resistor and clamp diode can be integrally formed as one element by short-circuiting both terminals of the E.
This has the effect of reducing the chip size of an LSI having a CL circuit.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above example,
Although the P-type diffusion layer 7 constitutes an element in which the collector resistor and the clamp diode are integrated, this diffusion layer can also be an N-type diffusion layer formed in a suitable region of the substrate. Further, in the embodiment, each element is separated by an oxide film using an isoplanar, but the element isolation region may be a separate body using LOC:O8 or trench isolation method.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to an integrated circuit consisting of an ECL circuit, which is the field of application that formed the background of the invention, but the invention is not limited thereto. It can be used in all semiconductor integrated circuits that have circuits that require clamping when the voltage drop amount exceeds a certain level.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of the configuration of a conventional ECL circuit; FIG. 2 is a plan view showing an embodiment of a semiconductor element in which a resistor and a clamp diode are integrated according to the present invention; The figure is a sectional view showing an example of the structure of the device and the bipolar transistor, and FIG. 4 is an explanatory diagram showing the characteristics of the semiconductor device according to the present invention. T1 to T4...Differential transistor, Rci. Rco-collector resistor, Di, Do...clamp diode, 1...semiconductor substrate, 2a, 2b...
N-type buried layer, 3...N- type epitaxial layer, 4.
...Isolation region (isolation oxide film), 5a to 5c...
Element formation region, 6...Base region, 7...Semiconductor layer (diffusion layer), 7a, 7b...Bulging portion, 8...
・Emitter area, 9...Collector pull-up port. Figure 1 Figure 2

Claims (1)

[Claims] 1. The resistance element is formed by a semiconductor layer formed in an annular shape on the main surface of a semiconductor substrate so that both ends thereof face each other with a predetermined distance between them. Semiconductor equipment. 2. The semiconductor layer is a diffusion layer formed at the same time as the base region of the bipolar transistor inside an element formation region surrounded by an isolation region. Semiconductor equipment. 3. Claim 1, wherein the semiconductor layer is used as a collector resistor of a differential transistor constituting an emitter-coupled logic circuit.
The semiconductor device according to item 1 or 2.